41 		.start = 0x800,
42 		.end	= 0x9ff,
52 #define SCR_REVID	0x08		/* b Revision ID	*/
53 #define SCR_IMR		0x42		/* b Interrupt Mask	*/
54 #define SCR_DEV_CTL	0xe0		/* b Device control	*/
55 #define SCR_ISR		0xe1		/* b Interrupt Status	*/
56 #define SCR_GPO_OC	0xf0		/* b GPO output control	*/
57 #define SCR_GPO_OS	0xf1		/* b GPO output enable	*/
58 #define SCR_GPI_S	0xf2		/* w GPI status		*/
59 #define SCR_APDC	0xf8		/* b Active pullup down ctrl */
61 #define SCR_DEV_CTL_USB		BIT(0)	/* USB enable		*/
99 	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,  in t7l66xb_mmc_enable()
100 		t7l66xb_mmc_resources[0].start & 0xfffe);  in t7l66xb_mmc_enable()
102 	return 0;  in t7l66xb_mmc_enable()
121 	return 0;  in t7l66xb_mmc_disable()
128 	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);  in t7l66xb_mmc_pwr()
135 	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);  in t7l66xb_mmc_clk_div()
148 		.start	= 0xc00,
149 		.end	= 0xc07,
153 		.start	= 0x0100,
154 		.end	= 0x01ff,
194 		for (i = 0; i < T7L66XB_NR_IRQS; i++)  in t7l66xb_irq()
278 	return 0;  in t7l66xb_suspend()
294 	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,  in t7l66xb_resume()
295 		t7l66xb_mmc_resources[0].start & 0xfffe);  in t7l66xb_resume()
297 	return 0;  in t7l66xb_resume()
316 	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);  in t7l66xb_probe()
328 	ret = platform_get_irq(dev, 0);  in t7l66xb_probe()
329 	if (ret >= 0)  in t7l66xb_probe()
351 	rscr->end = iomem->start + 0xff;  in t7l66xb_probe()
372 	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);  in t7l66xb_probe()
374 	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",  in t7l66xb_probe()
388 		return 0;  in t7l66xb_probe()