Lines Matching +full:0 +full:xfffe
9 #define CNF_CMD 0x04
10 #define CNF_CTL_BASE 0x10
11 #define CNF_INT_PIN 0x3d
12 #define CNF_STOP_CLK_CTL 0x40
13 #define CNF_GCLK_CTL 0x41
14 #define CNF_SD_CLK_MODE 0x42
15 #define CNF_PIN_STATUS 0x44
16 #define CNF_PWR_CTL_1 0x48
17 #define CNF_PWR_CTL_2 0x49
18 #define CNF_PWR_CTL_3 0x4a
19 #define CNF_CARD_DETECT_MODE 0x4c
20 #define CNF_SD_SLOT 0x50
21 #define CNF_EXT_GCLK_CTL_1 0xf0
22 #define CNF_EXT_GCLK_CTL_2 0xf1
23 #define CNF_EXT_GCLK_CTL_3 0xf9
24 #define CNF_SD_LED_EN_1 0xfa
25 #define CNF_SD_LED_EN_2 0xfe
27 #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
33 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_enable()
36 sd_config_write8(cnf, shift, CNF_PWR_CTL_3, 0x01); in tmio_core_mmc_enable()
39 sd_config_write8(cnf, shift, CNF_STOP_CLK_CTL, 0x1f); in tmio_core_mmc_enable()
42 sd_config_write8(cnf, shift, CNF_PWR_CTL_2, 0x00); in tmio_core_mmc_enable()
44 return 0; in tmio_core_mmc_enable()
53 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_resume()
55 return 0; in tmio_core_mmc_resume()
61 sd_config_write8(cnf, shift, CNF_PWR_CTL_2, state ? 0x02 : 0x00); in tmio_core_mmc_pwr()
67 sd_config_write8(cnf, shift, CNF_SD_CLK_MODE, state ? 1 : 0); in tmio_core_mmc_clk_div()