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/Linux-v5.10/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.txt75 reg = <0x0 0x30000000 0x0 0x50000>;
78 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
82 reg = <0x0 0x4e000 0x0 0x1000>;
89 reg = <0x0 0x4f000 0x0 0x1000>;
/Linux-v5.10/Documentation/devicetree/bindings/usb/
Dehci-orion.txt20 reg = <0x50000 0x1000>;
/Linux-v5.10/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi14 bus@0 {
19 ranges = <0x0 0x0 0x0 0x40000000>;
23 reg = <0x00100000 0xf000>,
24 <0x0010f000 0x1000>;
30 reg = <0x03100000 0x10000>;
41 reg = <0x03460000 0x20000>;
53 reg = <0x03810000 0x10000>;
60 reg = <0x03c00000 0xa0000>;
78 reg = <0x0c150000 0x90000>;
84 * Shared interrupt 0 is routed only to AON/SPE, so
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dpicoxcell-pc3x2.dtsi12 #address-cells = <0>;
13 #size-cells = <0>;
31 pclk: clock@0 {
43 ranges = <0 0x80000000 0x400000>;
47 reg = <0x30000 0x10000>;
53 reg = <0x40000 0x10000>;
59 reg = <0x50000 0x10000>;
66 reg = <0x60000 0x1000>;
73 reg = <0x64000 0x1000>;
79 reg = <0x80000 0x10000>;
[all …]
Dspear600-evb.dts17 reg = <0 0x10000000>;
55 reg = <0xf8000000 0x800000>;
63 partition@0 {
65 reg = <0x0 0x10000>;
69 reg = <0x10000 0x50000>;
73 reg = <0x60000 0x10000>;
77 reg = <0x70000 0x10000>;
81 reg = <0x80000 0x310000>;
85 reg = <0x390000 0x0>;
Dpicoxcell-pc3x3.dtsi12 #address-cells = <0>;
13 #size-cells = <0>;
33 #size-cells = <0>;
34 reg = <0x800a0048 4>;
37 tzprot_clk: clock@0 {
40 picochip,clk-disable-bit = <0>;
120 reg = <0x800a0050 0x8>;
139 ranges = <0 0x80000000 0x400000>;
143 reg = <0x30000 0x10000>;
150 reg = <0x40000 0x10000>;
[all …]
Dat91rm9200ek.dts19 reg = <0x20000000 0x4000000>;
35 timer@0 {
37 reg = <0>, <1>;
63 pinctrl-0 =
75 cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
76 mtd_dataflash@0 {
79 reg = <0>;
99 reg = <0x10000000 0x800000>;
100 linux,mtd-name = "physmap-flash.0";
105 barebox@0 {
[all …]
Dspear310-evb.dts18 reg = <0 0x40000000>;
24 pinctrl-0 = <&state_default>;
102 reg = <0xf8000000 0x800000>;
105 partition@0 {
107 reg = <0x0 0x10000>;
111 reg = <0x10000 0x50000>;
115 reg = <0x60000 0x10000>;
119 reg = <0x70000 0x10000>;
123 reg = <0x80000 0x310000>;
127 reg = <0x390000 0x0>;
[all …]
Dspear320-evb.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
103 reg = <0xf8000000 0x800000>;
106 partition@0 {
108 reg = <0x0 0x10000>;
112 reg = <0x10000 0x50000>;
116 reg = <0x60000 0x10000>;
120 reg = <0x70000 0x10000>;
124 reg = <0x80000 0x310000>;
128 reg = <0x390000 0x0>;
[all …]
/Linux-v5.10/arch/mips/boot/dts/ralink/
Drt2880_eval.dts10 memory@0 {
12 reg = <0x8000000 0x2000000>;
21 reg = <0x1f000000 0x400000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x3b0000>;
Drt3052_eval.dts10 memory@0 {
12 reg = <0x0 0x2000000>;
21 reg = <0x1f000000 0x800000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x7b0000>;
/Linux-v5.10/drivers/crypto/
Dgeode-aes.h9 #define AES_MODE_ECB 0
12 #define AES_DIR_DECRYPT 0
15 #define AES_FLAGS_HIDDENKEY (1 << 0)
19 #define AES_CTRLA_REG 0x0000
21 #define AES_CTRL_START 0x01
22 #define AES_CTRL_DECRYPT 0x00
23 #define AES_CTRL_ENCRYPT 0x02
24 #define AES_CTRL_WRKEY 0x04
25 #define AES_CTRL_DCA 0x08
26 #define AES_CTRL_SCA 0x10
[all …]
/Linux-v5.10/arch/arm/mach-orion5x/
Dorion5x.h39 #define ORION5X_REGS_PHYS_BASE 0xf1000000
40 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
43 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
44 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
47 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
48 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
51 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
55 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
56 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
59 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/Linux-v5.10/arch/arm/mach-mmp/
Daddr-map.h15 #define APB_PHYS_BASE 0xd4000000
16 #define APB_VIRT_BASE IOMEM(0xfe000000)
17 #define APB_PHYS_SIZE 0x00200000
19 #define AXI_PHYS_BASE 0xd4200000
20 #define AXI_VIRT_BASE IOMEM(0xfe200000)
21 #define AXI_PHYS_SIZE 0x00200000
23 #define PGU_PHYS_BASE 0xe0000000
24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
25 #define PGU_PHYS_SIZE 0x00100000
27 /* Static Memory Controller - Chip Select 0 and 1 */
[all …]
/Linux-v5.10/drivers/gpu/drm/msm/adreno/
Da6xx_hfi.c34 return 0; in a6xx_hfi_queue_read()
50 for (i = 0; i < HFI_HEADER_SIZE(hdr); i++) { in a6xx_hfi_queue_read()
78 for (i = 0; i < dwords; i++) { in a6xx_hfi_queue_write()
86 queue->data[index] = 0xfafafafa; in a6xx_hfi_queue_write()
92 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
93 return 0; in a6xx_hfi_queue_write()
161 return 0; in a6xx_hfi_wait_for_ack()
172 seqnum = atomic_inc_return(&queue->seqnum) % 0xfff; in a6xx_hfi_send_msg()
190 struct a6xx_hfi_msg_gmu_init_cmd msg = { 0 }; in a6xx_hfi_send_gmu_init()
197 NULL, 0); in a6xx_hfi_send_gmu_init()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/msm/
Dqcom,llcc.yaml54 reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
/Linux-v5.10/arch/arm64/boot/dts/freescale/
Dqoriq-bman-portals.dtsi14 bman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
26 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
32 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
38 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
44 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
50 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
56 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
62 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
68 reg = <0x80000 0x4000>, <0x4080000 0x4000>;
[all …]
Dqoriq-qman-portals.dtsi14 qportal0: qman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
22 cell-index = <0>;
27 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
34 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
41 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
48 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
55 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
62 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
69 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
[all …]
/Linux-v5.10/include/uapi/linux/genwqe/
Dgenwqe_card.h36 #define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
37 #define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
38 #define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
39 #define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
43 #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
49 #define IO_EXTENDED_ERROR_POINTER 0x00000048
50 #define IO_ERROR_INJECT_SELECTOR 0x00000060
51 #define IO_EXTENDED_DIAG_SELECTOR 0x00000070
52 #define IO_EXTENDED_DIAG_READ_MBX 0x00000078
53 #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
[all …]
/Linux-v5.10/drivers/staging/mt7621-dts/
Dgbpc1.dts12 memory@0 {
14 reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
69 m25p80@0 {
73 reg = <0>;
77 partition@0 {
79 reg = <0x0 0x30000>;
85 reg = <0x30000 0x10000>;
91 reg = <0x40000 0x10000>;
97 reg = <0x50000 0x1FB0000>;
116 pinctrl-0 = <&pcie_pins>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dqcom,sc7180-lpasscorecc.yaml87 reg = <0x63000000 0x28>;
100 reg = <0x62d00000 0x50000>, <0x62780000 0x30000>;
/Linux-v5.10/arch/powerpc/boot/dts/fsl/
Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
/Linux-v5.10/arch/arm/mach-mv78xx0/
Dmv78xx0.h20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra186-mc.yaml27 pattern: "^memory-controller@[0-9a-f]+$"
52 "^external-memory-controller@[0-9a-f]+$":
106 reg = <0x0 0x02c00000 0x0 0xb0000>;
112 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
118 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
122 reg = <0x0 0x02c60000 0x0 0x50000>;

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