Lines Matching +full:0 +full:x50000
36 #define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
37 #define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
38 #define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
39 #define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
43 #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
49 #define IO_EXTENDED_ERROR_POINTER 0x00000048
50 #define IO_ERROR_INJECT_SELECTOR 0x00000060
51 #define IO_EXTENDED_DIAG_SELECTOR 0x00000070
52 #define IO_EXTENDED_DIAG_READ_MBX 0x00000078
53 #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
57 /* UnitID 0: Service Layer Unit (SLU) */
60 #define IO_SLU_UNITCFG 0x00000000
61 #define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 /* 27:20 */
64 #define IO_SLU_FIR 0x00000008 /* read only, wr direct */
65 #define IO_SLU_FIR_CLR 0x00000010 /* read and clear */
68 #define IO_SLU_FEC 0x00000018
70 #define IO_SLU_ERR_ACT_MASK 0x00000020
71 #define IO_SLU_ERR_ATTN_MASK 0x00000028
72 #define IO_SLU_FIRX1_ACT_MASK 0x00000030
73 #define IO_SLU_FIRX0_ACT_MASK 0x00000038
74 #define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040
75 #define IO_SLU_EXTENDED_ERR_PTR 0x00000048
76 #define IO_SLU_COMMON_CONFIG 0x00000060
78 #define IO_SLU_FLASH_FIR 0x00000108
79 #define IO_SLU_SLC_FIR 0x00000110
80 #define IO_SLU_RIU_TRAP 0x00000280
81 #define IO_SLU_FLASH_FEC 0x00000308
82 #define IO_SLU_SLC_FEC 0x00000310
85 * The Virtual Function's Access is from offset 0x00010000
86 * The Physical Function's Access is from offset 0x00050000
87 * Single Shared Registers exists only at offset 0x00060000
90 * queue. When accessing the 0x10000 space using the 0x50000 address
92 * register is decoded. This register, and the 0x50000 register space
94 * 0x2, then a read from 0x50000 is the same as a read from 0x10000
99 #define IO_SLC_QUEUE_SEGMENT 0x00010000
100 #define IO_SLC_VF_QUEUE_SEGMENT 0x00050000
103 #define IO_SLC_QUEUE_OFFSET 0x00010008
104 #define IO_SLC_VF_QUEUE_OFFSET 0x00050008
107 #define IO_SLC_QUEUE_CONFIG 0x00010010
108 #define IO_SLC_VF_QUEUE_CONFIG 0x00050010
111 #define IO_SLC_APPJOB_TIMEOUT 0x00010018
112 #define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018
113 #define TIMEOUT_250MS 0x0000000f
114 #define HEARTBEAT_DISABLE 0x0000ff00
117 #define IO_SLC_QUEUE_INITSQN 0x00010020
118 #define IO_SLC_VF_QUEUE_INITSQN 0x00050020
121 #define IO_SLC_QUEUE_WRAP 0x00010028
122 #define IO_SLC_VF_QUEUE_WRAP 0x00050028
125 #define IO_SLC_QUEUE_STATUS 0x00010100
126 #define IO_SLC_VF_QUEUE_STATUS 0x00050100
129 #define IO_SLC_QUEUE_WTIME 0x00010030
130 #define IO_SLC_VF_QUEUE_WTIME 0x00050030
133 #define IO_SLC_QUEUE_ERRCNTS 0x00010038
134 #define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038
137 #define IO_SLC_QUEUE_LRW 0x00010040
138 #define IO_SLC_VF_QUEUE_LRW 0x00050040
141 #define IO_SLC_FREE_RUNNING_TIMER 0x00010108
142 #define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108
145 #define IO_PF_SLC_VIRTUAL_REGION 0x00050000
148 #define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000
150 /* SLC: DDCB Application Job Pending [n] (n=0:63) */
151 #define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8*(n))
154 /* SLC: Parser Trap RAM [n] (n=0:31) */
155 #define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8*(n))
157 /* SLC: Dispatcher Trap RAM [n] (n=0:31) */
158 #define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8*(n))
161 #define IO_SLC_CFGREG_GFIR 0x00020000
162 #define GFIR_ERR_TRIGGER 0x0000ffff
165 #define IO_SLC_CFGREG_SOFTRESET 0x00020018
168 #define IO_SLC_MISC_DEBUG 0x00020060
169 #define IO_SLC_MISC_DEBUG_CLR 0x00020068
170 #define IO_SLC_MISC_DEBUG_SET 0x00020070
173 #define IO_SLU_TEMPERATURE_SENSOR 0x00030000
174 #define IO_SLU_TEMPERATURE_CONFIG 0x00030008
177 #define IO_SLU_VOLTAGE_CONTROL 0x00030080
178 #define IO_SLU_VOLTAGE_NOMINAL 0x00000000
179 #define IO_SLU_VOLTAGE_DOWN5 0x00000006
180 #define IO_SLU_VOLTAGE_UP5 0x00000007
183 #define IO_SLU_LEDCONTROL 0x00030100
186 #define IO_SLU_FLASH_DIRECTACCESS 0x00040010
189 #define IO_SLU_FLASH_DIRECTACCESS2 0x00040020
192 #define IO_SLU_FLASH_CMDINTF 0x00040030
195 #define IO_SLU_BITSTREAM 0x00040040
198 #define IO_HSU_ERR_BEHAVIOR 0x01001010
200 #define IO_SLC2_SQB_TRAP 0x00062000
201 #define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008
202 #define IO_SLC2_FLS_MASTER_TRAP 0x00062010
205 #define IO_HSU_UNITCFG 0x01000000
206 #define IO_HSU_FIR 0x01000008
207 #define IO_HSU_FIR_CLR 0x01000010
208 #define IO_HSU_FEC 0x01000018
209 #define IO_HSU_ERR_ACT_MASK 0x01000020
210 #define IO_HSU_ERR_ATTN_MASK 0x01000028
211 #define IO_HSU_FIRX1_ACT_MASK 0x01000030
212 #define IO_HSU_FIRX0_ACT_MASK 0x01000038
213 #define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040
214 #define IO_HSU_EXTENDED_ERR_PTR 0x01000048
215 #define IO_HSU_COMMON_CONFIG 0x01000060
218 #define IO_APP_UNITCFG 0x02000000
219 #define IO_APP_FIR 0x02000008
220 #define IO_APP_FIR_CLR 0x02000010
221 #define IO_APP_FEC 0x02000018
222 #define IO_APP_ERR_ACT_MASK 0x02000020
223 #define IO_APP_ERR_ATTN_MASK 0x02000028
224 #define IO_APP_FIRX1_ACT_MASK 0x02000030
225 #define IO_APP_FIRX0_ACT_MASK 0x02000038
226 #define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040
227 #define IO_APP_EXTENDED_ERR_PTR 0x02000048
228 #define IO_APP_COMMON_CONFIG 0x02000060
230 #define IO_APP_DEBUG_REG_01 0x02010000
231 #define IO_APP_DEBUG_REG_02 0x02010008
232 #define IO_APP_DEBUG_REG_03 0x02010010
233 #define IO_APP_DEBUG_REG_04 0x02010018
234 #define IO_APP_DEBUG_REG_05 0x02010020
235 #define IO_APP_DEBUG_REG_06 0x02010028
236 #define IO_APP_DEBUG_REG_07 0x02010030
237 #define IO_APP_DEBUG_REG_08 0x02010038
238 #define IO_APP_DEBUG_REG_09 0x02010040
239 #define IO_APP_DEBUG_REG_10 0x02010048
240 #define IO_APP_DEBUG_REG_11 0x02010050
241 #define IO_APP_DEBUG_REG_12 0x02010058
242 #define IO_APP_DEBUG_REG_13 0x02010060
243 #define IO_APP_DEBUG_REG_14 0x02010068
244 #define IO_APP_DEBUG_REG_15 0x02010070
245 #define IO_APP_DEBUG_REG_16 0x02010078
246 #define IO_APP_DEBUG_REG_17 0x02010080
247 #define IO_APP_DEBUG_REG_18 0x02010088
260 #define IO_ILLEGAL_VALUE 0xffffffffffffffffull
285 #define DDCB_ACFUNC_SLU 0x00 /* chip service layer unit */
286 #define DDCB_ACFUNC_APP 0x01 /* chip application */
289 #define DDCB_RETC_IDLE 0x0000 /* Unexecuted/DDCB created */
290 #define DDCB_RETC_PENDING 0x0101 /* Pending Execution */
291 #define DDCB_RETC_COMPLETE 0x0102 /* Cmd complete. No error */
292 #define DDCB_RETC_FAULT 0x0104 /* App Err, recoverable */
293 #define DDCB_RETC_ERROR 0x0108 /* App Err, non-recoverable */
294 #define DDCB_RETC_FORCED_ERROR 0x01ff /* overwritten by driver */
296 #define DDCB_RETC_UNEXEC 0x0110 /* Unexe/Removed from queue */
297 #define DDCB_RETC_TERM 0x0120 /* Terminated */
298 #define DDCB_RETC_RES0 0x0140 /* Reserved */
299 #define DDCB_RETC_RES1 0x0180 /* Reserved */
302 #define DDCB_OPT_ECHO_FORCE_NO 0x0000 /* ECHO DDCB */
303 #define DDCB_OPT_ECHO_FORCE_102 0x0001 /* force return code */
304 #define DDCB_OPT_ECHO_FORCE_104 0x0002
305 #define DDCB_OPT_ECHO_FORCE_108 0x0003
307 #define DDCB_OPT_ECHO_FORCE_110 0x0004 /* only on PF ! */
308 #define DDCB_OPT_ECHO_FORCE_120 0x0005
309 #define DDCB_OPT_ECHO_FORCE_140 0x0006
310 #define DDCB_OPT_ECHO_FORCE_180 0x0007
312 #define DDCB_OPT_ECHO_COPY_NONE (0 << 5)
316 #define SLCMD_ECHO_SYNC 0x00 /* PF/VF */
317 #define SLCMD_MOVE_FLASH 0x06 /* PF only */
318 #define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 /* bit 0 and 1 used for mode */
319 #define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 /* mode: download */
329 GENWQE_CARD_UNUSED = 0,
342 __u32 partition; /* '0', '1', or 'v' */
380 * offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78
385 #define ATS_TYPE_DATA 0x0ull /* data */
386 #define ATS_TYPE_FLAT_RD 0x4ull /* flat buffer read only */
387 #define ATS_TYPE_FLAT_RDWR 0x5ull /* flat buffer read/write */
388 #define ATS_TYPE_SGL_RD 0x6ull /* sgl read only */
389 #define ATS_TYPE_SGL_RDWR 0x7ull /* sgl read/write */
392 (((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8))))
395 (((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf)
442 #define GENWQE_IOC_CODE 0xa5
458 * direction: 0: read/1: read and write
486 * Return: 0 on success or negative error code.