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Searched +full:0 +full:x46000 (Results 1 – 19 of 19) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/phy/
Damlogic,meson-g12a-usb3-pcie-phy.yaml53 reg = <0x46000 0x2000>;
/Linux-v6.1/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.c70 #define MERGE_3D_SM8150_MASK (0)
76 #define INTF_SDM845_MASK (0)
268 .max_mixer_blendstages = 0x7,
284 .max_mixer_blendstages = 0x4,
295 .max_mixer_blendstages = 0xb,
311 .max_mixer_blendstages = 0x9,
323 .max_mixer_blendstages = 0xb,
339 .max_mixer_blendstages = 0xb,
355 .max_mixer_blendstages = 0xb,
369 .max_mixer_blendstages = 0x7,
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dp4080si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/Linux-v6.1/drivers/soc/tegra/cbb/
Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
31 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
32 #define FABRIC_EN_CFG_STATUS_0_0 0x40
33 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
34 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
35 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
37 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
38 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
39 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
40 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/Linux-v6.1/drivers/clk/qcom/
Dgcc-mdm9607.c38 .offset = 0x21000,
41 .enable_reg = 0x45000,
42 .enable_mask = BIT(0),
56 .offset = 0x21000,
68 { P_XO, 0 },
78 .l_reg = 0x20004,
79 .m_reg = 0x20008,
80 .n_reg = 0x2000c,
81 .config_reg = 0x20010,
82 .mode_reg = 0x20000,
[all …]
Dgcc-msm8909.c53 { P_XO, 0 },
65 .offset = 0x21000,
68 .enable_reg = 0x45000,
69 .enable_mask = BIT(0),
81 .offset = 0x21000,
95 .l_reg = 0x20004,
96 .m_reg = 0x20008,
97 .n_reg = 0x2000c,
98 .config_reg = 0x20010,
99 .mode_reg = 0x20000,
[all …]
Dgcc-qcs404.c42 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
84 { P_XO, 0 },
98 { P_XO, 0 },
110 { P_XO, 0 },
124 { P_XO, 0 },
138 { P_XO, 0 },
156 { P_XO, 0 },
168 { P_XO, 0 },
[all …]
Dgcc-msm8916.c46 .l_reg = 0x21004,
47 .m_reg = 0x21008,
48 .n_reg = 0x2100c,
49 .config_reg = 0x21010,
50 .mode_reg = 0x21000,
51 .status_reg = 0x2101c,
64 .enable_reg = 0x45000,
65 .enable_mask = BIT(0),
77 .l_reg = 0x20004,
78 .m_reg = 0x20008,
[all …]
Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
Dgcc-msm8953.c41 .offset = 0x21000,
44 .enable_reg = 0x45000,
45 .enable_mask = BIT(0),
71 .offset = 0x21000,
84 .offset = 0x4a000,
87 .enable_reg = 0x45000,
101 .offset = 0x4a000,
114 { 1000000000, 2000000000, 0 },
119 .config_ctl_val = 0x4001055b,
120 .early_output_mask = 0,
[all …]
Dgcc-ipq6018.c53 .offset = 0x21000,
56 .enable_reg = 0x0b000,
57 .enable_mask = BIT(0),
83 .offset = 0x21000,
103 { P_XO, 0 },
109 .offset = 0x25000,
113 .enable_reg = 0x0b000,
127 .offset = 0x25000,
141 .offset = 0x37000,
144 .enable_reg = 0x0b000,
[all …]
/Linux-v6.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12-common.dtsi106 reg = <0x0 0x05000000 0x0 0x300000>;
112 reg = <0x0 0x05300000 0x0 0x2000000>;
119 size = <0x0 0x10000000>;
120 alignment = <0x0 0x400000>;
137 reg = <0x0 0xfc000000 0x0 0x400000>,
138 <0x0 0xff648000 0x0 0x2000>,
139 <0x0 0xfc400000 0x0 0x200000>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
145 bus-range = <0x0 0xff>;
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/
Di915_reg.h105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
110 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
114 * #define BAR _MMIO(0xb000)
115 * #define GEN8_BAR _MMIO(0xb888)
122 * numbers, pick the 0-based __index'th value.
129 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
177 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
179 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
185 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
[all …]