Lines Matching +full:0 +full:x46000
54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
87 .n_reg = 0x2000c,
88 .config_reg = 0x20010,
89 .mode_reg = 0x20000,
90 .status_reg = 0x2001c,
103 .enable_reg = 0x45000,
116 .l_reg = 0x4a004,
117 .m_reg = 0x4a008,
118 .n_reg = 0x4a00c,
119 .config_reg = 0x4a010,
120 .mode_reg = 0x4a000,
121 .status_reg = 0x4a01c,
134 .enable_reg = 0x45000,
147 .l_reg = 0x23004,
148 .m_reg = 0x23008,
149 .n_reg = 0x2300c,
150 .config_reg = 0x23010,
151 .mode_reg = 0x23000,
152 .status_reg = 0x2301c,
165 .enable_reg = 0x45000,
178 .l_reg = 0x22004,
179 .m_reg = 0x22008,
180 .n_reg = 0x2200c,
181 .config_reg = 0x22010,
182 .mode_reg = 0x22000,
183 .status_reg = 0x2201c,
196 .enable_reg = 0x45000,
213 .vco_val = 0x0,
215 .pre_div_val = 0x0,
217 .post_div_val = 0x0,
220 .main_output_mask = BIT(0),
225 .l_reg = 0x24004,
226 .m_reg = 0x24008,
227 .n_reg = 0x2400c,
228 .config_reg = 0x24010,
229 .mode_reg = 0x24000,
230 .status_reg = 0x2401c,
243 .enable_reg = 0x45000,
260 .vco_val = 0x0,
262 .pre_div_val = 0x0,
264 .post_div_val = 0x0,
267 .main_output_mask = BIT(0),
271 .l_reg = 0x25004,
272 .m_reg = 0x25008,
273 .n_reg = 0x2500c,
274 .config_reg = 0x25010,
275 .mode_reg = 0x25000,
276 .status_reg = 0x2501c,
289 .enable_reg = 0x45000,
302 .l_reg = 0x37004,
303 .m_reg = 0x37008,
304 .n_reg = 0x3700c,
305 .config_reg = 0x37010,
306 .mode_reg = 0x37000,
307 .status_reg = 0x3701c,
320 .enable_reg = 0x45000,
333 { P_XO, 0 },
343 { P_XO, 0 },
355 { P_XO, 0 },
367 { P_XO, 0 },
383 { P_XO, 0 },
395 { P_XO, 0 },
409 { P_XO, 0 },
419 { P_XO, 0 },
433 { P_XO, 0 },
449 { P_XO, 0 },
461 { P_XO, 0, },
471 { P_XO, 0 },
483 { P_XO, 0 },
501 { P_XO, 0 },
513 { P_XO, 0 },
529 { P_XO, 0 },
543 { P_XO, 0 },
559 { P_XO, 0 },
575 { P_XO, 0 },
585 { P_XO, 0 },
611 .cmd_rcgr = 0x27000,
623 .cmd_rcgr = 0x26004,
635 .cmd_rcgr = 0x32024,
648 .cmd_rcgr = 0x2600c,
661 F(80000000, P_GPLL0, 10, 0, 0),
666 .cmd_rcgr = 0x5a000,
680 F(19200000, P_XO, 1, 0, 0),
681 F(50000000, P_GPLL0, 16, 0, 0),
682 F(100000000, P_GPLL0, 8, 0, 0),
683 F(133330000, P_GPLL0, 6, 0, 0),
688 .cmd_rcgr = 0x46000,
701 F(100000000, P_GPLL0, 8, 0, 0),
702 F(200000000, P_GPLL0, 4, 0, 0),
707 .cmd_rcgr = 0x4e020,
720 .cmd_rcgr = 0x4f020,
733 F(19200000, P_XO, 1, 0, 0),
734 F(50000000, P_GPLL0, 16, 0, 0),
735 F(80000000, P_GPLL0, 10, 0, 0),
736 F(100000000, P_GPLL0, 8, 0, 0),
737 F(160000000, P_GPLL0, 5, 0, 0),
738 F(200000000, P_GPLL0, 4, 0, 0),
739 F(220000000, P_GPLL3, 5, 0, 0),
740 F(266670000, P_GPLL0, 3, 0, 0),
741 F(310000000, P_GPLL2_AUX, 3, 0, 0),
742 F(400000000, P_GPLL0, 2, 0, 0),
743 F(465000000, P_GPLL2_AUX, 2, 0, 0),
744 F(550000000, P_GPLL3, 2, 0, 0),
749 .cmd_rcgr = 0x59000,
762 F(50000000, P_GPLL0, 16, 0, 0),
763 F(80000000, P_GPLL0, 10, 0, 0),
764 F(100000000, P_GPLL0, 8, 0, 0),
765 F(160000000, P_GPLL0, 5, 0, 0),
766 F(177780000, P_GPLL0, 4.5, 0, 0),
767 F(200000000, P_GPLL0, 4, 0, 0),
768 F(266670000, P_GPLL0, 3, 0, 0),
769 F(320000000, P_GPLL0, 2.5, 0, 0),
770 F(400000000, P_GPLL0, 2, 0, 0),
771 F(465000000, P_GPLL2, 2, 0, 0),
772 F(480000000, P_GPLL4, 2.5, 0, 0),
773 F(600000000, P_GPLL4, 2, 0, 0),
778 .cmd_rcgr = 0x58000,
791 F(19200000, P_XO, 1, 0, 0),
792 F(50000000, P_GPLL0, 16, 0, 0),
797 .cmd_rcgr = 0x0200c,
811 F(4800000, P_XO, 4, 0, 0),
812 F(9600000, P_XO, 2, 0, 0),
814 F(19200000, P_XO, 1, 0, 0),
816 F(50000000, P_GPLL0, 16, 0, 0),
821 .cmd_rcgr = 0x02024,
835 .cmd_rcgr = 0x03000,
848 .cmd_rcgr = 0x03014,
862 .cmd_rcgr = 0x04000,
875 .cmd_rcgr = 0x04024,
889 .cmd_rcgr = 0x05000,
902 .cmd_rcgr = 0x05024,
916 .cmd_rcgr = 0x06000,
929 .cmd_rcgr = 0x06024,
943 .cmd_rcgr = 0x07000,
956 .cmd_rcgr = 0x07024,
974 F(19200000, P_XO, 1, 0, 0),
989 .cmd_rcgr = 0x02044,
1003 .cmd_rcgr = 0x03034,
1017 F(19200000, P_XO, 1, 0, 0),
1023 .cmd_rcgr = 0x51000,
1037 F(100000000, P_GPLL0, 8, 0, 0),
1038 F(200000000, P_GPLL0, 4, 0, 0),
1043 .cmd_rcgr = 0x54000,
1057 .cmd_rcgr = 0x55000,
1071 F(133330000, P_GPLL0, 6, 0, 0),
1072 F(266670000, P_GPLL0, 3, 0, 0),
1073 F(320000000, P_GPLL0, 2.5, 0, 0),
1078 .cmd_rcgr = 0x57000,
1092 F(66670000, P_GPLL0, 12, 0, 0),
1097 .cmd_rcgr = 0x52000,
1111 .cmd_rcgr = 0x53000,
1125 F(100000000, P_GPLL0, 8, 0, 0),
1126 F(200000000, P_GPLL0, 4, 0, 0),
1131 .cmd_rcgr = 0x4e000,
1144 .cmd_rcgr = 0x4f000,
1157 F(160000000, P_GPLL0, 5, 0, 0),
1158 F(200000000, P_GPLL0, 4, 0, 0),
1159 F(228570000, P_GPLL0, 3.5, 0, 0),
1160 F(266670000, P_GPLL0, 3, 0, 0),
1161 F(320000000, P_GPLL0, 2.5, 0, 0),
1162 F(465000000, P_GPLL2, 2, 0, 0),
1167 .cmd_rcgr = 0x58018,
1180 F(50000000, P_GPLL0, 16, 0, 0),
1181 F(80000000, P_GPLL0, 10, 0, 0),
1182 F(100000000, P_GPLL0, 8, 0, 0),
1183 F(160000000, P_GPLL0, 5, 0, 0),
1189 .cmd_rcgr = 0x16004,
1202 F(19200000, P_XO, 1, 0, 0),
1207 .cmd_rcgr = 0x08004,
1221 .cmd_rcgr = 0x09004,
1235 .cmd_rcgr = 0x0a004,
1249 .cmd_rcgr = 0x4d044,
1262 .cmd_rcgr = 0x4d0b0,
1275 F(19200000, P_XO, 1, 0, 0),
1280 .cmd_rcgr = 0x4d060,
1293 .cmd_rcgr = 0x4d0a8,
1306 F(50000000, P_GPLL0_AUX, 16, 0, 0),
1307 F(80000000, P_GPLL0_AUX, 10, 0, 0),
1308 F(100000000, P_GPLL0_AUX, 8, 0, 0),
1309 F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1310 F(153600000, P_GPLL0, 4, 0, 0),
1311 F(160000000, P_GPLL0_AUX, 5, 0, 0),
1312 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1313 F(200000000, P_GPLL0_AUX, 4, 0, 0),
1314 F(266670000, P_GPLL0_AUX, 3, 0, 0),
1315 F(307200000, P_GPLL1, 2, 0, 0),
1316 F(366670000, P_GPLL3_AUX, 3, 0, 0),
1321 .cmd_rcgr = 0x4d014,
1334 .cmd_rcgr = 0x4d000,
1348 .cmd_rcgr = 0x4d0b8,
1362 F(19200000, P_XO, 1, 0, 0),
1367 .cmd_rcgr = 0x4d02c,
1380 F(64000000, P_GPLL0, 12.5, 0, 0),
1386 .cmd_rcgr = 0x44010,
1403 F(50000000, P_GPLL0, 16, 0, 0),
1404 F(100000000, P_GPLL0, 8, 0, 0),
1405 F(177770000, P_GPLL0, 4.5, 0, 0),
1406 F(200000000, P_GPLL0, 4, 0, 0),
1411 .cmd_rcgr = 0x42004,
1425 .cmd_rcgr = 0x43004,
1439 F(154285000, P_GPLL6, 7, 0, 0),
1440 F(320000000, P_GPLL0, 2.5, 0, 0),
1441 F(400000000, P_GPLL0, 2, 0, 0),
1446 .cmd_rcgr = 0x1207c,
1459 F(19200000, P_XO, 1, 0, 0),
1460 F(100000000, P_GPLL0, 8, 0, 0),
1461 F(200000000, P_GPLL0, 4, 0, 0),
1462 F(266500000, P_BIMC, 4, 0, 0),
1463 F(400000000, P_GPLL0, 2, 0, 0),
1464 F(533000000, P_BIMC, 2, 0, 0),
1469 .cmd_rcgr = 0x31028,
1483 F(57140000, P_GPLL0, 14, 0, 0),
1484 F(80000000, P_GPLL0, 10, 0, 0),
1485 F(100000000, P_GPLL0, 8, 0, 0),
1490 .cmd_rcgr = 0x41010,
1503 F(64000000, P_GPLL0, 12.5, 0, 0),
1508 .cmd_rcgr = 0x3f010,
1526 .cmd_rcgr = 0x3f034,
1539 F(3200000, P_XO, 6, 0, 0),
1540 F(6400000, P_XO, 3, 0, 0),
1541 F(9600000, P_XO, 2, 0, 0),
1542 F(19200000, P_XO, 1, 0, 0),
1544 F(66670000, P_GPLL0, 12, 0, 0),
1545 F(80000000, P_GPLL0, 10, 0, 0),
1546 F(100000000, P_GPLL0, 8, 0, 0),
1551 .cmd_rcgr = 0x1c010,
1565 .halt_reg = 0x1c028,
1567 .enable_reg = 0x1c028,
1568 .enable_mask = BIT(0),
1582 .halt_reg = 0x1c024,
1584 .enable_reg = 0x1c024,
1585 .enable_mask = BIT(0),
1611 F(1600000, P_XO, 12, 0, 0),
1615 F(2400000, P_XO, 8, 0, 0),
1619 F(4800000, P_XO, 4, 0, 0),
1623 F(9600000, P_XO, 2, 0, 0),
1630 .cmd_rcgr = 0x1c054,
1644 .halt_reg = 0x1c068,
1646 .enable_reg = 0x1c068,
1647 .enable_mask = BIT(0),
1661 .cmd_rcgr = 0x1c06c,
1675 .halt_reg = 0x1c080,
1677 .enable_reg = 0x1c080,
1678 .enable_mask = BIT(0),
1692 .cmd_rcgr = 0x1c084,
1706 .halt_reg = 0x1c098,
1708 .enable_reg = 0x1c098,
1709 .enable_mask = BIT(0),
1723 F(19200000, P_XO, 1, 0, 0),
1728 .cmd_rcgr = 0x1c034,
1741 .halt_reg = 0x1c04c,
1743 .enable_reg = 0x1c04c,
1744 .enable_mask = BIT(0),
1758 .halt_reg = 0x1c050,
1760 .enable_reg = 0x1c050,
1761 .enable_mask = BIT(0),
1775 F(9600000, P_XO, 2, 0, 0),
1777 F(19200000, P_XO, 1, 0, 0),
1778 F(11289600, P_EXT_MCLK, 1, 0, 0),
1783 .cmd_rcgr = 0x1c09c,
1797 .halt_reg = 0x1c0b0,
1799 .enable_reg = 0x1c0b0,
1800 .enable_mask = BIT(0),
1814 .halt_reg = 0x1c000,
1816 .enable_reg = 0x1c000,
1817 .enable_mask = BIT(0),
1830 .halt_reg = 0x1c004,
1832 .enable_reg = 0x1c004,
1833 .enable_mask = BIT(0),
1846 F(133330000, P_GPLL0, 6, 0, 0),
1847 F(200000000, P_GPLL0, 4, 0, 0),
1848 F(266670000, P_GPLL0, 3, 0, 0),
1853 .cmd_rcgr = 0x4C000,
1867 .halt_reg = 0x01008,
1870 .enable_reg = 0x45004,
1884 .halt_reg = 0x01004,
1886 .enable_reg = 0x01004,
1887 .enable_mask = BIT(0),
1896 .halt_reg = 0x02008,
1898 .enable_reg = 0x02008,
1899 .enable_mask = BIT(0),
1913 .halt_reg = 0x02004,
1915 .enable_reg = 0x02004,
1916 .enable_mask = BIT(0),
1930 .halt_reg = 0x03010,
1932 .enable_reg = 0x03010,
1933 .enable_mask = BIT(0),
1947 .halt_reg = 0x0300c,
1949 .enable_reg = 0x0300c,
1950 .enable_mask = BIT(0),
1964 .halt_reg = 0x04020,
1966 .enable_reg = 0x04020,
1967 .enable_mask = BIT(0),
1981 .halt_reg = 0x0401c,
1983 .enable_reg = 0x0401c,
1984 .enable_mask = BIT(0),
1998 .halt_reg = 0x05020,
2000 .enable_reg = 0x05020,
2001 .enable_mask = BIT(0),
2015 .halt_reg = 0x0501c,
2017 .enable_reg = 0x0501c,
2018 .enable_mask = BIT(0),
2032 .halt_reg = 0x06020,
2034 .enable_reg = 0x06020,
2035 .enable_mask = BIT(0),
2049 .halt_reg = 0x0601c,
2051 .enable_reg = 0x0601c,
2052 .enable_mask = BIT(0),
2066 .halt_reg = 0x07020,
2068 .enable_reg = 0x07020,
2069 .enable_mask = BIT(0),
2083 .halt_reg = 0x0701c,
2085 .enable_reg = 0x0701c,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x0203c,
2102 .enable_reg = 0x0203c,
2103 .enable_mask = BIT(0),
2117 .halt_reg = 0x0302c,
2119 .enable_reg = 0x0302c,
2120 .enable_mask = BIT(0),
2134 .halt_reg = 0x1300c,
2137 .enable_reg = 0x45004,
2151 .halt_reg = 0x5101c,
2153 .enable_reg = 0x5101c,
2154 .enable_mask = BIT(0),
2168 .halt_reg = 0x51018,
2170 .enable_reg = 0x51018,
2171 .enable_mask = BIT(0),
2185 .halt_reg = 0x4e040,
2187 .enable_reg = 0x4e040,
2188 .enable_mask = BIT(0),
2202 .halt_reg = 0x4e03c,
2204 .enable_reg = 0x4e03c,
2205 .enable_mask = BIT(0),
2219 .halt_reg = 0x4e048,
2221 .enable_reg = 0x4e048,
2222 .enable_mask = BIT(0),
2236 .halt_reg = 0x4e058,
2238 .enable_reg = 0x4e058,
2239 .enable_mask = BIT(0),
2253 .halt_reg = 0x4e050,
2255 .enable_reg = 0x4e050,
2256 .enable_mask = BIT(0),
2270 .halt_reg = 0x4f040,
2272 .enable_reg = 0x4f040,
2273 .enable_mask = BIT(0),
2287 .halt_reg = 0x4f03c,
2289 .enable_reg = 0x4f03c,
2290 .enable_mask = BIT(0),
2304 .halt_reg = 0x4f048,
2306 .enable_reg = 0x4f048,
2307 .enable_mask = BIT(0),
2321 .halt_reg = 0x4f058,
2323 .enable_reg = 0x4f058,
2324 .enable_mask = BIT(0),
2338 .halt_reg = 0x4f050,
2340 .enable_reg = 0x4f050,
2341 .enable_mask = BIT(0),
2355 .halt_reg = 0x58050,
2357 .enable_reg = 0x58050,
2358 .enable_mask = BIT(0),
2372 .halt_reg = 0x54018,
2374 .enable_reg = 0x54018,
2375 .enable_mask = BIT(0),
2389 .halt_reg = 0x55018,
2391 .enable_reg = 0x55018,
2392 .enable_mask = BIT(0),
2406 .halt_reg = 0x50004,
2408 .enable_reg = 0x50004,
2409 .enable_mask = BIT(0),
2423 .halt_reg = 0x57020,
2425 .enable_reg = 0x57020,
2426 .enable_mask = BIT(0),
2440 .halt_reg = 0x57024,
2442 .enable_reg = 0x57024,
2443 .enable_mask = BIT(0),
2457 .halt_reg = 0x57028,
2459 .enable_reg = 0x57028,
2460 .enable_mask = BIT(0),
2474 .halt_reg = 0x52018,
2476 .enable_reg = 0x52018,
2477 .enable_mask = BIT(0),
2491 .halt_reg = 0x53018,
2493 .enable_reg = 0x53018,
2494 .enable_mask = BIT(0),
2508 .halt_reg = 0x5600c,
2510 .enable_reg = 0x5600c,
2511 .enable_mask = BIT(0),
2525 .halt_reg = 0x4e01c,
2527 .enable_reg = 0x4e01c,
2528 .enable_mask = BIT(0),
2542 .halt_reg = 0x4f01c,
2544 .enable_reg = 0x4f01c,
2545 .enable_mask = BIT(0),
2559 .halt_reg = 0x5a014,
2561 .enable_reg = 0x5a014,
2562 .enable_mask = BIT(0),
2576 .halt_reg = 0x56004,
2578 .enable_reg = 0x56004,
2579 .enable_mask = BIT(0),
2593 .halt_reg = 0x58040,
2595 .enable_reg = 0x58040,
2596 .enable_mask = BIT(0),
2610 .halt_reg = 0x5803c,
2612 .enable_reg = 0x5803c,
2613 .enable_mask = BIT(0),
2627 .halt_reg = 0x58038,
2629 .enable_reg = 0x58038,
2630 .enable_mask = BIT(0),
2644 .halt_reg = 0x58044,
2646 .enable_reg = 0x58044,
2647 .enable_mask = BIT(0),
2661 .halt_reg = 0x58048,
2663 .enable_reg = 0x58048,
2664 .enable_mask = BIT(0),
2678 .halt_reg = 0x16024,
2681 .enable_reg = 0x45004,
2682 .enable_mask = BIT(0),
2696 .halt_reg = 0x16020,
2699 .enable_reg = 0x45004,
2714 .halt_reg = 0x1601c,
2717 .enable_reg = 0x45004,
2732 .halt_reg = 0x59024,
2734 .enable_reg = 0x59024,
2735 .enable_mask = BIT(0),
2749 .halt_reg = 0x08000,
2751 .enable_reg = 0x08000,
2752 .enable_mask = BIT(0),
2766 .halt_reg = 0x09000,
2768 .enable_reg = 0x09000,
2769 .enable_mask = BIT(0),
2783 .halt_reg = 0x0a000,
2785 .enable_reg = 0x0a000,
2786 .enable_mask = BIT(0),
2800 .halt_reg = 0x4d07c,
2802 .enable_reg = 0x4d07c,
2803 .enable_mask = BIT(0),
2817 .halt_reg = 0x4d080,
2819 .enable_reg = 0x4d080,
2820 .enable_mask = BIT(0),
2834 .halt_reg = 0x4d094,
2836 .enable_reg = 0x4d094,
2837 .enable_mask = BIT(0),
2851 .halt_reg = 0x4d0a0,
2853 .enable_reg = 0x4d0a0,
2854 .enable_mask = BIT(0),
2868 .halt_reg = 0x4d098,
2870 .enable_reg = 0x4d098,
2871 .enable_mask = BIT(0),
2885 .halt_reg = 0x4d09c,
2887 .enable_reg = 0x4d09c,
2888 .enable_mask = BIT(0),
2902 .halt_reg = 0x4D088,
2904 .enable_reg = 0x4D088,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x4d084,
2921 .enable_reg = 0x4d084,
2922 .enable_mask = BIT(0),
2936 .halt_reg = 0x4d0a4,
2938 .enable_reg = 0x4d0a4,
2939 .enable_mask = BIT(0),
2953 .halt_reg = 0x4d090,
2955 .enable_reg = 0x4d090,
2956 .enable_mask = BIT(0),
2970 .halt_reg = 0x49000,
2972 .enable_reg = 0x49000,
2973 .enable_mask = BIT(0),
2987 .halt_reg = 0x49004,
2989 .enable_reg = 0x49004,
2990 .enable_mask = BIT(0),
3004 .halt_reg = 0x59028,
3006 .enable_reg = 0x59028,
3007 .enable_mask = BIT(0),
3021 .halt_reg = 0x59020,
3023 .enable_reg = 0x59020,
3024 .enable_mask = BIT(0),
3038 .halt_reg = 0x4400c,
3040 .enable_reg = 0x4400c,
3041 .enable_mask = BIT(0),
3055 .halt_reg = 0x44004,
3057 .enable_reg = 0x44004,
3058 .enable_mask = BIT(0),
3072 .halt_reg = 0x13004,
3075 .enable_reg = 0x45004,
3089 .halt_reg = 0x4201c,
3091 .enable_reg = 0x4201c,
3092 .enable_mask = BIT(0),
3106 .halt_reg = 0x42018,
3108 .enable_reg = 0x42018,
3109 .enable_mask = BIT(0),
3123 .halt_reg = 0x4301c,
3125 .enable_reg = 0x4301c,
3126 .enable_mask = BIT(0),
3140 .halt_reg = 0x43018,
3142 .enable_reg = 0x43018,
3143 .enable_mask = BIT(0),
3157 .halt_reg = 0x12018,
3160 .enable_reg = 0x4500c,
3174 .halt_reg = 0x12020,
3177 .enable_reg = 0x4500c,
3191 .halt_reg = 0x12010,
3194 .enable_reg = 0x4500c,
3208 .halt_reg = 0x1201c,
3211 .enable_reg = 0x4500c,
3226 .halt_reg = 0x12014,
3229 .enable_reg = 0x4500c,
3244 .halt_reg = 0x1203c,
3247 .enable_reg = 0x4500c,
3262 .halt_reg = 0x12034,
3265 .enable_reg = 0x4500c,
3280 .halt_reg = 0x12038,
3283 .enable_reg = 0x4500c,
3298 .halt_reg = 0x12044,
3301 .enable_reg = 0x4500c,
3316 .halt_reg = 0x12040,
3319 .enable_reg = 0x4500c,
3334 .halt_reg = 0x1201c,
3337 .enable_reg = 0x4500c,
3352 .halt_reg = 0x31024,
3354 .enable_reg = 0x31024,
3355 .enable_mask = BIT(0),
3369 .halt_reg = 0x31040,
3371 .enable_reg = 0x31040,
3372 .enable_mask = BIT(0),
3386 .halt_reg = 0x4102c,
3388 .enable_reg = 0x4102c,
3389 .enable_mask = BIT(0),
3398 .halt_reg = 0x3f008,
3400 .enable_reg = 0x3f008,
3401 .enable_mask = BIT(0),
3415 .halt_reg = 0x3f030,
3417 .enable_reg = 0x3f030,
3418 .enable_mask = BIT(0),
3432 .halt_reg = 0x3f004,
3434 .enable_reg = 0x3f004,
3435 .enable_mask = BIT(0),
3449 .halt_reg = 0x41008,
3451 .enable_reg = 0x41008,
3452 .enable_mask = BIT(0),
3466 .halt_reg = 0x41004,
3468 .enable_reg = 0x41004,
3469 .enable_mask = BIT(0),
3483 .halt_reg = 0x4c020,
3485 .enable_reg = 0x4c020,
3486 .enable_mask = BIT(0),
3500 .halt_reg = 0x4c024,
3502 .enable_reg = 0x4c024,
3503 .enable_mask = BIT(0),
3517 .halt_reg = 0x4c01c,
3519 .enable_reg = 0x4c01c,
3520 .enable_mask = BIT(0),
3534 .halt_reg = 0x4c02c,
3536 .enable_reg = 0x4c02c,
3537 .enable_mask = BIT(0),
3551 .halt_reg = 0x4c034,
3553 .enable_reg = 0x4c034,
3554 .enable_mask = BIT(0),
3568 .halt_reg = 0x59040,
3570 .enable_reg = 0x59040,
3571 .enable_mask = BIT(0),
3580 .gdscr = 0x4c018,
3588 .gdscr = 0x4d078,
3596 .gdscr = 0x5701c,
3604 .gdscr = 0x58034,
3612 .gdscr = 0x5901c,
3620 .gdscr = 0x4c028,
3628 .gdscr = 0x4c030,
3836 [GCC_BLSP1_BCR] = { 0x01000 },
3837 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3838 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3839 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3840 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3841 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3842 [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3843 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3844 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3845 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3846 [GCC_IMEM_BCR] = { 0x0e000 },
3847 [GCC_SMMU_BCR] = { 0x12000 },
3848 [GCC_APSS_TCU_BCR] = { 0x12050 },
3849 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3850 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3851 [GCC_PRNG_BCR] = { 0x13000 },
3852 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3853 [GCC_CRYPTO_BCR] = { 0x16000 },
3854 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3855 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3856 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3857 [GCC_DEHR_BCR] = { 0x1f000 },
3858 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3859 [GCC_PCNOC_BCR] = { 0x27018 },
3860 [GCC_TCSR_BCR] = { 0x28000 },
3861 [GCC_QDSS_BCR] = { 0x29000 },
3862 [GCC_DCD_BCR] = { 0x2a000 },
3863 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3864 [GCC_MPM_BCR] = { 0x2c000 },
3865 [GCC_SPMI_BCR] = { 0x2e000 },
3866 [GCC_SPDM_BCR] = { 0x2f000 },
3867 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3868 [GCC_BIMC_BCR] = { 0x31000 },
3869 [GCC_RBCPR_BCR] = { 0x33000 },
3870 [GCC_TLMM_BCR] = { 0x34000 },
3871 [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3872 [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3873 [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3874 [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3875 [GCC_USB_FS_BCR] = { 0x3f000 },
3876 [GCC_USB_HS_BCR] = { 0x41000 },
3877 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3878 [GCC_SDCC1_BCR] = { 0x42000 },
3879 [GCC_SDCC2_BCR] = { 0x43000 },
3880 [GCC_PDM_BCR] = { 0x44000 },
3881 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3882 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3883 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3884 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3885 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3886 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3887 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3888 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3889 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3890 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3891 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3892 [GCC_MMSS_BCR] = { 0x4b000 },
3893 [GCC_VENUS0_BCR] = { 0x4c014 },
3894 [GCC_MDSS_BCR] = { 0x4d074 },
3895 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3896 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3897 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3898 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3899 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3900 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3901 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3902 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3903 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3904 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3905 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3906 [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3907 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3908 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3909 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3910 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3911 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3912 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3913 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3914 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3915 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3916 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3917 [GCC_OXILI_BCR] = { 0x59018 },
3918 [GCC_GMEM_BCR] = { 0x5902c },
3919 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3920 [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3921 [GCC_MDP_TBU_BCR] = { 0x62000 },
3922 [GCC_GFX_TBU_BCR] = { 0x63000 },
3923 [GCC_GFX_TCU_BCR] = { 0x64000 },
3924 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3925 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3926 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3927 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3928 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3929 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3930 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3931 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3932 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3933 [GCC_CPP_TBU_BCR] = { 0x6e000 },
3934 [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3935 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3942 .max_register = 0x80000,