Lines Matching +full:0 +full:x46000

105  *  #define _FOO_A                      0xf000
106  *  #define _FOO_B                      0xf001
110  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
114  *  #define BAR                         _MMIO(0xb000)
115  *  #define GEN8_BAR                    _MMIO(0xb888)
122  * numbers, pick the 0-based __index'th value.
129  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
177 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
179 		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
185 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
187 #define GU_CNTL				_MMIO(0x101010)
190 #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
191 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
192 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
194 #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
199 #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
202 #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
206 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
207 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
209 #define _VGA_MSR_WRITE _MMIO(0x3c2)
211 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
212 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
218 #define DEBUG_RESET_I830		_MMIO(0x6070)
226 #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
232 #define   IOSF_SB_BUSY				(1 << 0)
233 #define   IOSF_PORT_BUNIT			0x03
234 #define   IOSF_PORT_PUNIT			0x04
235 #define   IOSF_PORT_NC				0x11
236 #define   IOSF_PORT_DPIO			0x12
237 #define   IOSF_PORT_GPIO_NC			0x13
238 #define   IOSF_PORT_CCK				0x14
239 #define   IOSF_PORT_DPIO_2			0x1a
240 #define   IOSF_PORT_FLISDSI			0x1b
241 #define   IOSF_PORT_GPIO_SC			0x48
242 #define   IOSF_PORT_GPIO_SUS			0xa8
243 #define   IOSF_PORT_CCU				0xa9
244 #define   CHV_IOSF_PORT_GPIO_N			0x13
245 #define   CHV_IOSF_PORT_GPIO_SE			0x48
246 #define   CHV_IOSF_PORT_GPIO_E			0xa8
247 #define   CHV_IOSF_PORT_GPIO_SW			0xb2
248 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
249 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
252 #define DPIO_DEVFN			0
254 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
258 #define  DPIO_CMNRST			(1 << 0)
265 #define _VLV_PLL_DW3_CH0		0x800c
267 #define   DPIO_POST_DIV_DAC		0
277 #define   DPIO_M2DIV_MASK		0xff
278 #define _VLV_PLL_DW3_CH1		0x802c
281 #define _VLV_PLL_DW5_CH0		0x8014
284 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
287 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
288 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
289 #define _VLV_PLL_DW5_CH1		0x8034
292 #define _VLV_PLL_DW7_CH0		0x801c
293 #define _VLV_PLL_DW7_CH1		0x803c
296 #define _VLV_PLL_DW8_CH0		0x8040
297 #define _VLV_PLL_DW8_CH1		0x8060
300 #define VLV_PLL_DW9_BCAST		0xc044
301 #define _VLV_PLL_DW9_CH0		0x8044
302 #define _VLV_PLL_DW9_CH1		0x8064
305 #define _VLV_PLL_DW10_CH0		0x8048
306 #define _VLV_PLL_DW10_CH1		0x8068
309 #define _VLV_PLL_DW11_CH0		0x804c
310 #define _VLV_PLL_DW11_CH1		0x806c
314 #define VLV_REF_DW13			0x80ac
316 #define VLV_CMN_DW0			0x8100
322 #define _VLV_PCS_DW0_CH0		0x8200
323 #define _VLV_PCS_DW0_CH1		0x8400
330 #define _VLV_PCS01_DW0_CH0		0x200
331 #define _VLV_PCS23_DW0_CH0		0x400
332 #define _VLV_PCS01_DW0_CH1		0x2600
333 #define _VLV_PCS23_DW0_CH1		0x2800
337 #define _VLV_PCS_DW1_CH0		0x8204
338 #define _VLV_PCS_DW1_CH1		0x8404
346 #define _VLV_PCS01_DW1_CH0		0x204
347 #define _VLV_PCS23_DW1_CH0		0x404
348 #define _VLV_PCS01_DW1_CH1		0x2604
349 #define _VLV_PCS23_DW1_CH1		0x2804
353 #define _VLV_PCS_DW8_CH0		0x8220
354 #define _VLV_PCS_DW8_CH1		0x8420
359 #define _VLV_PCS01_DW8_CH0		0x0220
360 #define _VLV_PCS23_DW8_CH0		0x0420
361 #define _VLV_PCS01_DW8_CH1		0x2620
362 #define _VLV_PCS23_DW8_CH1		0x2820
366 #define _VLV_PCS_DW9_CH0		0x8224
367 #define _VLV_PCS_DW9_CH1		0x8424
368 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
369 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
371 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
372 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
376 #define _VLV_PCS01_DW9_CH0		0x224
377 #define _VLV_PCS23_DW9_CH0		0x424
378 #define _VLV_PCS01_DW9_CH1		0x2624
379 #define _VLV_PCS23_DW9_CH1		0x2824
383 #define _CHV_PCS_DW10_CH0		0x8228
384 #define _CHV_PCS_DW10_CH1		0x8428
387 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
388 #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
390 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
391 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
395 #define _VLV_PCS01_DW10_CH0		0x0228
396 #define _VLV_PCS23_DW10_CH0		0x0428
397 #define _VLV_PCS01_DW10_CH1		0x2628
398 #define _VLV_PCS23_DW10_CH1		0x2828
402 #define _VLV_PCS_DW11_CH0		0x822c
403 #define _VLV_PCS_DW11_CH1		0x842c
407 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
410 #define _VLV_PCS01_DW11_CH0		0x022c
411 #define _VLV_PCS23_DW11_CH0		0x042c
412 #define _VLV_PCS01_DW11_CH1		0x262c
413 #define _VLV_PCS23_DW11_CH1		0x282c
417 #define _VLV_PCS01_DW12_CH0		0x0230
418 #define _VLV_PCS23_DW12_CH0		0x0430
419 #define _VLV_PCS01_DW12_CH1		0x2630
420 #define _VLV_PCS23_DW12_CH1		0x2830
424 #define _VLV_PCS_DW12_CH0		0x8230
425 #define _VLV_PCS_DW12_CH1		0x8430
430 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
433 #define _VLV_PCS_DW14_CH0		0x8238
434 #define _VLV_PCS_DW14_CH1		0x8438
437 #define _VLV_PCS_DW23_CH0		0x825c
438 #define _VLV_PCS_DW23_CH1		0x845c
441 #define _VLV_TX_DW2_CH0			0x8288
442 #define _VLV_TX_DW2_CH1			0x8488
444 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
448 #define _VLV_TX_DW3_CH0			0x828c
449 #define _VLV_TX_DW3_CH1			0x848c
453 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
456 #define _VLV_TX_DW4_CH0			0x8290
457 #define _VLV_TX_DW4_CH1			0x8490
459 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
461 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
464 #define _VLV_TX3_DW4_CH0		0x690
465 #define _VLV_TX3_DW4_CH1		0x2a90
468 #define _VLV_TX_DW5_CH0			0x8294
469 #define _VLV_TX_DW5_CH1			0x8494
473 #define _VLV_TX_DW11_CH0		0x82ac
474 #define _VLV_TX_DW11_CH1		0x84ac
477 #define _VLV_TX_DW14_CH0		0x82b8
478 #define _VLV_TX_DW14_CH1		0x84b8
482 #define _CHV_PLL_DW0_CH0		0x8000
483 #define _CHV_PLL_DW0_CH1		0x8180
486 #define _CHV_PLL_DW1_CH0		0x8004
487 #define _CHV_PLL_DW1_CH1		0x8184
489 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
492 #define _CHV_PLL_DW2_CH0		0x8008
493 #define _CHV_PLL_DW2_CH1		0x8188
496 #define _CHV_PLL_DW3_CH0		0x800c
497 #define _CHV_PLL_DW3_CH1		0x818c
499 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
501 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
502 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
505 #define _CHV_PLL_DW6_CH0		0x8018
506 #define _CHV_PLL_DW6_CH1		0x8198
509 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
512 #define _CHV_PLL_DW8_CH0		0x8020
513 #define _CHV_PLL_DW8_CH1		0x81A0
514 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
515 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
518 #define _CHV_PLL_DW9_CH0		0x8024
519 #define _CHV_PLL_DW9_CH1		0x81A4
522 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
525 #define _CHV_CMN_DW0_CH0               0x8100
529 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
531 #define _CHV_CMN_DW5_CH0               0x8114
532 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
536 #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
541 #define _CHV_CMN_DW13_CH0		0x8134
542 #define _CHV_CMN_DW0_CH1		0x8080
548 #define   DPIO_PLL_LOCK			(1 << 0)
551 #define _CHV_CMN_DW14_CH0		0x8138
552 #define _CHV_CMN_DW1_CH1		0x8084
555 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
559 #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
565 #define _CHV_CMN_DW19_CH0		0x814c
566 #define _CHV_CMN_DW6_CH1		0x8098
574 #define CHV_CMN_DW28			0x8170
577 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
578 #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
579 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
580 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
582 #define CHV_CMN_DW30			0x8178
586 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
587 					(lane) * 0x200 + (offset))
589 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
590 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
591 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
592 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
593 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
594 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
595 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
596 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
597 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
598 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
599 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
600 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
602 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
606 #define _BXT_PHY0_BASE			0x6C000
607 #define _BXT_PHY1_BASE			0x162000
608 #define _BXT_PHY2_BASE			0x163000
622 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
625 #define _BXT_PHY_CTL_DDI_A		0x64C00
626 #define _BXT_PHY_CTL_DDI_B		0x64C10
627 #define _BXT_PHY_CTL_DDI_C		0x64C20
634 #define _PHY_CTL_FAMILY_EDP		0x64C80
635 #define _PHY_CTL_FAMILY_DDI		0x64C90
636 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
643 #define _PORT_PLL_A			0x46074
644 #define _PORT_PLL_B			0x46078
645 #define _PORT_PLL_C			0x4607c
653 #define _PORT_PLL_EBB_0_A		0x162034
654 #define _PORT_PLL_EBB_0_B		0x6C034
655 #define _PORT_PLL_EBB_0_C		0x6C340
664 #define _PORT_PLL_EBB_4_A		0x162038
665 #define _PORT_PLL_EBB_4_B		0x6C038
666 #define _PORT_PLL_EBB_4_C		0x6C344
673 #define _PORT_PLL_0_A			0x162100
674 #define _PORT_PLL_0_B			0x6C100
675 #define _PORT_PLL_0_C			0x6C380
677 #define   PORT_PLL_M2_INT_MASK		REG_GENMASK(7, 0)
683 #define   PORT_PLL_M2_FRAC_MASK		REG_GENMASK(21, 0)
692 #define   PORT_PLL_PROP_COEFF_MASK	REG_GENMASK(3, 0)
695 #define   PORT_PLL_TARGET_CNT_MASK	REG_GENMASK(9, 0)
711 #define _PORT_CL1CM_DW0_A		0x162000
712 #define _PORT_CL1CM_DW0_BC		0x6C000
717 #define _PORT_CL1CM_DW9_A		0x162024
718 #define _PORT_CL1CM_DW9_BC		0x6C024
720 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
723 #define _PORT_CL1CM_DW10_A		0x162028
724 #define _PORT_CL1CM_DW10_BC		0x6C028
726 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
729 #define _PORT_CL1CM_DW28_A		0x162070
730 #define _PORT_CL1CM_DW28_BC		0x6C070
733 #define   SUS_CLK_CONFIG		0x3
736 #define _PORT_CL1CM_DW30_A		0x162078
737 #define _PORT_CL1CM_DW30_BC		0x6C078
744 #define _PORT_CL2CM_DW6_A		0x162358
745 #define _PORT_CL2CM_DW6_BC		0x6C358
750 #define _PORT_REF_DW3_A			0x16218C
751 #define _PORT_REF_DW3_BC		0x6C18C
755 #define _PORT_REF_DW6_A			0x162198
756 #define _PORT_REF_DW6_BC		0x6C198
758 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
760 #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
762 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
763 #define   GRC_CODE_NOM_MASK		0xFF
766 #define _PORT_REF_DW8_A			0x1621A0
767 #define _PORT_REF_DW8_BC		0x6C1A0
773 #define _PORT_PCS_DW10_LN01_A		0x162428
774 #define _PORT_PCS_DW10_LN01_B		0x6C428
775 #define _PORT_PCS_DW10_LN01_C		0x6C828
776 #define _PORT_PCS_DW10_GRP_A		0x162C28
777 #define _PORT_PCS_DW10_GRP_B		0x6CC28
778 #define _PORT_PCS_DW10_GRP_C		0x6CE28
789 #define _PORT_PCS_DW12_LN01_A		0x162430
790 #define _PORT_PCS_DW12_LN01_B		0x6C430
791 #define _PORT_PCS_DW12_LN01_C		0x6C830
792 #define _PORT_PCS_DW12_LN23_A		0x162630
793 #define _PORT_PCS_DW12_LN23_B		0x6C630
794 #define _PORT_PCS_DW12_LN23_C		0x6CA30
795 #define _PORT_PCS_DW12_GRP_A		0x162c30
796 #define _PORT_PCS_DW12_GRP_B		0x6CC30
797 #define _PORT_PCS_DW12_GRP_C		0x6CE30
799 #define   LANE_STAGGER_MASK		0x1F
811 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
812 					  ((lane) & 1) * 0x80)
814 #define _PORT_TX_DW2_LN0_A		0x162508
815 #define _PORT_TX_DW2_LN0_B		0x6C508
816 #define _PORT_TX_DW2_LN0_C		0x6C908
817 #define _PORT_TX_DW2_GRP_A		0x162D08
818 #define _PORT_TX_DW2_GRP_B		0x6CD08
819 #define _PORT_TX_DW2_GRP_C		0x6CF08
827 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
829 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
831 #define _PORT_TX_DW3_LN0_A		0x16250C
832 #define _PORT_TX_DW3_LN0_B		0x6C50C
833 #define _PORT_TX_DW3_LN0_C		0x6C90C
834 #define _PORT_TX_DW3_GRP_A		0x162D0C
835 #define _PORT_TX_DW3_GRP_B		0x6CD0C
836 #define _PORT_TX_DW3_GRP_C		0x6CF0C
846 #define _PORT_TX_DW4_LN0_A		0x162510
847 #define _PORT_TX_DW4_LN0_B		0x6C510
848 #define _PORT_TX_DW4_LN0_C		0x6C910
849 #define _PORT_TX_DW4_GRP_A		0x162D10
850 #define _PORT_TX_DW4_GRP_B		0x6CD10
851 #define _PORT_TX_DW4_GRP_C		0x6CF10
859 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
861 #define _PORT_TX_DW5_LN0_A		0x162514
862 #define _PORT_TX_DW5_LN0_B		0x6C514
863 #define _PORT_TX_DW5_LN0_C		0x6C914
864 #define _PORT_TX_DW5_GRP_A		0x162D14
865 #define _PORT_TX_DW5_GRP_B		0x6CD14
866 #define _PORT_TX_DW5_GRP_C		0x6CF14
876 #define _PORT_TX_DW14_LN0_A		0x162538
877 #define _PORT_TX_DW14_LN0_B		0x6C538
878 #define _PORT_TX_DW14_LN0_C		0x6C938
887 #define UAIMI_SPR1			_MMIO(0x4F074)
889 #define SKL_VCCIO_MASK			0x1
891 #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
901  * [0-7]  @ 0x2000 gen2,gen3
902  * [8-15] @ 0x3000 945,g33,pnv
904  * [0-15] @ 0x3000 gen4,gen5
906  * [0-15] @ 0x100000 gen6,vlv,chv
907  * [0-31] @ 0x100000 gen7+
909 #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
910 #define   I830_FENCE_START_MASK		0x07f80000
914 #define   I830_FENCE_REG_VALID		(1 << 0)
919 #define   I915_FENCE_START_MASK		0x0ff00000
922 #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
923 #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
926 #define   I965_FENCE_REG_VALID		(1 << 0)
927 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
929 #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
930 #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
932 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
936 #define TILECTL				_MMIO(0x101000)
937 #define   TILECTL_SWZCTL			(1 << 0)
945 #define PGTBL_CTL	_MMIO(0x02020)
946 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
947 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
948 #define PGTBL_ER	_MMIO(0x02024)
949 #define PRB0_BASE	(0x2030 - 0x30)
950 #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
951 #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
952 #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
953 #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
954 #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
955 #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
956 #define RENDER_RING_BASE	0x02000
957 #define BSD_RING_BASE		0x04000
958 #define GEN6_BSD_RING_BASE	0x12000
959 #define GEN8_BSD2_RING_BASE	0x1c000
960 #define GEN11_BSD_RING_BASE	0x1c0000
961 #define GEN11_BSD2_RING_BASE	0x1c4000
962 #define GEN11_BSD3_RING_BASE	0x1d0000
963 #define GEN11_BSD4_RING_BASE	0x1d4000
964 #define XEHP_BSD5_RING_BASE	0x1e0000
965 #define XEHP_BSD6_RING_BASE	0x1e4000
966 #define XEHP_BSD7_RING_BASE	0x1f0000
967 #define XEHP_BSD8_RING_BASE	0x1f4000
968 #define VEBOX_RING_BASE		0x1a000
969 #define GEN11_VEBOX_RING_BASE		0x1c8000
970 #define GEN11_VEBOX2_RING_BASE		0x1d8000
971 #define XEHP_VEBOX3_RING_BASE		0x1e8000
972 #define XEHP_VEBOX4_RING_BASE		0x1f8000
973 #define GEN12_COMPUTE0_RING_BASE	0x1a000
974 #define GEN12_COMPUTE1_RING_BASE	0x1c000
975 #define GEN12_COMPUTE2_RING_BASE	0x1e000
976 #define GEN12_COMPUTE3_RING_BASE	0x26000
977 #define BLT_RING_BASE		0x22000
978 #define XEHPC_BCS1_RING_BASE	0x3e0000
979 #define XEHPC_BCS2_RING_BASE	0x3e2000
980 #define XEHPC_BCS3_RING_BASE	0x3e4000
981 #define XEHPC_BCS4_RING_BASE	0x3e6000
982 #define XEHPC_BCS5_RING_BASE	0x3e8000
983 #define XEHPC_BCS6_RING_BASE	0x3ea000
984 #define XEHPC_BCS7_RING_BASE	0x3ec000
985 #define XEHPC_BCS8_RING_BASE	0x3ee000
986 #define DG1_GSC_HECI1_BASE	0x00258000
987 #define DG1_GSC_HECI2_BASE	0x00259000
988 #define DG2_GSC_HECI1_BASE	0x00373000
989 #define DG2_GSC_HECI2_BASE	0x00374000
993 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
994 #define   GTT_CACHE_EN_ALL	0xF0007FFF
995 #define GEN7_WR_WATERMARK	_MMIO(0x4028)
996 #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
997 #define ARB_MODE		_MMIO(0x4030)
1000 #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
1001 #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
1003 #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
1005 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
1006 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
1008 #define GEN7_ERR_INT	_MMIO(0x44040)
1017 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
1020 #define FPGA_DBG		_MMIO(0x42300)
1023 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
1026 #define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
1028 #define DERRMR		_MMIO(0x44050)
1030 #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
1047 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
1048 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
1049 #define SCPD0		_MMIO(0x209c) /* 915+ only */
1052 #define GEN2_IER	_MMIO(0x20a0)
1053 #define GEN2_IIR	_MMIO(0x20a4)
1054 #define GEN2_IMR	_MMIO(0x20a8)
1055 #define GEN2_ISR	_MMIO(0x20ac)
1056 #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
1059 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
1060 #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
1061 #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
1062 #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
1063 #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
1064 #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
1065 #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
1069 #define EIR		_MMIO(0x20b0)
1070 #define EMR		_MMIO(0x20b4)
1071 #define ESR		_MMIO(0x20b8)
1077 #define   I915_ERROR_INSTRUCTION			(1 << 0)
1078 #define INSTPM	        _MMIO(0x20c0)
1086 #define MEM_MODE	_MMIO(0x20cc)
1090 #define FW_BLC		_MMIO(0x20d8)
1091 #define FW_BLC2		_MMIO(0x20dc)
1092 #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
1096 #define MM_BURST_LENGTH     0x00700000
1097 #define MM_FIFO_WATERMARK   0x0001F000
1098 #define LM_BURST_LENGTH     0x00000700
1099 #define LM_FIFO_WATERMARK   0x0000001F
1100 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
1102 #define _MBUS_ABOX0_CTL			0x45038
1103 #define _MBUS_ABOX1_CTL			0x45048
1104 #define _MBUS_ABOX2_CTL			0x4504C
1110 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
1112 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
1114 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
1115 #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
1117 #define _PIPEA_MBUS_DBOX_CTL			0x7003C
1118 #define _PIPEB_MBUS_DBOX_CTL			0x7103C
1128 #define MBUS_DBOX_BW_4CREDITS_MTL		REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
1129 #define MBUS_DBOX_BW_8CREDITS_MTL		REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
1134 #define MBUS_DBOX_A_CREDIT_MASK			REG_GENMASK(3, 0)
1137 #define MBUS_UBOX_CTL			_MMIO(0x4503C)
1138 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
1139 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
1141 #define MBUS_CTL			_MMIO(0x4438C)
1144 #define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
1150 #define HDPORT_STATE			_MMIO(0x45050)
1153 #define   HDPORT_ENABLED		REG_BIT(0)
1170 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
1197 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
1207 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
1214 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
1215 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
1217 #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
1219 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
1245 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
1252 	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1290 #define I915_ASLE_INTERRUPT				(1 << 0)
1293 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
1294 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
1297 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
1298 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
1300 #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
1301 #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
1302 #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
1309 #define GEN6_BSD_RNCID			_MMIO(0x12198)
1311 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
1312 #define   GEN7_FF_SCHED_MASK		0x0077070
1315 #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
1316 #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
1317 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
1318 #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
1320 #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
1321 #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
1322 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
1323 #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
1324 #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
1325 #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
1326 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
1327 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
1333 #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
1334 #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
1335 #define FBC_CONTROL		_MMIO(0x3208)
1345 #define   FBC_CTL_FENCENO_MASK		REG_GENMASK(3, 0)
1347 #define FBC_COMMAND		_MMIO(0x320c)
1348 #define   FBC_CMD_COMPRESS		REG_BIT(0)
1349 #define FBC_STATUS		_MMIO(0x3210)
1353 #define   FBC_STAT_CURRENT_LINE_MASK	REG_GENMASK(10, 0)
1354 #define FBC_CONTROL2		_MMIO(0x3214) /* i965gm only */
1357 #define   FBC_CTL_IDLE_IMM		REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
1362 #define   FBC_CTL_PLANE_MASK		REG_GENMASK(1, 0)
1364 #define FBC_FENCE_OFF		_MMIO(0x3218)  /* i965gm only, BSpec typo has 321Bh */
1365 #define FBC_MOD_NUM		_MMIO(0x3220)  /* i965gm only */
1367 #define   FBC_MOD_NUM_VALID		REG_BIT(0)
1368 #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4) /* 49 reisters */
1369 #define   FBC_TAG_MASK			REG_GENMASK(1, 0) /* 16 tags per register */
1370 #define   FBC_TAG_MODIFIED		REG_FIELD_PREP(FBC_TAG_MASK, 0)
1378 #define DPFC_CB_BASE			_MMIO(0x3200)
1379 #define ILK_DPFC_CB_BASE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43200, 0x43240)
1380 #define DPFC_CONTROL			_MMIO(0x3208)
1381 #define ILK_DPFC_CONTROL(fbc_id)	_MMIO_PIPE((fbc_id), 0x43208, 0x43248)
1394 #define   DPFC_CTL_LIMIT_1X			REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
1397 #define   DPFC_CTL_FENCENO_MASK			REG_GENMASK(3, 0)
1399 #define DPFC_RECOMP_CTL			_MMIO(0x320c)
1400 #define ILK_DPFC_RECOMP_CTL(fbc_id)	_MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
1403 #define   DPFC_RECOMP_TIMER_COUNT_MASK		REG_GENMASK(5, 0)
1404 #define DPFC_STATUS			_MMIO(0x3210)
1405 #define ILK_DPFC_STATUS(fbc_id)		_MMIO_PIPE((fbc_id), 0x43210, 0x43250)
1407 #define   DPFC_COMP_SEG_MASK			REG_GENMASK(10, 0)
1408 #define DPFC_STATUS2			_MMIO(0x3214)
1409 #define ILK_DPFC_STATUS2(fbc_id)	_MMIO_PIPE((fbc_id), 0x43214, 0x43254)
1410 #define   DPFC_COMP_SEG_MASK_IVB		REG_GENMASK(11, 0)
1411 #define DPFC_FENCE_YOFF			_MMIO(0x3218)
1412 #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
1413 #define DPFC_CHICKEN			_MMIO(0x3224)
1414 #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
1421 #define GLK_FBC_STRIDE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43228, 0x43268)
1423 #define   FBC_STRIDE_MASK	REG_GENMASK(14, 0)
1426 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
1427 #define   ILK_FBC_RT_VALID	REG_BIT(0)
1430 #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
1435 #define   IVB_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
1440 #define   IVB_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
1451 #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
1453 #define   SNB_DPFC_FENCENO_MASK		REG_GENMASK(4, 0)
1455 #define SNB_DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
1458 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
1459 #define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
1461 #define IPS_CTL		_MMIO(0x43408)
1464 #define MSG_FBC_REND_STATE(fbc_id)	_MMIO_PIPE((fbc_id), 0x50380, 0x50384)
1471 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
1472 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
1473 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
1476 #define VGA0	_MMIO(0x6000)
1477 #define VGA1	_MMIO(0x6004)
1478 #define VGA_PD	_MMIO(0x6010)
1481 #define   VGA0_PD_P1_SHIFT	0
1482 #define   VGA0_PD_P1_MASK	(0x1f << 0)
1486 #define   VGA1_PD_P1_MASK	(0x1f << 8)
1497 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1499 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
1501 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
1502 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
1503 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
1508 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
1509 #define   DPLL_PORTB_READY_MASK		(0xf)
1511 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
1514 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
1515 #define   DPLL_PORTD_READY_MASK		(0xf)
1516 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
1518 #define   PHY_LDO_DELAY_0NS			0x0
1519 #define   PHY_LDO_DELAY_200NS			0x1
1520 #define   PHY_LDO_DELAY_600NS			0x2
1523 #define   PHY_CH_SU_PSR				0x1
1524 #define   PHY_CH_DEEP_PSR			0x7
1527 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
1536 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
1542 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
1552 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
1553 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
1561 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1566 #define   SDVO_MULTIPLIER_MASK			0x000000ff
1568 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
1570 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
1571 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
1572 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
1580 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
1583 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
1602 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
1609 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
1610 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
1612 #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
1614 #define _FPA0	0x6040
1615 #define _FPA1	0x6044
1616 #define _FPB0	0x6048
1617 #define _FPB1	0x604c
1620 #define   FP_N_DIV_MASK		0x003f0000
1621 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
1623 #define   FP_M1_DIV_MASK	0x00003f00
1625 #define   FP_M2_DIV_MASK	0x0000003f
1626 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
1627 #define   FP_M2_DIV_SHIFT		 0
1628 #define DPLL_TEST	_MMIO(0x606c)
1629 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
1638 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
1639 #define D_STATE		_MMIO(0x6104)
1643 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
1644 #define DSPCLK_GATE_D(__i915)		_MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
1681 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
1682 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
1684 #define RENCLK_GATE_D1		_MMIO(0x6204)
1700 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
1717 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
1746 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
1748 #define RENCLK_GATE_D2		_MMIO(0x6208)
1753 #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
1756 #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
1757 #define DEUC			_MMIO(0x6214)          /* CRL only */
1759 #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
1762 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
1764 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
1766 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
1767 #define   CZCLK_FREQ_MASK	0xf
1769 #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
1776 #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
1781 #define _PALETTE_A		0xa000
1782 #define _PALETTE_B		0xa800
1783 #define _CHV_PALETTE_C		0xc000
1786 #define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
1792 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
1794 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
1795 #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
1796 #define XEHPSDV_RP_STATE_CAP	_MMIO(0x250014)
1797 #define PVC_RP_STATE_CAP	_MMIO(0x281014)
1799 #define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)
1800 #define   GT0_PERF_LIMIT_REASONS_MASK	0xde3
1801 #define   PROCHOT_MASK			REG_BIT(0)
1810 #define CHV_CLK_CTL1			_MMIO(0x101100)
1811 #define VLV_CLK_CTL2			_MMIO(0x101104)
1818 #define OVADD			_MMIO(0x30000)
1819 #define DOVSTA			_MMIO(0x30008)
1820 #define OC_BUF			(0x3 << 20)
1821 #define OGAMC5			_MMIO(0x30010)
1822 #define OGAMC4			_MMIO(0x30014)
1823 #define OGAMC3			_MMIO(0x30018)
1824 #define OGAMC2			_MMIO(0x3001c)
1825 #define OGAMC1			_MMIO(0x30020)
1826 #define OGAMC0			_MMIO(0x30024)
1831 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
1836 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
1840 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
1843 #define GEN9_CLKGATE_DIS_5		_MMIO(0x46540)
1846 #define _CLKGATE_DIS_PSL_A		0x46520
1847 #define _CLKGATE_DIS_PSL_B		0x46524
1848 #define _CLKGATE_DIS_PSL_C		0x46528
1860 #define _CLKGATE_DIS_PSL_EXT_A		0x4654C
1861 #define _CLKGATE_DIS_PSL_EXT_B		0x46550
1872 #define _PIPE_CRC_CTL_A			0x60050
1876 #define   PIPE_CRC_SOURCE_PLANE_1_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
1886 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
1891 #define   PIPE_CRC_SOURCE_PRIMARY_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
1899 #define   PIPE_CRC_SOURCE_PIPE_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
1908 #define   PIPE_CRC_SOURCE_PIPE_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
1920 #define _PIPE_CRC_RES_1_A_IVB		0x60064
1921 #define _PIPE_CRC_RES_2_A_IVB		0x60068
1922 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
1923 #define _PIPE_CRC_RES_4_A_IVB		0x60070
1924 #define _PIPE_CRC_RES_5_A_IVB		0x60074
1926 #define _PIPE_CRC_RES_RED_A		0x60060
1927 #define _PIPE_CRC_RES_GREEN_A		0x60064
1928 #define _PIPE_CRC_RES_BLUE_A		0x60068
1929 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
1930 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
1933 #define _PIPE_CRC_RES_1_B_IVB		0x61064
1934 #define _PIPE_CRC_RES_2_B_IVB		0x61068
1935 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
1936 #define _PIPE_CRC_RES_4_B_IVB		0x61070
1937 #define _PIPE_CRC_RES_5_B_IVB		0x61074
1953 #define _HTOTAL_A	0x60000
1954 #define _HBLANK_A	0x60004
1955 #define _HSYNC_A	0x60008
1956 #define _VTOTAL_A	0x6000c
1957 #define _VBLANK_A	0x60010
1958 #define _VSYNC_A	0x60014
1959 #define _EXITLINE_A	0x60018
1960 #define _PIPEASRC	0x6001c
1963 #define   PIPESRC_HEIGHT_MASK	REG_GENMASK(15, 0)
1965 #define _BCLRPAT_A	0x60020
1966 #define _VSYNCSHIFT_A	0x60028
1967 #define _PIPE_MULT_A	0x6002c
1970 #define _HTOTAL_B	0x61000
1971 #define _HBLANK_B	0x61004
1972 #define _HSYNC_B	0x61008
1973 #define _VTOTAL_B	0x6100c
1974 #define _VBLANK_B	0x61010
1975 #define _VSYNC_B	0x61014
1976 #define _PIPEBSRC	0x6101c
1977 #define _BCLRPAT_B	0x61020
1978 #define _VSYNCSHIFT_B	0x61028
1979 #define _PIPE_MULT_B	0x6102c
1981 /* DSI 0 timing regs */
1982 #define _HTOTAL_DSI0		0x6b000
1983 #define _HSYNC_DSI0		0x6b008
1984 #define _VTOTAL_DSI0		0x6b00c
1985 #define _VSYNC_DSI0		0x6b014
1986 #define _VSYNCSHIFT_DSI0	0x6b028
1989 #define _HTOTAL_DSI1		0x6b800
1990 #define _HSYNC_DSI1		0x6b808
1991 #define _VTOTAL_DSI1		0x6b80c
1992 #define _VSYNC_DSI1		0x6b814
1993 #define _VSYNCSHIFT_DSI1	0x6b828
1995 #define TRANSCODER_A_OFFSET 0x60000
1996 #define TRANSCODER_B_OFFSET 0x61000
1997 #define TRANSCODER_C_OFFSET 0x62000
1998 #define CHV_TRANSCODER_C_OFFSET 0x63000
1999 #define TRANSCODER_D_OFFSET 0x63000
2000 #define TRANSCODER_EDP_OFFSET 0x6f000
2001 #define TRANSCODER_DSI0_OFFSET	0x6b000
2002 #define TRANSCODER_DSI1_OFFSET	0x6b800
2017 #define   EXITLINE_MASK		REG_GENMASK(12, 0)
2018 #define   EXITLINE_SHIFT	0
2021 #define _TRANS_VRR_CTL_A		0x60420
2022 #define _TRANS_VRR_CTL_B		0x61420
2023 #define _TRANS_VRR_CTL_C		0x62420
2024 #define _TRANS_VRR_CTL_D		0x63420
2031 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
2032 #define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
2035 #define _TRANS_VRR_VMAX_A		0x60424
2036 #define _TRANS_VRR_VMAX_B		0x61424
2037 #define _TRANS_VRR_VMAX_C		0x62424
2038 #define _TRANS_VRR_VMAX_D		0x63424
2040 #define   VRR_VMAX_MASK			REG_GENMASK(19, 0)
2042 #define _TRANS_VRR_VMIN_A		0x60434
2043 #define _TRANS_VRR_VMIN_B		0x61434
2044 #define _TRANS_VRR_VMIN_C		0x62434
2045 #define _TRANS_VRR_VMIN_D		0x63434
2047 #define   VRR_VMIN_MASK			REG_GENMASK(15, 0)
2049 #define _TRANS_VRR_VMAXSHIFT_A		0x60428
2050 #define _TRANS_VRR_VMAXSHIFT_B		0x61428
2051 #define _TRANS_VRR_VMAXSHIFT_C		0x62428
2052 #define _TRANS_VRR_VMAXSHIFT_D		0x63428
2057 #define   VRR_VMAXSHIFT_INC_MASK	REG_GENMASK(12, 0)
2059 #define _TRANS_VRR_STATUS_A		0x6042C
2060 #define _TRANS_VRR_STATUS_B		0x6142C
2061 #define _TRANS_VRR_STATUS_C		0x6242C
2062 #define _TRANS_VRR_STATUS_D		0x6342C
2071 #define   STATUS_FSM_IDLE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
2079 #define _TRANS_VRR_VTOTAL_PREV_A	0x60480
2080 #define _TRANS_VRR_VTOTAL_PREV_B	0x61480
2081 #define _TRANS_VRR_VTOTAL_PREV_C	0x62480
2082 #define _TRANS_VRR_VTOTAL_PREV_D	0x63480
2088 #define   VRR_VTOTAL_PREV_FRAME_MASK	REG_GENMASK(19, 0)
2090 #define _TRANS_VRR_FLIPLINE_A		0x60438
2091 #define _TRANS_VRR_FLIPLINE_B		0x61438
2092 #define _TRANS_VRR_FLIPLINE_C		0x62438
2093 #define _TRANS_VRR_FLIPLINE_D		0x63438
2096 #define   VRR_FLIPLINE_MASK		REG_GENMASK(19, 0)
2098 #define _TRANS_VRR_STATUS2_A		0x6043C
2099 #define _TRANS_VRR_STATUS2_B		0x6143C
2100 #define _TRANS_VRR_STATUS2_C		0x6243C
2101 #define _TRANS_VRR_STATUS2_D		0x6343C
2103 #define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
2105 #define _TRANS_PUSH_A			0x60A70
2106 #define _TRANS_PUSH_B			0x61A70
2107 #define _TRANS_PUSH_C			0x62A70
2108 #define _TRANS_PUSH_D			0x63A70
2116  * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
2119 #define _SRD_CTL_A				0x60800
2120 #define _SRD_CTL_EDP				0x6f800
2127 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0 << 25)
2133 #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
2136 #define   EDP_PSR_TP2_TP3_TIME_500us		(0 << 8)
2141 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
2145 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
2148  * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
2152 #define EDP_PSR_IMR				_MMIO(0x64834)
2153 #define EDP_PSR_IIR				_MMIO(0x64838)
2154 #define _PSR_IMR_A				0x60814
2155 #define _PSR_IIR_A				0x60818
2159 						 0 : ((trans) - TRANSCODER_A + 1) * 8)
2160 #define   TGL_PSR_MASK			REG_GENMASK(2, 0)
2163 #define   TGL_PSR_PRE_ENTRY		REG_BIT(0)
2173 #define _SRD_AUX_DATA_A				0x60814
2174 #define _SRD_AUX_DATA_EDP			0x6f814
2177 #define _SRD_STATUS_A				0x60840
2178 #define _SRD_STATUS_EDP				0x6f840
2182 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
2190 #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0 << 26)
2194 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
2196 #define   EDP_PSR_STATUS_COUNT_MASK		0xf
2202 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
2204 #define _SRD_PERF_CNT_A			0x60844
2205 #define _SRD_PERF_CNT_EDP		0x6f844
2207 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
2210 #define _SRD_DEBUG_A				0x60860
2211 #define _SRD_DEBUG_EDP				0x6f860
2220 #define _PSR2_CTL_A				0x60900
2221 #define _PSR2_CTL_EDP				0x6f900
2225 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
2230 #define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)
2245 #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
2251 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK		(0xf << 4)
2253 #define   EDP_PSR2_IDLE_FRAME_MASK		0xf
2254 #define   EDP_PSR2_IDLE_FRAME_SHIFT		0
2256 #define _PSR_EVENT_TRANS_A			0x60848
2257 #define _PSR_EVENT_TRANS_B			0x61848
2258 #define _PSR_EVENT_TRANS_C			0x62848
2259 #define _PSR_EVENT_TRANS_D			0x63848
2260 #define _PSR_EVENT_TRANS_EDP			0x6f848
2277 #define  PSR_EVENT_PSR_DISABLE			(1 << 0)
2279 #define _PSR2_STATUS_A				0x60940
2280 #define _PSR2_STATUS_EDP			0x6f940
2283 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP	REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
2285 #define _PSR2_SU_STATUS_A		0x60914
2286 #define _PSR2_SU_STATUS_EDP		0x6f914
2290 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
2293 #define _PSR2_MAN_TRK_CTL_A					0x60910
2294 #define _PSR2_MAN_TRK_CTL_EDP					0x6f910
2306 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
2313 #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
2314 #define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
2315 #define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
2316 #define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
2317 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
2318 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
2319 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
2320 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
2321 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
2322 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
2323 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
2324 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
2339 #define RC_MIN_QP_SHIFT				0
2341 #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
2342 #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
2343 #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
2344 #define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
2345 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
2346 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
2347 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
2348 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
2349 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
2350 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
2351 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
2352 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
2366 #define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
2367 #define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
2368 #define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
2369 #define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
2370 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
2371 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
2372 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
2373 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
2374 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
2375 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
2376 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
2377 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
2391 #define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
2392 #define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
2393 #define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
2394 #define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
2395 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
2396 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
2397 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
2398 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
2399 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
2400 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
2401 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
2402 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
2417 #define ADPA			_MMIO(0x61100)
2418 #define PCH_ADPA                _MMIO(0xe1100)
2419 #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
2422 #define   ADPA_DAC_DISABLE	0
2429 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
2430 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
2435 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
2437 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
2439 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
2441 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
2445 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
2449 #define   ADPA_SETS_HVPOLARITY	0
2451 #define   ADPA_VSYNC_CNTL_ENABLE 0
2453 #define   ADPA_HSYNC_CNTL_ENABLE 0
2455 #define   ADPA_VSYNC_ACTIVE_LOW	0
2457 #define   ADPA_HSYNC_ACTIVE_LOW	0
2459 #define   ADPA_DPMS_ON		(0 << 10)
2466 #define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
2481 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
2484 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
2486 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
2491 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
2493 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
2496 #define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
2527 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
2562 #define _GEN3_SDVOB	0x61140
2563 #define _GEN3_SDVOC	0x61160
2568 #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
2569 #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
2570 #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
2571 #define PCH_SDVOB	_MMIO(0xe1140)
2573 #define PCH_HDMIC	_MMIO(0xe1150)
2574 #define PCH_HDMID	_MMIO(0xe1160)
2576 #define PORT_DFT_I9XX				_MMIO(0x61150)
2578 #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
2580 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
2583 #define   PIPE_A_SCRAMBLE_RESET			REG_BIT(0)
2612 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
2614 #define   SDVO_ENCODING_SDVO			(0 << 10)
2617 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
2640 #define _DVOA			0x61120
2642 #define _DVOB			0x61140
2644 #define _DVOC			0x61160
2650 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
2655 #define   DVO_DATA_ORDER_I740		(0 << 14)
2663 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
2664 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
2670 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
2671 #define   DVO_PRESERVE_MASK		(0x7 << 24)
2672 #define DVOA_SRCDIM		_MMIO(0x61124)
2673 #define DVOB_SRCDIM		_MMIO(0x61144)
2674 #define DVOC_SRCDIM		_MMIO(0x61164)
2676 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
2679 #define LVDS			_MMIO(0x61180)
2705 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
2713 #define   LVDS_A3_POWER_DOWN		(0 << 6)
2720 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
2728 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
2732 #define VIDEO_DIP_DATA		_MMIO(0x61178)
2740 #define VIDEO_DIP_CTL		_MMIO(0x61170)
2750 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
2755 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
2762 #define   VSC_SELECT_MASK		(0x3 << 25)
2764 #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
2774 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
2777 #define PPS_BASE			0x61200
2779 #define PCH_PPS_BASE			0xC7200
2783 					      (pps_idx) * 0x100)
2785 #define _PP_STATUS			0x61200
2797 #define   PP_SEQUENCE_NONE		REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
2801 #define   PP_SEQUENCE_STATE_MASK	REG_GENMASK(3, 0)
2802 #define   PP_SEQUENCE_STATE_OFF_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
2803 #define   PP_SEQUENCE_STATE_OFF_S0_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
2804 #define   PP_SEQUENCE_STATE_OFF_S0_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
2805 #define   PP_SEQUENCE_STATE_OFF_S0_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
2806 #define   PP_SEQUENCE_STATE_ON_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
2807 #define   PP_SEQUENCE_STATE_ON_S1_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
2808 #define   PP_SEQUENCE_STATE_ON_S1_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
2809 #define   PP_SEQUENCE_STATE_ON_S1_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
2810 #define   PP_SEQUENCE_STATE_RESET	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
2812 #define _PP_CONTROL			0x61204
2815 #define  PANEL_UNLOCK_REGS		REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
2820 #define  PANEL_POWER_ON			REG_BIT(0)
2822 #define _PP_ON_DELAYS			0x61208
2825 #define  PANEL_PORT_SELECT_LVDS		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
2831 #define  PANEL_LIGHT_ON_DELAY_MASK	REG_GENMASK(12, 0)
2833 #define _PP_OFF_DELAYS			0x6120C
2836 #define  PANEL_LIGHT_OFF_DELAY_MASK	REG_GENMASK(12, 0)
2838 #define _PP_DIVISOR			0x61210
2841 #define  PANEL_POWER_CYCLE_DELAY_MASK	REG_GENMASK(4, 0)
2844 #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
2849 #define   VERT_INTERP_DISABLE	(0 << 10)
2853 #define   HORIZ_INTERP_DISABLE	(0 << 6)
2858 #define   PFIT_FILTER_FUZZY	(0 << 24)
2859 #define   PFIT_SCALING_AUTO	(0 << 26)
2863 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
2866 #define		PFIT_VERT_SCALE_MASK		0xfff00000
2868 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
2871 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
2872 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
2873 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
2875 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
2877 #define PCH_GTC_CTL		_MMIO(0xe7000)
2881 #define TV_CTL			_MMIO(0x68000)
2889 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
2900 # define TV_OVERSAMPLE_4X		(0 << 18)
2923 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2926 # define TV_FUSE_STATE_ENABLED		(0 << 4)
2932 # define TV_TEST_MODE_NORMAL		(0 << 0)
2934 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
2936 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
2938 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
2940 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
2942 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
2948 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
2949 # define TV_TEST_MODE_MASK		(7 << 0)
2951 #define TV_DAC			_MMIO(0x68004)
2952 # define TV_DAC_SAVE		0x00ffff00
2983 # define DAC_A_1_3_V			(0 << 4)
2987 # define DAC_B_1_3_V			(0 << 2)
2991 # define DAC_C_1_3_V			(0 << 0)
2992 # define DAC_C_1_1_V			(1 << 0)
2993 # define DAC_C_0_7_V			(2 << 0)
2994 # define DAC_C_MASK			(3 << 0)
3000  * -1 (0x3) being the only legal negative value.
3002 #define TV_CSC_Y		_MMIO(0x68010)
3003 # define TV_RY_MASK			0x07ff0000
3005 # define TV_GY_MASK			0x00000fff
3006 # define TV_GY_SHIFT			0
3008 #define TV_CSC_Y2		_MMIO(0x68014)
3009 # define TV_BY_MASK			0x07ff0000
3016 # define TV_AY_MASK			0x000003ff
3017 # define TV_AY_SHIFT			0
3019 #define TV_CSC_U		_MMIO(0x68018)
3020 # define TV_RU_MASK			0x07ff0000
3022 # define TV_GU_MASK			0x000007ff
3023 # define TV_GU_SHIFT			0
3025 #define TV_CSC_U2		_MMIO(0x6801c)
3026 # define TV_BU_MASK			0x07ff0000
3033 # define TV_AU_MASK			0x000003ff
3034 # define TV_AU_SHIFT			0
3036 #define TV_CSC_V		_MMIO(0x68020)
3037 # define TV_RV_MASK			0x0fff0000
3039 # define TV_GV_MASK			0x000007ff
3040 # define TV_GV_SHIFT			0
3042 #define TV_CSC_V2		_MMIO(0x68024)
3043 # define TV_BV_MASK			0x07ff0000
3050 # define TV_AV_MASK			0x000007ff
3051 # define TV_AV_SHIFT			0
3053 #define TV_CLR_KNOBS		_MMIO(0x68028)
3055 # define TV_BRIGHTNESS_MASK		0xff000000
3058 # define TV_CONTRAST_MASK		0x00ff0000
3061 # define TV_SATURATION_MASK		0x0000ff00
3064 # define TV_HUE_MASK			0x000000ff
3065 # define TV_HUE_SHIFT			0
3067 #define TV_CLR_LEVEL		_MMIO(0x6802c)
3069 # define TV_BLACK_LEVEL_MASK		0x01ff0000
3072 # define TV_BLANK_LEVEL_MASK		0x000001ff
3073 # define TV_BLANK_LEVEL_SHIFT		0
3075 #define TV_H_CTL_1		_MMIO(0x68030)
3077 # define TV_HSYNC_END_MASK		0x1fff0000
3080 # define TV_HTOTAL_MASK			0x00001fff
3081 # define TV_HTOTAL_SHIFT		0
3083 #define TV_H_CTL_2		_MMIO(0x68034)
3088 # define TV_HBURST_START_MASK		0x1fff0000
3090 # define TV_HBURST_LEN_SHIFT		0
3091 # define TV_HBURST_LEN_MASK		0x0001fff
3093 #define TV_H_CTL_3		_MMIO(0x68038)
3096 # define TV_HBLANK_END_MASK		0x1fff0000
3098 # define TV_HBLANK_START_SHIFT		0
3099 # define TV_HBLANK_START_MASK		0x0001fff
3101 #define TV_V_CTL_1		_MMIO(0x6803c)
3104 # define TV_NBR_END_MASK		0x07ff0000
3107 # define TV_VI_END_F1_MASK		0x00003f00
3109 # define TV_VI_END_F2_SHIFT		0
3110 # define TV_VI_END_F2_MASK		0x0000003f
3112 #define TV_V_CTL_2		_MMIO(0x68040)
3114 # define TV_VSYNC_LEN_MASK		0x07ff0000
3119 # define TV_VSYNC_START_F1_MASK		0x00007f00
3125 # define TV_VSYNC_START_F2_MASK		0x0000007f
3126 # define TV_VSYNC_START_F2_SHIFT	0
3128 #define TV_V_CTL_3		_MMIO(0x68044)
3132 # define TV_VEQ_LEN_MASK		0x007f0000
3137 # define TV_VEQ_START_F1_MASK		0x0007f00
3143 # define TV_VEQ_START_F2_MASK		0x000007f
3144 # define TV_VEQ_START_F2_SHIFT		0
3146 #define TV_V_CTL_4		_MMIO(0x68048)
3151 # define TV_VBURST_START_F1_MASK	0x003f0000
3157 # define TV_VBURST_END_F1_MASK		0x000000ff
3158 # define TV_VBURST_END_F1_SHIFT		0
3160 #define TV_V_CTL_5		_MMIO(0x6804c)
3165 # define TV_VBURST_START_F2_MASK	0x003f0000
3171 # define TV_VBURST_END_F2_MASK		0x000000ff
3172 # define TV_VBURST_END_F2_SHIFT		0
3174 #define TV_V_CTL_6		_MMIO(0x68050)
3179 # define TV_VBURST_START_F3_MASK	0x003f0000
3185 # define TV_VBURST_END_F3_MASK		0x000000ff
3186 # define TV_VBURST_END_F3_SHIFT		0
3188 #define TV_V_CTL_7		_MMIO(0x68054)
3193 # define TV_VBURST_START_F4_MASK	0x003f0000
3199 # define TV_VBURST_END_F4_MASK		0x000000ff
3200 # define TV_VBURST_END_F4_SHIFT		0
3202 #define TV_SC_CTL_1		_MMIO(0x68060)
3210 # define TV_SC_RESET_EVERY_2		(0 << 24)
3218 # define TV_BURST_LEVEL_MASK		0x00ff0000
3221 # define TV_SCDDA1_INC_MASK		0x00000fff
3222 # define TV_SCDDA1_INC_SHIFT		0
3224 #define TV_SC_CTL_2		_MMIO(0x68064)
3226 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
3229 # define TV_SCDDA2_INC_MASK		0x00007fff
3230 # define TV_SCDDA2_INC_SHIFT		0
3232 #define TV_SC_CTL_3		_MMIO(0x68068)
3234 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
3237 # define TV_SCDDA3_INC_MASK		0x00007fff
3238 # define TV_SCDDA3_INC_SHIFT		0
3240 #define TV_WIN_POS		_MMIO(0x68070)
3242 # define TV_XPOS_MASK			0x1fff0000
3245 # define TV_YPOS_MASK			0x00000fff
3246 # define TV_YPOS_SHIFT			0
3248 #define TV_WIN_SIZE		_MMIO(0x68074)
3250 # define TV_XSIZE_MASK			0x1fff0000
3257 # define TV_YSIZE_MASK			0x00000fff
3258 # define TV_YSIZE_SHIFT			0
3260 #define TV_FILTER_CTL_1		_MMIO(0x68080)
3277 # define TV_VADAPT_MODE_LEAST		(0 << 26)
3290 # define TV_HSCALE_FRAC_MASK		0x00003fff
3291 # define TV_HSCALE_FRAC_SHIFT		0
3293 #define TV_FILTER_CTL_2		_MMIO(0x68084)
3299 # define TV_VSCALE_INT_MASK		0x00038000
3306 # define TV_VSCALE_FRAC_MASK		0x00007fff
3307 # define TV_VSCALE_FRAC_SHIFT		0
3309 #define TV_FILTER_CTL_3		_MMIO(0x68088)
3317 # define TV_VSCALE_IP_INT_MASK		0x00038000
3326 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
3327 # define TV_VSCALE_IP_FRAC_SHIFT		0
3329 #define TV_CC_CONTROL		_MMIO(0x68090)
3334  * CC data is usually sent in field 0.
3339 # define TV_CC_HOFF_MASK		0x03ff0000
3342 # define TV_CC_LINE_MASK		0x0000003f
3343 # define TV_CC_LINE_SHIFT		0
3345 #define TV_CC_DATA		_MMIO(0x68094)
3348 # define TV_CC_DATA_2_MASK		0x007f0000
3351 # define TV_CC_DATA_1_MASK		0x0000007f
3352 # define TV_CC_DATA_1_SHIFT		0
3354 #define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
3355 #define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
3356 #define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
3357 #define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
3360 #define DP_A			_MMIO(0x64000) /* eDP */
3361 #define DP_B			_MMIO(0x64100)
3362 #define DP_C			_MMIO(0x64200)
3363 #define DP_D			_MMIO(0x64300)
3365 #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
3366 #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
3367 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
3381 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
3389 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
3397 #define   DP_VOLTAGE_0_4		(0 << 25)
3407 #define   DP_PRE_EMPHASIS_0		(0 << 22)
3423 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
3457 #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
3458 #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
3460 #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
3461 #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
3466 #define _XELPDP_USBC1_AUX_CH_CTL	0x16F210
3467 #define _XELPDP_USBC2_AUX_CH_CTL	0x16F410
3468 #define _XELPDP_USBC3_AUX_CH_CTL	0x16F610
3469 #define _XELPDP_USBC4_AUX_CH_CTL	0x16F810
3474 						       0, /* port/aux_ch C is non-existent */ \
3480 #define _XELPDP_USBC1_AUX_CH_DATA1      0x16F214
3481 #define _XELPDP_USBC2_AUX_CH_DATA1      0x16F414
3482 #define _XELPDP_USBC3_AUX_CH_DATA1      0x16F614
3483 #define _XELPDP_USBC4_AUX_CH_DATA1      0x16F814
3488 						       0, /* port/aux_ch C is non-existent */ \
3498 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
3504 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
3508 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
3515 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
3516 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
3521 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
3538 #define _PIPEA_DATA_M_G4X	0x70050
3539 #define _PIPEB_DATA_M_G4X	0x71050
3541 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3545 #define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
3546 #define  DATA_LINK_N_MAX	(0x800000)
3548 #define _PIPEA_DATA_N_G4X	0x70054
3549 #define _PIPEB_DATA_N_G4X	0x71054
3562 #define _PIPEA_LINK_M_G4X	0x70060
3563 #define _PIPEB_LINK_M_G4X	0x71060
3564 #define _PIPEA_LINK_N_G4X	0x70064
3565 #define _PIPEB_LINK_N_G4X	0x71064
3575 #define _PIPEADSL		0x70000
3577 #define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)
3578 #define _PIPEACONF		0x70008
3584 …ECONF_FRAME_START_DELAY(x)		REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
3589 #define   PIPECONF_GAMMA_MODE_8BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
3595 #define   PIPECONF_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
3606 #define   PIPECONF_INTERLACE_PF_PD_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
3618 #define   PIPECONF_OUTPUT_COLORSPACE_RGB	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-…
3623 #define   PIPECONF_BPC_8			REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
3629 #define   PIPECONF_DITHER_TYPE_SP		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
3633 #define _PIPEASTAT		0x70024
3678 #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
3679 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
3681 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
3682 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
3684 #define PIPE_A_OFFSET		0x70000
3685 #define PIPE_B_OFFSET		0x71000
3686 #define PIPE_C_OFFSET		0x72000
3687 #define PIPE_D_OFFSET		0x73000
3688 #define CHV_PIPE_C_OFFSET	0x74000
3695 #define PIPE_EDP_OFFSET	0x7f000
3697 /* ICL DSI 0 and 1 */
3698 #define PIPE_DSI0_OFFSET	0x7b000
3699 #define PIPE_DSI1_OFFSET	0x7b800
3707 #define  _PIPEAGCMAX           0x70010
3708 #define  _PIPEBGCMAX           0x71010
3711 #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
3715 #define _PIPE_MISC_A			0x70030
3716 #define _PIPE_MISC_B			0x71030
3729 #define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
3735 #define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
3741 #define _PIPE_MISC2_A					0x7002C
3742 #define _PIPE_MISC2_B					0x7102C
3749 #define _SKL_BOTTOM_COLOR_A		0x70034
3754 #define _ICL_PIPE_A_STATUS			0x70058
3761 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
3782 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3797 #define   DPINVGTT_STATUS_MASK_CHV			REG_GENMASK(11, 0)
3798 #define   DPINVGTT_STATUS_MASK_VLV			REG_GENMASK(7, 0)
3810 #define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
3812 #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
3813 #define   DSPARB_CSTART_MASK	(0x7f << 7)
3815 #define   DSPARB_BSTART_MASK	(0x7f)
3816 #define   DSPARB_BSTART_SHIFT	0
3818 #define   DSPARB_AEND_SHIFT	0
3819 #define   DSPARB_SPRITEA_SHIFT_VLV	0
3820 #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
3822 #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
3824 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
3826 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
3827 #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
3828 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
3829 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
3831 #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
3833 #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
3835 #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
3837 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
3839 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
3840 #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
3841 #define   DSPARB_SPRITEE_SHIFT_VLV	0
3842 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
3844 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
3847 #define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
3849 #define   DSPFW_SR_MASK			(0x1ff << 23)
3851 #define   DSPFW_CURSORB_MASK		(0x3f << 16)
3853 #define   DSPFW_PLANEB_MASK		(0x7f << 8)
3854 #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
3855 #define   DSPFW_PLANEA_SHIFT		0
3856 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
3857 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
3858 #define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
3861 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
3863 #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
3865 #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
3866 #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
3868 #define   DSPFW_CURSORA_MASK		(0x3f << 8)
3869 #define   DSPFW_PLANEC_OLD_SHIFT	0
3870 #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
3871 #define   DSPFW_SPRITEA_SHIFT		0
3872 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
3873 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
3874 #define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
3878 #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
3880 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
3881 #define   DSPFW_HPLL_SR_SHIFT		0
3882 #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
3885 #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
3887 #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
3889 #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
3890 #define   DSPFW_SPRITEA_WM1_SHIFT	0
3891 #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
3892 #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
3894 #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
3896 #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
3898 #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
3899 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
3900 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
3901 #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
3902 #define   DSPFW_SR_WM1_SHIFT		0
3903 #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
3904 #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
3905 #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
3907 #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
3909 #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
3911 #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
3912 #define   DSPFW_SPRITEC_SHIFT		0
3913 #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
3914 #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
3916 #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
3918 #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
3920 #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
3921 #define   DSPFW_SPRITEE_SHIFT		0
3922 #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
3923 #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
3925 #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
3927 #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
3929 #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
3930 #define   DSPFW_CURSORC_SHIFT		0
3931 #define   DSPFW_CURSORC_MASK		(0x3f << 0)
3934 #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
3953 #define   DSPFW_PLANEA_HI_SHIFT		0
3954 #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
3955 #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
3974 #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
3975 #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
3978 #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
3981 #define DDL_PLANE_SHIFT			0
3983 #define DDL_PRECISION_LOW		(0 << 7)
3984 #define DRAIN_LATENCY_MASK		0x7f
3986 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
3990 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
4006 #define VALLEYVIEW_MAX_WM	0xff
4007 #define G4X_MAX_WM		0x3f
4008 #define I915_MAX_WM		0x3f
4012 #define PINEVIEW_MAX_WM		0x1ff
4013 #define PINEVIEW_DFT_WM		0x3f
4014 #define PINEVIEW_DFT_HPLLOFF_WM	0
4017 #define PINEVIEW_CURSOR_MAX_WM	0x3f
4018 #define PINEVIEW_CURSOR_DFT_WM	0
4027 #define _CUR_WM_A_0		0x70140
4028 #define _CUR_WM_B_0		0x71140
4029 #define _CUR_WM_SAGV_A		0x70158
4030 #define _CUR_WM_SAGV_B		0x71158
4031 #define _CUR_WM_SAGV_TRANS_A	0x7015C
4032 #define _CUR_WM_SAGV_TRANS_B	0x7115C
4033 #define _CUR_WM_TRANS_A		0x70168
4034 #define _CUR_WM_TRANS_B		0x71168
4035 #define _PLANE_WM_1_A_0		0x70240
4036 #define _PLANE_WM_1_B_0		0x71240
4037 #define _PLANE_WM_2_A_0		0x70340
4038 #define _PLANE_WM_2_B_0		0x71340
4039 #define _PLANE_WM_SAGV_1_A	0x70258
4040 #define _PLANE_WM_SAGV_1_B	0x71258
4041 #define _PLANE_WM_SAGV_2_A	0x70358
4042 #define _PLANE_WM_SAGV_2_B	0x71358
4043 #define _PLANE_WM_SAGV_TRANS_1_A	0x7025C
4044 #define _PLANE_WM_SAGV_TRANS_1_B	0x7125C
4045 #define _PLANE_WM_SAGV_TRANS_2_A	0x7035C
4046 #define _PLANE_WM_SAGV_TRANS_2_B	0x7135C
4047 #define _PLANE_WM_TRANS_1_A	0x70268
4048 #define _PLANE_WM_TRANS_1_B	0x71268
4049 #define _PLANE_WM_TRANS_2_A	0x70368
4050 #define _PLANE_WM_TRANS_2_B	0x71368
4054 #define   PLANE_WM_BLOCKS_MASK	REG_GENMASK(11, 0)
4087 #define _WM0_PIPEA_ILK		0x45100
4088 #define _WM0_PIPEB_ILK		0x45104
4089 #define _WM0_PIPEC_IVB		0x45200
4094 #define  WM0_PIPE_CURSOR_MASK	REG_GENMASK(7, 0)
4098 #define WM1_LP_ILK		_MMIO(0x45108)
4099 #define WM2_LP_ILK		_MMIO(0x4510c)
4100 #define WM3_LP_ILK		_MMIO(0x45110)
4106 #define  WM_LP_CURSOR_MASK	REG_GENMASK(7, 0)
4112 #define WM1S_LP_ILK		_MMIO(0x45120)
4113 #define WM2S_LP_IVB		_MMIO(0x45124)
4114 #define WM3S_LP_IVB		_MMIO(0x45128)
4116 #define  WM_LP_SPRITE_MASK	REG_GENMASK(10, 0)
4134 #define _PIPEAFRAMEHIGH          0x70040
4135 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
4136 #define   PIPE_FRAME_HIGH_SHIFT   0
4137 #define _PIPEAFRAMEPIXEL         0x70044
4138 #define   PIPE_FRAME_LOW_MASK     0xff000000
4140 #define   PIPE_PIXEL_MASK         0x00ffffff
4141 #define   PIPE_PIXEL_SHIFT        0
4143 #define _PIPEA_FRMCOUNT_G4X	0x70040
4144 #define _PIPEA_FLIPCOUNT_G4X	0x70044
4149 #define _CURACNTR		0x70080
4156 #define   CURSOR_FORMAT_2C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
4170 #define   MCURSOR_MODE_MASK		0x27
4171 #define   MCURSOR_MODE_DISABLE		0x00
4172 #define   MCURSOR_MODE_128_32B_AX	0x02
4173 #define   MCURSOR_MODE_256_32B_AX	0x03
4174 #define   MCURSOR_MODE_64_32B_AX	0x07
4175 #define   MCURSOR_MODE_128_ARGB_AX	(0x20 | MCURSOR_MODE_128_32B_AX)
4176 #define   MCURSOR_MODE_256_ARGB_AX	(0x20 | MCURSOR_MODE_256_32B_AX)
4177 #define   MCURSOR_MODE_64_ARGB_AX	(0x20 | MCURSOR_MODE_64_32B_AX)
4178 #define _CURABASE		0x70084
4179 #define _CURAPOS		0x70088
4184 #define   CURSOR_POS_X_MASK		REG_GENMASK(14, 0)
4186 #define _CURASIZE		0x700a0 /* 845/865 */
4189 #define   CURSOR_WIDTH_MASK		REG_GENMASK(9, 0)
4191 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
4193 #define   CUR_FBC_HEIGHT_MASK		REG_GENMASK(7, 0)
4195 #define _CURASURFLIVE		0x700ac /* g4x+ */
4196 #define _CURBCNTR		0x700c0
4197 #define _CURBBASE		0x700c4
4198 #define _CURBPOS		0x700c8
4200 #define _CURBCNTR_IVB		0x71080
4201 #define _CURBBASE_IVB		0x71084
4202 #define _CURBPOS_IVB		0x71088
4211 #define CURSOR_A_OFFSET 0x70080
4212 #define CURSOR_B_OFFSET 0x700c0
4213 #define CHV_CURSOR_C_OFFSET 0x700e0
4214 #define IVB_CURSOR_B_OFFSET 0x71080
4215 #define IVB_CURSOR_C_OFFSET 0x72080
4216 #define TGL_CURSOR_D_OFFSET 0x73080
4219 #define _DSPAADDR_VLV				0x7017C /* vlv/chv */
4220 #define _DSPACNTR				0x70180
4250 #define _DSPAADDR				0x70184
4251 #define _DSPASTRIDE				0x70188
4252 #define _DSPAPOS				0x7018C /* reserved */
4255 #define   DISP_POS_X_MASK		REG_GENMASK(15, 0)
4257 #define _DSPASIZE				0x70190
4260 #define   DISP_WIDTH_MASK		REG_GENMASK(15, 0)
4262 #define _DSPASURF				0x7019C /* 965+ only */
4264 #define _DSPATILEOFF				0x701A4 /* 965+ only */
4267 #define   DISP_OFFSET_X_MASK		REG_GENMASK(15, 0)
4269 #define _DSPAOFFSET				0x701A4 /* HSW */
4270 #define _DSPASURFLIVE				0x701AC
4271 #define _DSPAGAMC				0x701E0
4287 #define _CHV_BLEND_A		0x60a00
4289 #define   CHV_BLEND_LEGACY	REG_FIELD_PREP(CHV_BLEND_MASK, 0)
4292 #define _CHV_CANVAS_A		0x60a04
4295 #define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)
4296 #define _PRIMPOS_A		0x60a08
4299 #define   PRIM_POS_X_MASK	REG_GENMASK(15, 0)
4301 #define _PRIMSIZE_A		0x60a0c
4304 #define   PRIM_WIDTH_MASK	REG_GENMASK(15, 0)
4306 #define _PRIMCNSTALPHA_A	0x60a10
4308 #define   PRIM_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
4318 #define DISP_BASEADDR_MASK	(0xfffff000)
4329  * [00:0f] all
4333 #define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
4334 #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
4335 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
4336 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
4339 #define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
4340 #define _PIPEBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
4341 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
4342 #define _PIPEBFRAMEHIGH		0x71040
4343 #define _PIPEBFRAMEPIXEL	0x71044
4344 #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
4345 #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
4349 #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
4351 #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
4352 #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
4353 #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
4354 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
4355 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
4356 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
4357 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
4358 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
4359 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
4361 /* ICL DSI 0 and 1 */
4362 #define _PIPEDSI0CONF		0x7b008
4363 #define _PIPEDSI1CONF		0x7b808
4366 #define _DVSACNTR		0x72180
4371 #define   DVS_FORMAT_YUV422		REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
4380 #define   DVS_YUV_ORDER_YUYV		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
4388 #define _DVSALINOFF		0x72184
4389 #define _DVSASTRIDE		0x72188
4390 #define _DVSAPOS		0x7218c
4393 #define   DVS_POS_X_MASK		REG_GENMASK(15, 0)
4395 #define _DVSASIZE		0x72190
4398 #define   DVS_WIDTH_MASK		REG_GENMASK(15, 0)
4400 #define _DVSAKEYVAL		0x72194
4401 #define _DVSAKEYMSK		0x72198
4402 #define _DVSASURF		0x7219c
4404 #define _DVSAKEYMAXVAL		0x721a0
4405 #define _DVSATILEOFF		0x721a4
4408 #define   DVS_OFFSET_X_MASK		REG_GENMASK(15, 0)
4410 #define _DVSASURFLIVE		0x721ac
4411 #define _DVSAGAMC_G4X		0x721e0 /* g4x */
4412 #define _DVSASCALE		0x72204
4415 #define   DVS_FILTER_MEDIUM		REG_FIELD_PREP(DVS_FILTER_MASK, 0)
4422 #define   DVS_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
4424 #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
4425 #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
4427 #define _DVSBCNTR		0x73180
4428 #define _DVSBLINOFF		0x73184
4429 #define _DVSBSTRIDE		0x73188
4430 #define _DVSBPOS		0x7318c
4431 #define _DVSBSIZE		0x73190
4432 #define _DVSBKEYVAL		0x73194
4433 #define _DVSBKEYMSK		0x73198
4434 #define _DVSBSURF		0x7319c
4435 #define _DVSBKEYMAXVAL		0x731a0
4436 #define _DVSBTILEOFF		0x731a4
4437 #define _DVSBSURFLIVE		0x731ac
4438 #define _DVSBGAMC_G4X		0x731e0 /* g4x */
4439 #define _DVSBSCALE		0x73204
4440 #define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
4441 #define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
4459 #define _SPRA_CTL		0x70280
4464 #define   SPRITE_FORMAT_YUV422			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
4474 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	REG_BIT(18) /* 0 is BT601 */
4476 #define   SPRITE_YUV_ORDER_YUYV			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
4485 #define _SPRA_LINOFF		0x70284
4486 #define _SPRA_STRIDE		0x70288
4487 #define _SPRA_POS		0x7028c
4490 #define   SPRITE_POS_X_MASK	REG_GENMASK(15, 0)
4492 #define _SPRA_SIZE		0x70290
4495 #define   SPRITE_WIDTH_MASK	REG_GENMASK(15, 0)
4497 #define _SPRA_KEYVAL		0x70294
4498 #define _SPRA_KEYMSK		0x70298
4499 #define _SPRA_SURF		0x7029c
4501 #define _SPRA_KEYMAX		0x702a0
4502 #define _SPRA_TILEOFF		0x702a4
4505 #define   SPRITE_OFFSET_X_MASK	REG_GENMASK(15, 0)
4507 #define _SPRA_OFFSET		0x702a4
4508 #define _SPRA_SURFLIVE		0x702ac
4509 #define _SPRA_SCALE		0x70304
4512 #define   SPRITE_FILTER_MEDIUM			REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
4519 #define   SPRITE_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
4521 #define _SPRA_GAMC		0x70400
4522 #define _SPRA_GAMC16		0x70440
4523 #define _SPRA_GAMC17		0x7044c
4525 #define _SPRB_CTL		0x71280
4526 #define _SPRB_LINOFF		0x71284
4527 #define _SPRB_STRIDE		0x71288
4528 #define _SPRB_POS		0x7128c
4529 #define _SPRB_SIZE		0x71290
4530 #define _SPRB_KEYVAL		0x71294
4531 #define _SPRB_KEYMSK		0x71298
4532 #define _SPRB_SURF		0x7129c
4533 #define _SPRB_KEYMAX		0x712a0
4534 #define _SPRB_TILEOFF		0x712a4
4535 #define _SPRB_OFFSET		0x712a4
4536 #define _SPRB_SURFLIVE		0x712ac
4537 #define _SPRB_SCALE		0x71304
4538 #define _SPRB_GAMC		0x71400
4539 #define _SPRB_GAMC16		0x71440
4540 #define _SPRB_GAMC17		0x7144c
4559 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
4563 #define   SP_FORMAT_YUV422		REG_FIELD_PREP(SP_FORMAT_MASK, 0)
4578 #define   SP_YUV_ORDER_YUYV		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
4585 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
4586 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
4587 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
4590 #define   SP_POS_X_MASK			REG_GENMASK(15, 0)
4592 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
4595 #define   SP_WIDTH_MASK			REG_GENMASK(15, 0)
4597 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
4598 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
4599 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
4601 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
4602 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
4605 #define   SP_OFFSET_X_MASK		REG_GENMASK(15, 0)
4607 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
4609 #define   SP_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
4611 #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
4614 #define   SP_BRIGHTNESS_MASK		REG_GENMASK(7, 0)
4616 #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
4619 #define   SP_SH_COS_MASK		REG_GENMASK(9, 0)
4621 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
4623 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
4624 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
4625 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
4626 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
4627 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
4628 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
4629 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
4630 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
4631 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
4632 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
4633 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
4634 #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
4635 #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
4636 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
4666 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
4668 #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
4669 #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
4670 #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
4672 #define  SPCSC_OOFF(x)		REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
4673 #define  SPCSC_IOFF_MASK	REG_GENMASK(10, 0)
4674 #define  SPCSC_IOFF(x)		REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
4676 #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
4677 #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
4678 #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
4679 #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
4680 #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
4682 #define  SPCSC_C1(x)		REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
4683 #define  SPCSC_C0_MASK		REG_GENMASK(14, 0)
4684 #define  SPCSC_C0(x)		REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
4686 #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
4687 #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
4688 #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
4690 #define  SPCSC_IMAX(x)		REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
4691 #define  SPCSC_IMIN_MASK	REG_GENMASK(10, 0)
4692 #define  SPCSC_IMIN(x)		REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
4694 #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
4695 #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
4696 #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
4699 #define  SPCSC_OMIN_MASK	REG_GENMASK(9, 0)
4704 #define _PLANE_CTL_1_A				0x70180
4705 #define _PLANE_CTL_2_A				0x70280
4706 #define _PLANE_CTL_3_A				0x70380
4715  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
4719 #define   PLANE_CTL_FORMAT_YUV422		REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
4744 #define   PLANE_CTL_YUV422_ORDER_YUYV		REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
4753 #define   PLANE_CTL_TILED_LINEAR		REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
4762 #define   PLANE_CTL_ALPHA_DISABLE		REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
4765 #define   PLANE_CTL_ROTATE_MASK			REG_GENMASK(1, 0)
4766 #define   PLANE_CTL_ROTATE_0			REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
4770 #define _PLANE_STRIDE_1_A			0x70188
4771 #define _PLANE_STRIDE_2_A			0x70288
4772 #define _PLANE_STRIDE_3_A			0x70388
4773 #define   PLANE_STRIDE__MASK			REG_GENMASK(11, 0)
4775 #define _PLANE_POS_1_A				0x7018c
4776 #define _PLANE_POS_2_A				0x7028c
4777 #define _PLANE_POS_3_A				0x7038c
4780 #define   PLANE_POS_X_MASK			REG_GENMASK(15, 0)
4782 #define _PLANE_SIZE_1_A				0x70190
4783 #define _PLANE_SIZE_2_A				0x70290
4784 #define _PLANE_SIZE_3_A				0x70390
4787 #define   PLANE_WIDTH_MASK			REG_GENMASK(15, 0)
4789 #define _PLANE_SURF_1_A				0x7019c
4790 #define _PLANE_SURF_2_A				0x7029c
4791 #define _PLANE_SURF_3_A				0x7039c
4794 #define _PLANE_OFFSET_1_A			0x701a4
4795 #define _PLANE_OFFSET_2_A			0x702a4
4796 #define _PLANE_OFFSET_3_A			0x703a4
4799 #define   PLANE_OFFSET_X_MASK			REG_GENMASK(15, 0)
4801 #define _PLANE_KEYVAL_1_A			0x70194
4802 #define _PLANE_KEYVAL_2_A			0x70294
4803 #define _PLANE_KEYMSK_1_A			0x70198
4804 #define _PLANE_KEYMSK_2_A			0x70298
4806 #define _PLANE_KEYMAX_1_A			0x701a0
4807 #define _PLANE_KEYMAX_2_A			0x702a0
4809 #define _PLANE_CC_VAL_1_A			0x701b4
4810 #define _PLANE_CC_VAL_2_A			0x702b4
4811 #define _PLANE_AUX_DIST_1_A			0x701c0
4813 #define   PLANE_AUX_STRIDE_MASK			REG_GENMASK(11, 0)
4815 #define _PLANE_AUX_DIST_2_A			0x702c0
4816 #define _PLANE_AUX_OFFSET_1_A			0x701c4
4817 #define _PLANE_AUX_OFFSET_2_A			0x702c4
4818 #define _PLANE_CUS_CTL_1_A			0x701c8
4819 #define _PLANE_CUS_CTL_2_A			0x702c8
4822 #define   PLANE_CUS_Y_PLANE_4_RKL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
4824 #define   PLANE_CUS_Y_PLANE_6_ICL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
4828 #define   PLANE_CUS_HPHASE_0			REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
4833 #define   PLANE_CUS_VPHASE_0			REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
4836 #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
4837 #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
4838 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
4845 #define   PLANE_COLOR_CSC_MODE_BYPASS			REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
4852 #define   PLANE_COLOR_ALPHA_DISABLE			REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
4855 #define _PLANE_BUF_CFG_1_A			0x7027c
4856 #define _PLANE_BUF_CFG_2_A			0x7037c
4857 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
4858 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
4860 #define _PLANE_CC_VAL_1_B		0x711b4
4861 #define _PLANE_CC_VAL_2_B		0x712b4
4868 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
4869 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
4871 #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
4872 #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
4885 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
4886 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
4888 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
4889 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
4901 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
4902 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
4904 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
4905 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
4917 #define _PLANE_CTL_1_B				0x71180
4918 #define _PLANE_CTL_2_B				0x71280
4919 #define _PLANE_CTL_3_B				0x71380
4926 #define _PLANE_STRIDE_1_B			0x71188
4927 #define _PLANE_STRIDE_2_B			0x71288
4928 #define _PLANE_STRIDE_3_B			0x71388
4938 #define _PLANE_POS_1_B				0x7118c
4939 #define _PLANE_POS_2_B				0x7128c
4940 #define _PLANE_POS_3_B				0x7138c
4947 #define _PLANE_SIZE_1_B				0x71190
4948 #define _PLANE_SIZE_2_B				0x71290
4949 #define _PLANE_SIZE_3_B				0x71390
4956 #define _PLANE_SURF_1_B				0x7119c
4957 #define _PLANE_SURF_2_B				0x7129c
4958 #define _PLANE_SURF_3_B				0x7139c
4965 #define _PLANE_OFFSET_1_B			0x711a4
4966 #define _PLANE_OFFSET_2_B			0x712a4
4972 #define _PLANE_KEYVAL_1_B			0x71194
4973 #define _PLANE_KEYVAL_2_B			0x71294
4979 #define _PLANE_KEYMSK_1_B			0x71198
4980 #define _PLANE_KEYMSK_2_B			0x71298
4986 #define _PLANE_KEYMAX_1_B			0x711a0
4987 #define _PLANE_KEYMAX_2_B			0x712a0
4993 #define _PLANE_BUF_CFG_1_B			0x7127c
4994 #define _PLANE_BUF_CFG_2_B			0x7137c
4998 #define   PLANE_BUF_START_MASK		REG_GENMASK(11, 0)
5007 #define _PLANE_NV12_BUF_CFG_1_B		0x71278
5008 #define _PLANE_NV12_BUF_CFG_2_B		0x71378
5016 #define _PLANE_AUX_DIST_1_B		0x711c0
5017 #define _PLANE_AUX_DIST_2_B		0x712c0
5025 #define _PLANE_AUX_OFFSET_1_B		0x711c4
5026 #define _PLANE_AUX_OFFSET_2_B		0x712c4
5034 #define _PLANE_CUS_CTL_1_B		0x711c8
5035 #define _PLANE_CUS_CTL_2_B		0x712c8
5043 #define _PLANE_COLOR_CTL_1_B			0x711CC
5044 #define _PLANE_COLOR_CTL_2_B			0x712CC
5045 #define _PLANE_COLOR_CTL_3_B			0x713CC
5053 #define _SEL_FETCH_PLANE_BASE_1_A		0x70890
5054 #define _SEL_FETCH_PLANE_BASE_2_A		0x708B0
5055 #define _SEL_FETCH_PLANE_BASE_3_A		0x708D0
5056 #define _SEL_FETCH_PLANE_BASE_4_A		0x708F0
5057 #define _SEL_FETCH_PLANE_BASE_5_A		0x70920
5058 #define _SEL_FETCH_PLANE_BASE_6_A		0x70940
5059 #define _SEL_FETCH_PLANE_BASE_7_A		0x70960
5060 #define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880
5061 #define _SEL_FETCH_PLANE_BASE_1_B		0x71890
5077 #define _SEL_FETCH_PLANE_CTL_1_A		0x70890
5083 #define _SEL_FETCH_PLANE_POS_1_A		0x70894
5088 #define _SEL_FETCH_PLANE_SIZE_1_A		0x70898
5093 #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089C
5099 #define _CUR_BUF_CFG_A				0x7017c
5100 #define _CUR_BUF_CFG_B				0x7117c
5104 #define VGACNTRL		_MMIO(0x71400)
5109 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
5113 #define CPU_VGACNTRL	_MMIO(0x41000)
5115 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
5117 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
5122 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
5123 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
5124 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
5125 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
5128 #define RR_HW_CTL       _MMIO(0x45300)
5129 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
5130 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
5132 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
5133 #define  FDI_PLL_FB_CLOCK_MASK  0xff
5134 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
5135 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
5136 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
5137 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
5138 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
5140 #define PCH_3DCGDIS0		_MMIO(0x46020)
5144 #define PCH_3DCGDIS1		_MMIO(0x46024)
5147 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
5149 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
5150 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
5153 #define _PIPEA_DATA_M1		0x60030
5154 #define _PIPEA_DATA_N1		0x60034
5155 #define _PIPEA_DATA_M2		0x60038
5156 #define _PIPEA_DATA_N2		0x6003c
5157 #define _PIPEA_LINK_M1		0x60040
5158 #define _PIPEA_LINK_N1		0x60044
5159 #define _PIPEA_LINK_M2		0x60048
5160 #define _PIPEA_LINK_N2		0x6004c
5162 /* PIPEB timing regs are same start from 0x61000 */
5164 #define _PIPEB_DATA_M1		0x61030
5165 #define _PIPEB_DATA_N1		0x61034
5166 #define _PIPEB_DATA_M2		0x61038
5167 #define _PIPEB_DATA_N2		0x6103c
5168 #define _PIPEB_LINK_M1		0x61040
5169 #define _PIPEB_LINK_N1		0x61044
5170 #define _PIPEB_LINK_M2		0x61048
5171 #define _PIPEB_LINK_N2		0x6104c
5183 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5184 #define _PFA_CTL_1               0x68080
5185 #define _PFB_CTL_1               0x68880
5190 #define  PF_FILTER_PROGRAMMED	(0 << 23)
5194 #define _PFA_WIN_SZ		0x68074
5195 #define _PFB_WIN_SZ		0x68874
5196 #define _PFA_WIN_POS		0x68070
5197 #define _PFB_WIN_POS		0x68870
5198 #define _PFA_VSCALE		0x68084
5199 #define _PFB_VSCALE		0x68884
5200 #define _PFA_HSCALE		0x68090
5201 #define _PFB_HSCALE		0x68890
5209 #define _PSA_CTL		0x68180
5210 #define _PSB_CTL		0x68980
5212 #define _PSA_WIN_SZ		0x68174
5213 #define _PSB_WIN_SZ		0x68974
5214 #define _PSA_WIN_POS		0x68170
5215 #define _PSB_WIN_POS		0x68970
5224 #define _PS_1A_CTRL      0x68180
5225 #define _PS_2A_CTRL      0x68280
5226 #define _PS_1B_CTRL      0x68980
5227 #define _PS_2B_CTRL      0x68A80
5228 #define _PS_1C_CTRL      0x69180
5231 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
5235 #define PS_SCALER_MODE_NORMAL (0 << 29)
5239 #define PS_FILTER_MEDIUM       (0 << 23)
5244 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5250 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5260 #define _PS_PWR_GATE_1A     0x68160
5261 #define _PS_PWR_GATE_2A     0x68260
5262 #define _PS_PWR_GATE_1B     0x68960
5263 #define _PS_PWR_GATE_2B     0x68A60
5264 #define _PS_PWR_GATE_1C     0x69160
5266 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
5270 #define PS_PWR_GATE_SLPEN_8             0
5275 #define _PS_WIN_POS_1A      0x68170
5276 #define _PS_WIN_POS_2A      0x68270
5277 #define _PS_WIN_POS_1B      0x68970
5278 #define _PS_WIN_POS_2B      0x68A70
5279 #define _PS_WIN_POS_1C      0x69170
5281 #define _PS_WIN_SZ_1A       0x68174
5282 #define _PS_WIN_SZ_2A       0x68274
5283 #define _PS_WIN_SZ_1B       0x68974
5284 #define _PS_WIN_SZ_2B       0x68A74
5285 #define _PS_WIN_SZ_1C       0x69174
5287 #define _PS_VSCALE_1A       0x68184
5288 #define _PS_VSCALE_2A       0x68284
5289 #define _PS_VSCALE_1B       0x68984
5290 #define _PS_VSCALE_2B       0x68A84
5291 #define _PS_VSCALE_1C       0x69184
5293 #define _PS_HSCALE_1A       0x68190
5294 #define _PS_HSCALE_2A       0x68290
5295 #define _PS_HSCALE_1B       0x68990
5296 #define _PS_HSCALE_2B       0x68A90
5297 #define _PS_HSCALE_1C       0x69190
5299 #define _PS_VPHASE_1A       0x68188
5300 #define _PS_VPHASE_2A       0x68288
5301 #define _PS_VPHASE_1B       0x68988
5302 #define _PS_VPHASE_2B       0x68A88
5303 #define _PS_VPHASE_1C       0x69188
5305 #define  PS_UV_RGB_PHASE(x)	((x) << 0)
5306 #define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
5307 #define   PS_PHASE_TRIP	(1 << 0)
5309 #define _PS_HPHASE_1A       0x68194
5310 #define _PS_HPHASE_2A       0x68294
5311 #define _PS_HPHASE_1B       0x68994
5312 #define _PS_HPHASE_2B       0x68A94
5313 #define _PS_HPHASE_1C       0x69194
5315 #define _PS_ECC_STAT_1A     0x681D0
5316 #define _PS_ECC_STAT_2A     0x682D0
5317 #define _PS_ECC_STAT_1B     0x689D0
5318 #define _PS_ECC_STAT_2B     0x68AD0
5319 #define _PS_ECC_STAT_1C     0x691D0
5321 #define _PS_COEF_SET0_INDEX_1A	   0x68198
5322 #define _PS_COEF_SET0_INDEX_2A	   0x68298
5323 #define _PS_COEF_SET0_INDEX_1B	   0x68998
5324 #define _PS_COEF_SET0_INDEX_2B	   0x68A98
5327 #define _PS_COEF_SET0_DATA_1A	   0x6819C
5328 #define _PS_COEF_SET0_DATA_2A	   0x6829C
5329 #define _PS_COEF_SET0_DATA_1B	   0x6899C
5330 #define _PS_COEF_SET0_DATA_2B	   0x68A9C
5368 #define _LGC_PALETTE_A           0x4a000
5369 #define _LGC_PALETTE_B           0x4a800
5372 #define LGC_PALETTE_BLUE_MASK    REG_GENMASK(7, 0)
5376 #define _PREC_PALETTE_A           0x4b000
5377 #define _PREC_PALETTE_B           0x4c000
5380 #define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
5383 #define  _PREC_PIPEAGCMAX              0x4d000
5384 #define  _PREC_PIPEBGCMAX              0x4d010
5387 #define _GAMMA_MODE_A		0x4a480
5388 #define _GAMMA_MODE_B		0x4ac80
5392 #define  GAMMA_MODE_MODE_MASK	(3 << 0)
5393 #define  GAMMA_MODE_MODE_8BIT	(0 << 0)
5394 #define  GAMMA_MODE_MODE_10BIT	(1 << 0)
5395 #define  GAMMA_MODE_MODE_12BIT	(2 << 0)
5396 #define  GAMMA_MODE_MODE_SPLIT	(3 << 0) /* ivb-bdw */
5397 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
5400 #define RM_TIMEOUT		_MMIO(0x42060)
5401 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
5433 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
5452 #define DE_PIPEA_VBLANK_IVB		(1 << 0)
5455 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
5458 #define DEISR   _MMIO(0x44000)
5459 #define DEIMR   _MMIO(0x44004)
5460 #define DEIIR   _MMIO(0x44008)
5461 #define DEIER   _MMIO(0x4400c)
5463 #define GTISR   _MMIO(0x44010)
5464 #define GTIMR   _MMIO(0x44014)
5465 #define GTIIR   _MMIO(0x44018)
5466 #define GTIER   _MMIO(0x4401c)
5468 #define GEN8_MASTER_IRQ			_MMIO(0x44200)
5484 #define  GEN8_GT_RCS_IRQ		(1 << 0)
5486 #define XELPD_DISPLAY_ERR_FATAL_MASK	_MMIO(0x4421c)
5488 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
5489 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
5490 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
5491 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
5493 #define GEN8_RCS_IRQ_SHIFT 0
5495 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
5497 #define GEN8_VECS_IRQ_SHIFT 0
5500 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
5501 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
5502 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
5503 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
5516 #define  GEN8_PIPE_VBLANK		(1 << 0)
5552 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
5553 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
5554 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
5555 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
5571 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
5582 #define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
5584 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
5585 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
5586 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
5587 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
5591 #define GEN8_PCU_ISR _MMIO(0x444e0)
5592 #define GEN8_PCU_IMR _MMIO(0x444e4)
5593 #define GEN8_PCU_IIR _MMIO(0x444e8)
5594 #define GEN8_PCU_IER _MMIO(0x444ec)
5596 #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
5597 #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
5598 #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
5599 #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
5602 #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
5609 #define  GEN11_GT_DW0_IRQ		(1 << 0)
5611 #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
5615 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
5626 #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
5627 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
5628 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
5629 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
5645 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
5646 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
5650 #define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
5652 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
5657 #define FUSE_STRAP			_MMIO(0x42014)
5668 #define FUSE_STRAP3			_MMIO(0x42020)
5671 #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
5678 #define IVB_CHICKEN3	_MMIO(0x4200c)
5682 #define CHICKEN_PAR1_1			_MMIO(0x42080)
5692 #define CHICKEN_PAR2_1		_MMIO(0x42090)
5695 #define CHICKEN_MISC_2		_MMIO(0x42084)
5702 #define CHICKEN_MISC_4		_MMIO(0x4208c)
5704 #define   CHICKEN_FBC_STRIDE_MASK	REG_GENMASK(12, 0)
5707 #define _CHICKEN_PIPESL_1_A	0x420b0
5708 #define _CHICKEN_PIPESL_1_B	0x420b4
5710 #define  HSW_PRI_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
5715 #define  HSW_SPR_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
5720 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
5721 #define  SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
5722 #define  SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
5728 #define _CHICKEN_TRANS_A	0x420c0
5729 #define _CHICKEN_TRANS_B	0x420c4
5730 #define _CHICKEN_TRANS_C	0x420c8
5731 #define _CHICKEN_TRANS_EDP	0x420cc
5732 #define _CHICKEN_TRANS_D	0x420d8
5740 #define _MTL_CHICKEN_TRANS_A	0x604e0
5741 #define _MTL_CHICKEN_TRANS_B	0x614e0
5758 #define DISP_ARB_CTL	_MMIO(0x45000)
5762 #define DISP_ARB_CTL2	_MMIO(0x45004)
5768  * with display 13, the bspec switches to a 0-based numbering scheme
5770  * We'll just use the 0-based numbering here for all platforms since it's the
5774 #define _DBUF_CTL_S0				0x45008
5775 #define _DBUF_CTL_S1				0x44FE8
5776 #define _DBUF_CTL_S2				0x44300
5777 #define _DBUF_CTL_S3				0x44304
5790 #define GEN7_MSG_CTL	_MMIO(0x45010)
5792 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
5794 #define _BW_BUDDY0_CTL			0x45130
5795 #define _BW_BUDDY1_CTL			0x45140
5803 #define _BW_BUDDY0_PAGE_MASK		0x45134
5804 #define _BW_BUDDY1_PAGE_MASK		0x45144
5809 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
5813 #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
5823 #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
5829 #define SKL_DFSM			_MMIO(0x51000)
5833 #define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
5844 #define SKL_DSSM				_MMIO(0x51004)
5846 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
5851 #define _PIPEA_CHICKEN				0x70038
5852 #define _PIPEB_CHICKEN				0x71038
5853 #define _PIPEC_CHICKEN				0x72038
5864 #define PCH_DISPLAY_BASE	0xc0000u
5904 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
5905 #define SDE_TRANS_MASK		(0x3f)
5944 #define SDE_FDI_RXA_CPT		(1 << 0)
5971 #define SDEISR  _MMIO(0xc4000)
5972 #define SDEIMR  _MMIO(0xc4004)
5973 #define SDEIIR  _MMIO(0xc4008)
5974 #define SDEIER  _MMIO(0xc400c)
5976 #define SERR_INT			_MMIO(0xc4040)
5981 #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
5985 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
5989 #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
5995 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
6000 #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
6006 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
6011 #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
6016 #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
6017 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
6018 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
6019 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
6024 #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
6026 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
6027 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
6028 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
6029 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
6036 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
6037 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
6038 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
6039 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
6040 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
6041 #define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin)		(0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
6042 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
6044 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
6049 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
6050 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
6052 #define _PCH_DPLL_A              0xc6014
6053 #define _PCH_DPLL_B              0xc6018
6054 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6056 #define _PCH_FPA0                0xc6040
6057 #define  FP_CB_TUNE		(0x3 << 22)
6058 #define _PCH_FPA1                0xc6044
6059 #define _PCH_FPB0                0xc6048
6060 #define _PCH_FPB1                0xc604c
6061 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
6062 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
6064 #define PCH_DPLL_TEST           _MMIO(0xc606c)
6066 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
6067 #define  DREF_CONTROL_MASK      0x7fc3
6068 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
6072 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
6075 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
6079 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
6082 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
6084 #define  DREF_SSC1_DISABLE                      (0 << 1)
6086 #define  DREF_SSC4_DISABLE                      (0)
6089 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
6094 #define  RAWCLK_FREQ_MASK       0x3ff
6095 #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
6097 #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
6101 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
6103 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
6104 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
6106 #define PCH_DPLL_SEL		_MMIO(0xc7000)
6108 #define	 TRANS_DPLLA_SEL(pipe)		0
6113 #define _PCH_TRANS_HTOTAL_A		0xe0000
6115 #define  TRANS_HACTIVE_SHIFT		0
6116 #define _PCH_TRANS_HBLANK_A		0xe0004
6118 #define  TRANS_HBLANK_START_SHIFT	0
6119 #define _PCH_TRANS_HSYNC_A		0xe0008
6121 #define  TRANS_HSYNC_START_SHIFT	0
6122 #define _PCH_TRANS_VTOTAL_A		0xe000c
6124 #define  TRANS_VACTIVE_SHIFT		0
6125 #define _PCH_TRANS_VBLANK_A		0xe0010
6127 #define  TRANS_VBLANK_START_SHIFT	0
6128 #define _PCH_TRANS_VSYNC_A		0xe0014
6130 #define  TRANS_VSYNC_START_SHIFT	0
6131 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
6133 #define _PCH_TRANSA_DATA_M1	0xe0030
6134 #define _PCH_TRANSA_DATA_N1	0xe0034
6135 #define _PCH_TRANSA_DATA_M2	0xe0038
6136 #define _PCH_TRANSA_DATA_N2	0xe003c
6137 #define _PCH_TRANSA_LINK_M1	0xe0040
6138 #define _PCH_TRANSA_LINK_N1	0xe0044
6139 #define _PCH_TRANSA_LINK_M2	0xe0048
6140 #define _PCH_TRANSA_LINK_N2	0xe004c
6143 #define _VIDEO_DIP_CTL_A         0xe0200
6144 #define _VIDEO_DIP_DATA_A        0xe0208
6145 #define _VIDEO_DIP_GCP_A         0xe0210
6148 #define  GCP_AV_MUTE			(1 << 0)
6150 #define _VIDEO_DIP_CTL_B         0xe1200
6151 #define _VIDEO_DIP_DATA_B        0xe1208
6152 #define _VIDEO_DIP_GCP_B         0xe1210
6159 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
6160 #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
6161 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
6163 #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
6164 #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
6165 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
6167 #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
6168 #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
6169 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
6183 #define _HSW_VIDEO_DIP_CTL_A		0x60200
6184 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
6185 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
6186 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
6187 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
6188 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
6189 #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
6190 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
6191 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
6192 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
6193 #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
6194 #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
6195 #define _HSW_VIDEO_DIP_GCP_A		0x60210
6197 #define _HSW_VIDEO_DIP_CTL_B		0x61200
6198 #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
6199 #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
6200 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
6201 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
6202 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
6203 #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
6204 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
6205 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
6206 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
6207 #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
6208 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
6209 #define _HSW_VIDEO_DIP_GCP_B		0x61210
6217 #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
6218 #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
6219 #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
6220 #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
6233 #define _HSW_STEREO_3D_CTL_A		0x70020
6235 #define _HSW_STEREO_3D_CTL_B		0x71020
6239 #define _PCH_TRANS_HTOTAL_B          0xe1000
6240 #define _PCH_TRANS_HBLANK_B          0xe1004
6241 #define _PCH_TRANS_HSYNC_B           0xe1008
6242 #define _PCH_TRANS_VTOTAL_B          0xe100c
6243 #define _PCH_TRANS_VBLANK_B          0xe1010
6244 #define _PCH_TRANS_VSYNC_B           0xe1014
6245 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6255 #define _PCH_TRANSB_DATA_M1	0xe1030
6256 #define _PCH_TRANSB_DATA_N1	0xe1034
6257 #define _PCH_TRANSB_DATA_M2	0xe1038
6258 #define _PCH_TRANSB_DATA_N2	0xe103c
6259 #define _PCH_TRANSB_LINK_M1	0xe1040
6260 #define _PCH_TRANSB_LINK_N1	0xe1044
6261 #define _PCH_TRANSB_LINK_M2	0xe1048
6262 #define _PCH_TRANSB_LINK_N2	0xe104c
6273 #define _PCH_TRANSACONF              0xf0008
6274 #define _PCH_TRANSBCONF              0xf1008
6280 #define  TRANS_FRAME_START_DELAY(x)	REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
6282 #define  TRANS_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
6286 #define  TRANS_BPC_8			REG_FIELD_PREP(TRANS_BPC_MASK, 0)
6290 #define _TRANSA_CHICKEN1	 0xf0060
6291 #define _TRANSB_CHICKEN1	 0xf1060
6295 #define _TRANSA_CHICKEN2	 0xf0064
6296 #define _TRANSB_CHICKEN2	 0xf1064
6301 #define  TRANS_CHICKEN2_FRAME_START_DELAY(x)		((x) << 27) /* 0-3 */
6305 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
6315 #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
6318 #define  SPT_PWM_GRANULARITY		(1 << 0)
6319 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
6323 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
6325 #define _FDI_RXA_CHICKEN        0xc200c
6326 #define _FDI_RXB_CHICKEN        0xc2010
6328 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
6331 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
6341 #define _FDI_TXA_CTL            0x60100
6342 #define _FDI_TXB_CTL            0x61100
6344 #define  FDI_TX_DISABLE         (0 << 31)
6346 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
6350 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
6354 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
6358 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6361 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
6362 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
6363 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
6364 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
6366 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
6367 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
6368 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
6369 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
6370 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
6379 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
6387 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
6391 #define _FDI_RXA_CTL             0xf000c
6392 #define _FDI_RXB_CTL             0xf100c
6399 #define  FDI_8BPC                       (0 << 16)
6414 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
6420 #define _FDI_RXA_MISC			0xf0010
6421 #define _FDI_RXB_MISC			0xf1010
6428 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
6431 #define _FDI_RXA_TUSIZE1        0xf0030
6432 #define _FDI_RXA_TUSIZE2        0xf0038
6433 #define _FDI_RXB_TUSIZE1        0xf1030
6434 #define _FDI_RXB_TUSIZE2        0xf1038
6449 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
6451 #define _FDI_RXA_IIR            0xf0014
6452 #define _FDI_RXA_IMR            0xf0018
6453 #define _FDI_RXB_IIR            0xf1014
6454 #define _FDI_RXB_IMR            0xf1018
6458 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
6459 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
6461 #define PCH_LVDS	_MMIO(0xe1180)
6464 #define _PCH_DP_B		0xe4100
6466 #define _PCH_DPB_AUX_CH_CTL	0xe4110
6467 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
6468 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
6469 #define _PCH_DPB_AUX_CH_DATA3	0xe411c
6470 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
6471 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
6473 #define _PCH_DP_C		0xe4200
6475 #define _PCH_DPC_AUX_CH_CTL	0xe4210
6476 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
6477 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
6478 #define _PCH_DPC_AUX_CH_DATA3	0xe421c
6479 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
6480 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
6482 #define _PCH_DP_D		0xe4300
6484 #define _PCH_DPD_AUX_CH_CTL	0xe4310
6485 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
6486 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
6487 #define _PCH_DPD_AUX_CH_DATA3	0xe431c
6488 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
6489 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
6495 #define _TRANS_DP_CTL_A		0xe0300
6496 #define _TRANS_DP_CTL_B		0xe1300
6497 #define _TRANS_DP_CTL_C		0xe2300
6506 #define  TRANS_DP_BPC_8			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
6513 #define _TRANS_DP2_CTL_A			0x600a0
6514 #define _TRANS_DP2_CTL_B			0x610a0
6515 #define _TRANS_DP2_CTL_C			0x620a0
6516 #define _TRANS_DP2_CTL_D			0x630a0
6522 #define _TRANS_DP2_VFREQHIGH_A			0x600a4
6523 #define _TRANS_DP2_VFREQHIGH_B			0x610a4
6524 #define _TRANS_DP2_VFREQHIGH_C			0x620a4
6525 #define _TRANS_DP2_VFREQHIGH_D			0x630a4
6530 #define _TRANS_DP2_VFREQLOW_A			0x600a8
6531 #define _TRANS_DP2_VFREQLOW_B			0x610a8
6532 #define _TRANS_DP2_VFREQLOW_C			0x620a8
6533 #define _TRANS_DP2_VFREQLOW_D			0x630a8
6538 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
6539 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
6540 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
6541 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
6543 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
6544 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
6545 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
6546 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
6547 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
6548 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
6551 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
6552 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
6553 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
6554 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
6555 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
6556 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
6557 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
6560 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
6561 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
6562 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
6563 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
6564 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
6566 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
6568 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
6570 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
6571 #define    EDRAM_ENABLED			0x1
6572 #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
6573 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
6574 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
6576 #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
6580 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
6584 #define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
6585 #define   GEN6_PCODE_ERROR_MASK			0xFF
6586 #define     GEN6_PCODE_SUCCESS			0x0
6587 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
6588 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
6589 #define     GEN6_PCODE_TIMEOUT			0x3
6590 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
6591 #define     GEN7_PCODE_TIMEOUT			0x2
6592 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
6593 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
6594 #define     GEN11_PCODE_LOCKED			0x6
6595 #define     GEN11_PCODE_REJECTED		0x11
6596 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
6597 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
6598 #define   GEN6_PCODE_READ_RC6VIDS		0x5
6601 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
6602 #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
6606 #define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
6607 #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
6608 #define   SKL_PCODE_CDCLK_CONTROL		0x7
6609 #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
6610 #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
6611 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
6612 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
6613 #define   GEN6_READ_OC_PARAMS			0xc
6614 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
6615 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
6616 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
6617 #define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
6618 #define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
6619 #define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
6620 #define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
6624 #define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
6627 #define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
6631 #define   GEN6_PCODE_READ_D_COMP		0x10
6632 #define   GEN6_PCODE_WRITE_D_COMP		0x11
6633 #define   ICL_PCODE_EXIT_TCCOLD			0x12
6634 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
6635 #define   DISPLAY_IPS_CONTROL			0x19
6636 #define   TGL_PCODE_TCCOLD			0x26
6637 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
6638 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
6639 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
6642 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
6643 #define   GEN9_PCODE_SAGV_CONTROL		0x21
6644 #define     GEN9_SAGV_DISABLE			0x0
6645 #define     GEN9_SAGV_IS_DISABLED		0x1
6646 #define     GEN9_SAGV_ENABLE			0x3
6647 #define   DG1_PCODE_STATUS			0x7E
6648 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
6649 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
6650 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
6651 #define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
6653 #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
6654 #define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
6657 #define     PCODE_MBOX_DOMAIN_NONE		0x0
6658 #define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
6659 #define GEN6_PCODE_DATA				_MMIO(0x138128)
6662 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
6665 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
6666 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
6682 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
6699 #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
6700 #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
6701 #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
6702 #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
6703 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
6704 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
6720 #define   SKL_PW_CTL_IDX_MISC_IO		0
6727 #define   ICL_PW_CTL_IDX_PW_1			0
6735 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
6736 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
6737 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
6761 #define   ICL_PW_CTL_IDX_AUX_A			0
6763 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
6764 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
6765 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
6779 #define   ICL_PW_CTL_IDX_DDI_A			0
6782 #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
6786 #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
6797 #define SKL_FUSE_STATUS				_MMIO(0x42000)
6814 #define _ICL_AUX_ANAOVRD1_A		0x162398
6815 #define _ICL_AUX_ANAOVRD1_B		0x6C398
6820 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
6823 #define _TRANS_DDI_FUNC_CTL_A		0x60400
6824 #define _TRANS_DDI_FUNC_CTL_B		0x61400
6825 #define _TRANS_DDI_FUNC_CTL_C		0x62400
6826 #define _TRANS_DDI_FUNC_CTL_D		0x63400
6827 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
6828 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
6829 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
6837 #define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)
6841 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
6847 #define  TRANS_DDI_BPC_8		(0 << 20)
6857 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
6872 #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
6877 #define _TRANS_DDI_FUNC_CTL2_A		0x60404
6878 #define _TRANS_DDI_FUNC_CTL2_B		0x61404
6879 #define _TRANS_DDI_FUNC_CTL2_C		0x62404
6880 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
6881 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
6882 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
6885 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
6888 #define TRANS_CMTG_CHICKEN		_MMIO(0x6fa90)
6892 #define _DP_TP_CTL_A			0x64040
6893 #define _DP_TP_CTL_B			0x64140
6894 #define _TGL_DP_TP_CTL_A		0x60540
6899 #define  DP_TP_CTL_MODE_SST			(0 << 27)
6905 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
6914 #define _DP_TP_STATUS_A			0x64044
6915 #define _DP_TP_STATUS_B			0x64144
6916 #define _TGL_DP_TP_STATUS_A		0x60544
6926 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
6929 #define _DDI_BUF_CTL_A				0x64000
6930 #define _DDI_BUF_CTL_B				0x64100
6934 #define  DDI_BUF_EMP_MASK			(0xf << 24)
6943 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
6946 #define _DDI_BUF_TRANS_A		0x64E00
6947 #define _DDI_BUF_TRANS_B		0x64E60
6953 #define _DDI_DP_COMP_CTL_A			0x605F0
6954 #define _DDI_DP_COMP_CTL_B			0x615F0
6957 #define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
6963 #define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
6966 #define _DDI_DP_COMP_PAT_A			0x605F4
6967 #define _DDI_DP_COMP_PAT_B			0x615F4
6973 #define SBI_ADDR			_MMIO(0xC6000)
6974 #define SBI_DATA			_MMIO(0xC6004)
6975 #define SBI_CTL_STAT			_MMIO(0xC6008)
6976 #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
6977 #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
6978 #define  SBI_CTL_OP_IORD		(0x2 << 8)
6979 #define  SBI_CTL_OP_IOWR		(0x3 << 8)
6980 #define  SBI_CTL_OP_CRRD		(0x6 << 8)
6981 #define  SBI_CTL_OP_CRWR		(0x7 << 8)
6982 #define  SBI_RESPONSE_FAIL		(0x1 << 1)
6983 #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
6984 #define  SBI_BUSY			(0x1 << 0)
6985 #define  SBI_READY			(0x0 << 0)
6988 #define  SBI_SSCDIVINTPHASE			0x0200
6989 #define  SBI_SSCDIVINTPHASE6			0x0600
6991 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
6994 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
6997 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
6998 #define  SBI_SSCDITHPHASE			0x0204
6999 #define  SBI_SSCCTL				0x020c
7000 #define  SBI_SSCCTL6				0x060C
7002 #define   SBI_SSCCTL_DISABLE			(1 << 0)
7003 #define  SBI_SSCAUXDIV6				0x0610
7007 #define  SBI_DBUFF0				0x2a00
7008 #define  SBI_GEN0				0x1f00
7009 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
7012 #define PIXCLK_GATE			_MMIO(0xC6020)
7013 #define  PIXCLK_GATE_UNGATE		(1 << 0)
7014 #define  PIXCLK_GATE_GATE		(0 << 0)
7017 #define SPLL_CTL			_MMIO(0x46020)
7019 #define  SPLL_REF_BCLK			(0 << 28)
7025 #define  SPLL_FREQ_810MHz		(0 << 26)
7031 #define _WRPLL_CTL1			0x46040
7032 #define _WRPLL_CTL2			0x46060
7035 #define  WRPLL_REF_BCLK			(0 << 28)
7042 #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
7043 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
7045 #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
7049 #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
7052 #define _PORT_CLK_SEL_A			0x46100
7053 #define _PORT_CLK_SEL_B			0x46104
7056 #define  PORT_CLK_SEL_LCPLL_2700	REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
7068 #define  DDI_CLK_SEL_NONE		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
7069 #define  DDI_CLK_SEL_MG			REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
7070 #define  DDI_CLK_SEL_TBT_162		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
7071 #define  DDI_CLK_SEL_TBT_270		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
7072 #define  DDI_CLK_SEL_TBT_540		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
7073 #define  DDI_CLK_SEL_TBT_810		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
7076 #define _TRANS_CLK_SEL_A		0x46140
7077 #define _TRANS_CLK_SEL_B		0x46144
7080 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
7082 #define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
7086 #define CDCLK_FREQ			_MMIO(0x46200)
7088 #define _TRANSA_MSA_MISC		0x60410
7089 #define _TRANSB_MSA_MISC		0x61410
7090 #define _TRANSC_MSA_MISC		0x62410
7091 #define _TRANS_EDP_MSA_MISC		0x6f410
7095 #define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
7096 #define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
7097 #define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
7098 #define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
7100 #define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
7104 #define LCPLL_CTL			_MMIO(0x130040)
7107 #define  LCPLL_REF_NON_SSC		(0 << 28)
7112 #define  LCPLL_CLK_FREQ_450		(0 << 26)
7128 #define CDCLK_CTL			_MMIO(0x46000)
7130 #define  CDCLK_FREQ_450_432		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
7135 #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
7142 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
7147 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
7150 #define CDCLK_SQUASH_CTL		_MMIO(0x46008)
7154 #define  CDCLK_SQUASH_WAVEFORM_MASK	REG_GENMASK(15, 0)
7158 #define LCPLL1_CTL		_MMIO(0x46010)
7159 #define LCPLL2_CTL		_MMIO(0x46014)
7163 #define DPLL_CTRL1		_MMIO(0x6C058)
7170 #define  DPLL_CTRL1_LINK_RATE_2700		0
7178 #define DPLL_CTRL2				_MMIO(0x6C05C)
7186 #define DPLL_STATUS	_MMIO(0x6C060)
7190 #define _DPLL1_CFGCR1	0x6C040
7191 #define _DPLL2_CFGCR1	0x6C048
7192 #define _DPLL3_CFGCR1	0x6C050
7194 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
7196 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
7198 #define _DPLL1_CFGCR2	0x6C044
7199 #define _DPLL2_CFGCR2	0x6C04C
7200 #define _DPLL3_CFGCR2	0x6C054
7201 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
7206 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
7212 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
7223 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
7232 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	_PICK(phy, 0, 2, 4, 27)
7244 #define _DG1_DPCLKA_CFGCR0				0x164280
7245 #define _DG1_DPCLKA1_CFGCR0				0x16C280
7254 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7257 #define _ADLS_DPCLKA_CFGCR0			0x164280
7258 #define _ADLS_DPCLKA_CFGCR1			0x1642BC
7266 #define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
7269 #define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
7278 #define DPLL0_ENABLE		0x46010
7279 #define DPLL1_ENABLE		0x46014
7280 #define _ADLS_DPLL2_ENABLE	0x46018
7281 #define _ADLS_DPLL3_ENABLE	0x46030
7289 #define _DG2_PLL3_ENABLE	0x4601C
7294 #define TBT_PLL_ENABLE		_MMIO(0x46020)
7296 #define _MG_PLL1_ENABLE		0x46030
7297 #define _MG_PLL2_ENABLE		0x46034
7298 #define _MG_PLL3_ENABLE		0x46038
7299 #define _MG_PLL4_ENABLE		0x4603C
7309 #define PORTTC1_PLL_ENABLE	0x46038
7310 #define PORTTC2_PLL_ENABLE	0x46040
7316 #define _ICL_DPLL0_CFGCR0		0x164000
7317 #define _ICL_DPLL1_CFGCR0		0x164080
7323 #define   DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
7324 #define   DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
7332 #define   DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
7335 #define   DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
7337 #define _ICL_DPLL0_CFGCR1		0x164004
7338 #define _ICL_DPLL1_CFGCR1		0x164084
7341 #define   DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
7352 #define   DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
7359 #define   DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
7360 #define   DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
7361 #define   TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
7363 #define _TGL_DPLL0_CFGCR0		0x164284
7364 #define _TGL_DPLL1_CFGCR0		0x16428C
7365 #define _TGL_TBTPLL_CFGCR0		0x16429C
7372 #define _TGL_DPLL0_DIV0					0x164B00
7373 #define _TGL_DPLL1_DIV0					0x164C00
7378 #define _TGL_DPLL0_CFGCR1		0x164288
7379 #define _TGL_DPLL1_CFGCR1		0x164290
7380 #define _TGL_TBTPLL_CFGCR1		0x1642A0
7387 #define _DG1_DPLL2_CFGCR0		0x16C284
7388 #define _DG1_DPLL3_CFGCR0		0x16C28C
7394 #define _DG1_DPLL2_CFGCR1               0x16C288
7395 #define _DG1_DPLL3_CFGCR1               0x16C290
7402 #define _ADLS_DPLL3_CFGCR0		0x1642C0
7403 #define _ADLS_DPLL4_CFGCR0		0x164294
7409 #define _ADLS_DPLL3_CFGCR1		0x1642C4
7410 #define _ADLS_DPLL4_CFGCR1		0x164298
7416 #define _DKL_PHY1_BASE			0x168000
7417 #define _DKL_PHY2_BASE			0x169000
7418 #define _DKL_PHY3_BASE			0x16A000
7419 #define _DKL_PHY4_BASE			0x16B000
7420 #define _DKL_PHY5_BASE			0x16C000
7421 #define _DKL_PHY6_BASE			0x16D000
7427 #define _DKL_PCS_DW5			0x14
7433 #define _DKL_PLL_DIV0			0x200
7437 #define   DKL_PLL_DIV0_INTEG_COEFF_MASK	(0x1F << 16)
7439 #define   DKL_PLL_DIV0_PROP_COEFF_MASK	(0xF << 12)
7442 #define   DKL_PLL_DIV0_FBPREDIV_MASK	(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
7443 #define   DKL_PLL_DIV0_FBDIV_INT(x)	((x) << 0)
7444 #define   DKL_PLL_DIV0_FBDIV_INT_MASK	(0xFF << 0)
7453 #define _DKL_PLL_DIV1				0x204
7455 #define   DKL_PLL_DIV1_IREF_TRIM_MASK		(0x1F << 16)
7456 #define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)	((x) << 0)
7457 #define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK	(0xFF << 0)
7462 #define _DKL_PLL_SSC				0x210
7464 #define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK	(0x7 << 29)
7466 #define   DKL_PLL_SSC_STEP_LEN_MASK		(0xFF << 16)
7468 #define   DKL_PLL_SSC_STEP_NUM_MASK		(0x7 << 11)
7474 #define _DKL_PLL_BIAS			0x214
7478 #define   DKL_PLL_BIAS_FBDIV_FRAC_MASK	(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
7483 #define _DKL_PLL_TDC_COLDST_BIAS		0x218
7485 #define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK	(0xFF << 8)
7486 #define   DKL_PLL_TDC_FEED_FWD_GAIN(x)		((x) << 0)
7487 #define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK	(0xFF << 0)
7493 #define _DKL_REFCLKIN_CTL		0x12C
7500 #define _DKL_CLKTOP2_HSCLKCTL		0xD4
7507 #define _DKL_CLKTOP2_CORECLKCTL1		0xD8
7514 #define _DKL_TX_DPCNTL0				0x2C0
7516 #define  DKL_TX_PRESHOOT_COEFF_MASK			(0x1f << 13)
7518 #define  DKL_TX_DE_EMPAHSIS_COEFF_MASK		(0x1f << 8)
7519 #define  DKL_TX_VSWING_CONTROL(x)			((x) << 0)
7520 #define  DKL_TX_VSWING_CONTROL_MASK			(0x7 << 0)
7526 #define _DKL_TX_DPCNTL1				0x2C4
7533 #define _DKL_TX_DPCNTL2					0x2C8
7544 #define _DKL_TX_FW_CALIB				0x2F8
7551 #define _DKL_TX_PMD_LANE_SUS				0xD00
7557 #define _DKL_TX_DW17					0xDC4
7563 #define _DKL_TX_DW18					0xDC8
7569 #define _DKL_DP_MODE					0xA0
7575 #define _DKL_CMN_UC_DW27			0x36C
7576 #define  DKL_CMN_UC_DW27_UC_HEALTH		(0x1 << 15)
7588 #define _HIP_INDEX_REG0			0x1010A0
7589 #define _HIP_INDEX_REG1			0x1010A4
7596 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
7598 #define   BXT_DE_PLL_RATIO_MASK		0xff
7600 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
7606 #define   ICL_CDCLK_PLL_RATIO_MASK	0xff
7609 #define DC_STATE_EN			_MMIO(0x45504)
7610 #define  DC_STATE_DISABLE		0
7613 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
7615 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
7616 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
7618 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
7619 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
7622 #define D_COMP_BDW			_MMIO(0x138144)
7625 #define _WM_LINETIME_A		0x45270
7626 #define _WM_LINETIME_B		0x45274
7628 #define  HSW_LINETIME_MASK	REG_GENMASK(8, 0)
7634 #define SFUSE_STRAP			_MMIO(0xc2014)
7642 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
7644 #define WM_MISC				_MMIO(0x45260)
7645 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
7647 #define WM_DBG				_MMIO(0x45280)
7648 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
7653 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
7654 #define _PIPE_A_CSC_COEFF_BY	0x49014
7655 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
7656 #define _PIPE_A_CSC_COEFF_BU	0x4901c
7657 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
7658 #define _PIPE_A_CSC_COEFF_BV	0x49024
7660 #define _PIPE_A_CSC_MODE	0x49028
7665 #define  CSC_MODE_YUV_TO_RGB		(1 << 0) /* ilk/snb */
7667 #define _PIPE_A_CSC_PREOFF_HI	0x49030
7668 #define _PIPE_A_CSC_PREOFF_ME	0x49034
7669 #define _PIPE_A_CSC_PREOFF_LO	0x49038
7670 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
7671 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
7672 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
7674 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
7675 #define _PIPE_B_CSC_COEFF_BY	0x49114
7676 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
7677 #define _PIPE_B_CSC_COEFF_BU	0x4911c
7678 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
7679 #define _PIPE_B_CSC_COEFF_BV	0x49124
7680 #define _PIPE_B_CSC_MODE	0x49128
7681 #define _PIPE_B_CSC_PREOFF_HI	0x49130
7682 #define _PIPE_B_CSC_PREOFF_ME	0x49134
7683 #define _PIPE_B_CSC_PREOFF_LO	0x49138
7684 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
7685 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
7686 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
7703 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
7704 #define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
7705 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
7706 #define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
7707 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
7708 #define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
7709 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
7710 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
7711 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
7712 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
7713 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
7714 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
7716 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
7717 #define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
7718 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
7719 #define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
7720 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
7721 #define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
7722 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
7723 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
7724 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
7725 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
7726 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
7727 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
7767 #define _PAL_PREC_INDEX_A	0x4A400
7768 #define _PAL_PREC_INDEX_B	0x4AC00
7769 #define _PAL_PREC_INDEX_C	0x4B400
7770 #define   PAL_PREC_10_12_BIT		(0 << 31)
7773 #define   PAL_PREC_INDEX_VALUE_MASK	(0x3ff << 0)
7774 #define   PAL_PREC_INDEX_VALUE(x)	((x) << 0)
7775 #define _PAL_PREC_DATA_A	0x4A404
7776 #define _PAL_PREC_DATA_B	0x4AC04
7777 #define _PAL_PREC_DATA_C	0x4B404
7778 #define _PAL_PREC_GC_MAX_A	0x4A410
7779 #define _PAL_PREC_GC_MAX_B	0x4AC10
7780 #define _PAL_PREC_GC_MAX_C	0x4B410
7783 #define   PREC_PAL_DATA_BLUE_MASK	REG_GENMASK(9, 0)
7784 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
7785 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
7786 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
7787 #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
7788 #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
7789 #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
7797 #define _PRE_CSC_GAMC_INDEX_A	0x4A484
7798 #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
7799 #define _PRE_CSC_GAMC_INDEX_C	0x4B484
7801 #define _PRE_CSC_GAMC_DATA_A	0x4A488
7802 #define _PRE_CSC_GAMC_DATA_B	0x4AC88
7803 #define _PRE_CSC_GAMC_DATA_C	0x4B488
7809 #define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
7810 #define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
7812 #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK	REG_GENMASK(4, 0)
7814 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
7815 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
7821 #define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
7833 #define _PLANE_CSC_RY_GY_1_A	0x70210
7834 #define _PLANE_CSC_RY_GY_2_A	0x70310
7836 #define _PLANE_CSC_RY_GY_1_B	0x71210
7837 #define _PLANE_CSC_RY_GY_2_B	0x71310
7847 #define _PLANE_CSC_PREOFF_HI_1_A		0x70228
7848 #define _PLANE_CSC_PREOFF_HI_2_A		0x70328
7850 #define _PLANE_CSC_PREOFF_HI_1_B		0x71228
7851 #define _PLANE_CSC_PREOFF_HI_2_B		0x71328
7861 #define _PLANE_CSC_POSTOFF_HI_1_A		0x70234
7862 #define _PLANE_CSC_POSTOFF_HI_2_A		0x70334
7864 #define _PLANE_CSC_POSTOFF_HI_1_B		0x71234
7865 #define _PLANE_CSC_POSTOFF_HI_2_B		0x71334
7876 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
7877 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
7878 #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
7879 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
7880 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
7881 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
7882 #define   CGM_PIPE_DEGAMMA_RED_MASK	REG_GENMASK(13, 0)
7884 #define   CGM_PIPE_DEGAMMA_BLUE_MASK	REG_GENMASK(13, 0)
7885 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
7886 #define   CGM_PIPE_GAMMA_RED_MASK	REG_GENMASK(9, 0)
7888 #define   CGM_PIPE_GAMMA_BLUE_MASK	REG_GENMASK(9, 0)
7889 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
7892 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
7894 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
7895 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
7896 #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
7897 #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
7898 #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
7899 #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
7900 #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
7901 #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
7913 #define GEN4_TIMESTAMP		_MMIO(0x2358)
7914 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
7915 #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
7917 #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
7918 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
7919 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
7921 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
7923 #define _PIPE_FRMTMSTMP_A		0x70048
7928 #define DSS_CTL1				_MMIO(0x67400)
7932 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
7933 #define  OVERLAP_PIXELS_MASK			(0xf << 16)
7935 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
7936 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
7937 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
7939 #define DSS_CTL2				_MMIO(0x67404)
7942 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
7943 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
7945 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
7946 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
7954 #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
7959 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
7960 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
7965 #define GEN12_GSMBASE			_MMIO(0x108100)
7966 #define GEN12_DSMBASE			_MMIO(0x1080C0)
7968 #define XEHP_CLOCK_GATE_DIS		_MMIO(0x101014)
7973 #define _ICL_PHY_MISC_A		0x64C00
7974 #define _ICL_PHY_MISC_B		0x64C04
7975 #define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
7984 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
7985 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
7986 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
7987 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
7988 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
7989 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
8004 #define  DSC_VER_MAJ			(0x1 << 0)
8006 #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
8007 #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
8008 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
8009 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
8010 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
8011 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
8018 #define  DSC_BPP(bpp)				((bpp) << 0)
8020 #define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
8021 #define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
8022 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
8023 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
8024 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
8025 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
8033 #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
8035 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
8036 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
8037 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
8038 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
8039 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
8040 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
8048 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
8050 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
8051 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
8052 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
8053 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
8054 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
8055 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
8063 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
8065 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
8066 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
8067 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
8068 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
8069 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
8070 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
8078 #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
8080 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
8081 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
8082 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
8083 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
8084 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
8085 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
8095 #define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
8097 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
8098 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
8099 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
8100 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
8101 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
8102 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
8110 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
8112 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
8113 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
8114 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
8115 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
8116 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
8117 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
8125 #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
8127 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
8128 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
8129 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
8130 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
8131 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
8132 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
8140 #define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
8142 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
8143 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
8144 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
8145 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
8146 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
8147 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
8157 #define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
8159 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
8160 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
8161 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
8162 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
8163 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
8164 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
8172 #define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
8173 #define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
8174 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
8175 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
8176 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
8177 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
8185 #define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
8186 #define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
8187 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
8188 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
8189 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
8190 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
8198 #define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
8199 #define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
8200 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
8201 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
8202 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
8203 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
8211 #define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
8212 #define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
8213 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
8214 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
8215 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
8216 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
8224 #define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
8225 #define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
8226 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
8227 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
8228 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
8229 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
8238 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
8241 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
8242 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
8243 #define DSCC_RC_BUF_THRESH_0			_MMIO(0x6BA30)
8244 #define DSCC_RC_BUF_THRESH_0_UDW		_MMIO(0x6BA30 + 4)
8245 #define _ICL_DSC0_RC_BUF_THRESH_0_PB		(0x78254)
8246 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB	(0x78254 + 4)
8247 #define _ICL_DSC1_RC_BUF_THRESH_0_PB		(0x78354)
8248 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB	(0x78354 + 4)
8249 #define _ICL_DSC0_RC_BUF_THRESH_0_PC		(0x78454)
8250 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC	(0x78454 + 4)
8251 #define _ICL_DSC1_RC_BUF_THRESH_0_PC		(0x78554)
8252 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC	(0x78554 + 4)
8266 #define DSCA_RC_BUF_THRESH_1			_MMIO(0x6B238)
8267 #define DSCA_RC_BUF_THRESH_1_UDW		_MMIO(0x6B238 + 4)
8268 #define DSCC_RC_BUF_THRESH_1			_MMIO(0x6BA38)
8269 #define DSCC_RC_BUF_THRESH_1_UDW		_MMIO(0x6BA38 + 4)
8270 #define _ICL_DSC0_RC_BUF_THRESH_1_PB		(0x7825C)
8271 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB	(0x7825C + 4)
8272 #define _ICL_DSC1_RC_BUF_THRESH_1_PB		(0x7835C)
8273 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB	(0x7835C + 4)
8274 #define _ICL_DSC0_RC_BUF_THRESH_1_PC		(0x7845C)
8275 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC	(0x7845C + 4)
8276 #define _ICL_DSC1_RC_BUF_THRESH_1_PC		(0x7855C)
8277 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC	(0x7855C + 4)
8291 #define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
8296 #define   DP_LANE_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 8))
8299 #define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
8302 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
8305 #define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
8307 #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
8310 #define _TCSS_DDI_STATUS_1			0x161500
8311 #define _TCSS_DDI_STATUS_2			0x161504
8317 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
8319 #define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
8320 #define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
8321 #define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
8322 #define SPI_STATIC_REGIONS			_MMIO(0x102090)
8323 #define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
8324 #define OROM_OFFSET				_MMIO(0x1020c0)
8328 #define _DSBSL_INSTANCE_BASE		0x70B00
8330 					 (pipe) * 0x1000 + (id) * 0x100)
8331 #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
8332 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
8333 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
8335 #define   DSB_STATUS			(1 << 0)
8337 #define CLKREQ_POLICY			_MMIO(0x101038)
8340 #define CLKGATE_DIS_MISC			_MMIO(0x46534)
8343 #define GEN12_CULLBIT1			_MMIO(0x6100)
8344 #define GEN12_CULLBIT2			_MMIO(0x7030)
8345 #define GEN12_STATE_ACK_DEBUG		_MMIO(0x20BC)
8347 #define MTL_LATENCY_LP0_LP1		_MMIO(0x45780)
8348 #define MTL_LATENCY_LP2_LP3		_MMIO(0x45784)
8349 #define MTL_LATENCY_LP4_LP5		_MMIO(0x45788)
8350 #define  MTL_LATENCY_LEVEL_EVEN_MASK	REG_GENMASK(12, 0)
8353 #define MTL_LATENCY_SAGV		_MMIO(0x4578b)
8354 #define   MTL_LATENCY_QCLK_SAGV		REG_GENMASK(12, 0)
8356 #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
8359 #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
8361 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point)	 _MMIO(0x45710 + (point) * 2)
8364 #define   MTL_DCLK_MASK			REG_GENMASK(15, 0)
8366 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)	 _MMIO(0x45714 + (point) * 2)
8368 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)