Lines Matching +full:0 +full:x46000
38 .offset = 0x21000,
41 .enable_reg = 0x45000,
42 .enable_mask = BIT(0),
56 .offset = 0x21000,
68 { P_XO, 0 },
78 .l_reg = 0x20004,
79 .m_reg = 0x20008,
80 .n_reg = 0x2000c,
81 .config_reg = 0x20010,
82 .mode_reg = 0x20000,
83 .status_reg = 0x2001c,
96 .enable_reg = 0x45000,
107 { P_XO, 0 },
121 .offset = 0x25000,
124 .enable_reg = 0x45000,
139 .offset = 0x25000,
151 { P_XO, 0 },
163 { P_XO, 0 },
177 F(19200000, P_XO, 1, 0, 0),
178 F(50000000, P_GPLL0, 16, 0, 0),
179 F(100000000, P_GPLL0, 8, 0, 0),
184 .cmd_rcgr = 0x46000,
197 .l_reg = 0x23004,
198 .m_reg = 0x23008,
199 .n_reg = 0x2300c,
200 .config_reg = 0x23010,
201 .mode_reg = 0x23000,
202 .status_reg = 0x2301c,
215 .enable_reg = 0x45000,
226 { P_XO, 0 },
238 F(19200000, P_XO, 1, 0, 0),
239 F(50000000, P_GPLL0, 16, 0, 0),
240 F(100000000, P_GPLL0, 8, 0, 0),
245 .cmd_rcgr = 0x27000,
259 .cmd_rcgr = 0x26004,
271 F(19200000, P_XO, 1, 0, 0),
272 F(50000000, P_GPLL0, 16, 0, 0),
277 .cmd_rcgr = 0x200c,
291 F(4800000, P_XO, 4, 0, 0),
292 F(9600000, P_XO, 2, 0, 0),
294 F(19200000, P_XO, 1, 0, 0),
296 F(50000000, P_GPLL0, 16, 0, 0),
301 .cmd_rcgr = 0x2024,
315 .cmd_rcgr = 0x3000,
328 .cmd_rcgr = 0x3014,
342 .cmd_rcgr = 0x4000,
355 .cmd_rcgr = 0x4024,
369 .cmd_rcgr = 0x5000,
382 .cmd_rcgr = 0x5024,
396 .cmd_rcgr = 0x6000,
409 .cmd_rcgr = 0x6024,
423 .cmd_rcgr = 0x7000,
436 .cmd_rcgr = 0x7024,
454 F(19200000, P_XO, 1, 0, 0),
469 .cmd_rcgr = 0x2044,
483 .cmd_rcgr = 0x3034,
497 .cmd_rcgr = 0x4044,
511 .cmd_rcgr = 0x5044,
525 .cmd_rcgr = 0x6044,
539 .cmd_rcgr = 0x6044,
553 F(50000000, P_GPLL0, 16, 0, 0),
554 F(80000000, P_GPLL0, 10, 0, 0),
555 F(100000000, P_GPLL0, 8, 0, 0),
556 F(160000000, P_GPLL0, 5, 0, 0),
561 .cmd_rcgr = 0x16004,
574 F(19200000, P_XO, 1, 0, 0),
579 .cmd_rcgr = 0x8004,
593 .cmd_rcgr = 0x09004,
607 .cmd_rcgr = 0x0a004,
621 F(64000000, P_GPLL0, 12.5, 0, 0),
626 .cmd_rcgr = 0x44010,
643 F(50000000, P_GPLL0, 16, 0, 0),
644 F(100000000, P_GPLL0, 8, 0, 0),
645 F(177770000, P_GPLL0, 4.5, 0, 0),
646 F(200000000, P_GPLL0, 4, 0, 0),
651 .cmd_rcgr = 0x42004,
665 .cmd_rcgr = 0x43004,
679 F(155000000, P_GPLL2, 6, 0, 0),
680 F(310000000, P_GPLL2, 3, 0, 0),
681 F(400000000, P_GPLL0, 2, 0, 0),
686 .cmd_rcgr = 0x1207c,
699 F(19200000, P_XO, 1, 0, 0),
700 F(57140000, P_GPLL0, 14, 0, 0),
701 F(69565000, P_GPLL0, 11.5, 0, 0),
702 F(133330000, P_GPLL0, 6, 0, 0),
703 F(177778000, P_GPLL0, 4.5, 0, 0),
708 .cmd_rcgr = 0x41010,
721 F(480000000, P_GPLL2, 1, 0, 0),
726 .cmd_rcgr = 0x3d018,
739 F(9600000, P_XO, 2, 0, 0),
744 .cmd_rcgr = 0x3d030,
757 F(19200000, P_XO, 1, 0, 0),
758 F(57140000, P_GPLL0, 14, 0, 0),
759 F(133330000, P_GPLL0, 6, 0, 0),
760 F(177778000, P_GPLL0, 4.5, 0, 0),
765 .cmd_rcgr = 0x3d000,
778 .halt_reg = 0x1008,
781 .enable_reg = 0x45004,
793 .halt_reg = 0x1004,
795 .enable_reg = 0x1004,
796 .enable_mask = BIT(0),
810 .halt_reg = 0x2008,
812 .enable_reg = 0x2008,
813 .enable_mask = BIT(0),
825 .halt_reg = 0x2004,
827 .enable_reg = 0x2004,
828 .enable_mask = BIT(0),
840 .halt_reg = 0x3010,
842 .enable_reg = 0x3010,
843 .enable_mask = BIT(0),
855 .halt_reg = 0x300c,
857 .enable_reg = 0x300c,
858 .enable_mask = BIT(0),
870 .halt_reg = 0x4020,
872 .enable_reg = 0x4020,
873 .enable_mask = BIT(0),
885 .halt_reg = 0x401c,
887 .enable_reg = 0x401c,
888 .enable_mask = BIT(0),
900 .halt_reg = 0x5020,
902 .enable_reg = 0x5020,
903 .enable_mask = BIT(0),
915 .halt_reg = 0x501c,
917 .enable_reg = 0x501c,
918 .enable_mask = BIT(0),
930 .halt_reg = 0x6020,
932 .enable_reg = 0x6020,
933 .enable_mask = BIT(0),
945 .halt_reg = 0x601c,
947 .enable_reg = 0x601c,
948 .enable_mask = BIT(0),
960 .halt_reg = 0x7020,
962 .enable_reg = 0x7020,
963 .enable_mask = BIT(0),
975 .halt_reg = 0x701c,
977 .enable_reg = 0x701c,
978 .enable_mask = BIT(0),
990 .halt_reg = 0x203c,
992 .enable_reg = 0x203c,
993 .enable_mask = BIT(0),
1005 .halt_reg = 0x302c,
1007 .enable_reg = 0x302c,
1008 .enable_mask = BIT(0),
1020 .halt_reg = 0x403c,
1022 .enable_reg = 0x403c,
1023 .enable_mask = BIT(0),
1035 .halt_reg = 0x503c,
1037 .enable_reg = 0x503c,
1038 .enable_mask = BIT(0),
1050 .halt_reg = 0x603c,
1052 .enable_reg = 0x603c,
1053 .enable_mask = BIT(0),
1065 .halt_reg = 0x703c,
1067 .enable_reg = 0x703c,
1068 .enable_mask = BIT(0),
1080 .halt_reg = 0x1300c,
1083 .enable_reg = 0x45004,
1095 .halt_reg = 0x16024,
1098 .enable_reg = 0x45004,
1099 .enable_mask = BIT(0),
1111 .halt_reg = 0x16020,
1114 .enable_reg = 0x45004,
1127 .halt_reg = 0x1601c,
1130 .enable_reg = 0x45004,
1143 .halt_reg = 0x08000,
1145 .enable_reg = 0x08000,
1146 .enable_mask = BIT(0),
1158 .halt_reg = 0x09000,
1160 .enable_reg = 0x09000,
1161 .enable_mask = BIT(0),
1173 .halt_reg = 0x0a000,
1175 .enable_reg = 0x0a000,
1176 .enable_mask = BIT(0),
1188 .halt_reg = 0x49000,
1190 .enable_reg = 0x49000,
1191 .enable_mask = BIT(0),
1203 .halt_reg = 0x4400c,
1205 .enable_reg = 0x4400c,
1206 .enable_mask = BIT(0),
1218 .halt_reg = 0x44004,
1220 .enable_reg = 0x44004,
1221 .enable_mask = BIT(0),
1233 .halt_reg = 0x13004,
1236 .enable_reg = 0x45004,
1249 .halt_reg = 0x4201c,
1251 .enable_reg = 0x4201c,
1252 .enable_mask = BIT(0),
1264 .halt_reg = 0x42018,
1266 .enable_reg = 0x42018,
1267 .enable_mask = BIT(0),
1279 .halt_reg = 0x4301c,
1281 .enable_reg = 0x4301c,
1282 .enable_mask = BIT(0),
1294 .halt_reg = 0x43018,
1296 .enable_reg = 0x43018,
1297 .enable_mask = BIT(0),
1309 .cmd_rcgr = 0x32004,
1322 .halt_reg = 0x49004,
1324 .enable_reg = 0x49004,
1325 .enable_mask = BIT(0),
1337 .halt_reg = 0x12018,
1340 .enable_reg = 0x4500c,
1352 .halt_reg = 0x12038,
1355 .enable_reg = 0x4500c,
1368 .halt_reg = 0x29084,
1371 .enable_reg = 0x45004,
1385 .halt_reg = 0x4102c,
1387 .enable_reg = 0x4102c,
1388 .enable_mask = BIT(0),
1402 .halt_reg = 0x41030,
1405 .enable_reg = 0x41030,
1406 .enable_mask = BIT(0),
1418 .halt_reg = 0x41008,
1420 .enable_reg = 0x41008,
1421 .enable_mask = BIT(0),
1433 .halt_reg = 0x41004,
1435 .enable_reg = 0x41004,
1436 .enable_mask = BIT(0),
1448 .halt_reg = 0x4601c,
1451 .enable_reg = 0x45004,
1463 .halt_reg = 0x4601c,
1466 .enable_reg = 0x45004,
1568 [USB_HS_HSIC_BCR] = { 0x3d05c },
1569 [GCC_MSS_RESTART] = { 0x3e000 },
1570 [USB_HS_BCR] = { 0x41000 },
1571 [USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
1572 [QUSB2_PHY_BCR] = { 0x4103c },
1579 .max_register = 0x80000,
1606 regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0)); in gcc_mdm9607_probe()