Lines Matching +full:0 +full:x46000
46 .l_reg = 0x21004,
47 .m_reg = 0x21008,
48 .n_reg = 0x2100c,
49 .config_reg = 0x21010,
50 .mode_reg = 0x21000,
51 .status_reg = 0x2101c,
64 .enable_reg = 0x45000,
65 .enable_mask = BIT(0),
77 .l_reg = 0x20004,
78 .m_reg = 0x20008,
79 .n_reg = 0x2000c,
80 .config_reg = 0x20010,
81 .mode_reg = 0x20000,
82 .status_reg = 0x2001c,
95 .enable_reg = 0x45000,
108 .l_reg = 0x4a004,
109 .m_reg = 0x4a008,
110 .n_reg = 0x4a00c,
111 .config_reg = 0x4a010,
112 .mode_reg = 0x4a000,
113 .status_reg = 0x4a01c,
126 .enable_reg = 0x45000,
139 .l_reg = 0x23004,
140 .m_reg = 0x23008,
141 .n_reg = 0x2300c,
142 .config_reg = 0x23010,
143 .mode_reg = 0x23000,
144 .status_reg = 0x2301c,
157 .enable_reg = 0x45000,
170 { P_XO, 0 },
180 { P_XO, 0 },
192 { P_XO, 0 },
206 { P_XO, 0 },
218 { P_XO, 0 },
228 { P_XO, 0 },
242 { P_XO, 0 },
254 { P_XO, 0, },
264 { P_XO, 0 },
276 { P_XO, 0 },
288 { P_XO, 0 },
300 { P_XO, 0 },
314 { P_XO, 0 },
328 { P_XO, 0 },
344 { P_XO, 0 },
360 { P_XO, 0 },
370 { P_XO, 0 },
384 .cmd_rcgr = 0x27000,
396 .cmd_rcgr = 0x26004,
409 F(80000000, P_GPLL0, 10, 0, 0),
414 .cmd_rcgr = 0x5a000,
428 F(19200000, P_XO, 1, 0, 0),
429 F(50000000, P_GPLL0, 16, 0, 0),
430 F(100000000, P_GPLL0, 8, 0, 0),
431 F(133330000, P_GPLL0, 6, 0, 0),
436 .cmd_rcgr = 0x46000,
449 F(100000000, P_GPLL0, 8, 0, 0),
450 F(200000000, P_GPLL0, 4, 0, 0),
455 .cmd_rcgr = 0x4e020,
468 .cmd_rcgr = 0x4f020,
481 F(19200000, P_XO, 1, 0, 0),
482 F(50000000, P_GPLL0_AUX, 16, 0, 0),
483 F(80000000, P_GPLL0_AUX, 10, 0, 0),
484 F(100000000, P_GPLL0_AUX, 8, 0, 0),
485 F(160000000, P_GPLL0_AUX, 5, 0, 0),
486 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
487 F(200000000, P_GPLL0_AUX, 4, 0, 0),
488 F(266670000, P_GPLL0_AUX, 3, 0, 0),
489 F(294912000, P_GPLL1, 3, 0, 0),
490 F(310000000, P_GPLL2, 3, 0, 0),
491 F(400000000, P_GPLL0_AUX, 2, 0, 0),
496 .cmd_rcgr = 0x59000,
509 F(50000000, P_GPLL0, 16, 0, 0),
510 F(80000000, P_GPLL0, 10, 0, 0),
511 F(100000000, P_GPLL0, 8, 0, 0),
512 F(160000000, P_GPLL0, 5, 0, 0),
513 F(177780000, P_GPLL0, 4.5, 0, 0),
514 F(200000000, P_GPLL0, 4, 0, 0),
515 F(266670000, P_GPLL0, 3, 0, 0),
516 F(320000000, P_GPLL0, 2.5, 0, 0),
517 F(400000000, P_GPLL0, 2, 0, 0),
518 F(465000000, P_GPLL2, 2, 0, 0),
523 .cmd_rcgr = 0x58000,
536 F(19200000, P_XO, 1, 0, 0),
537 F(50000000, P_GPLL0, 16, 0, 0),
542 .cmd_rcgr = 0x0200c,
560 F(4800000, P_XO, 4, 0, 0),
561 F(9600000, P_XO, 2, 0, 0),
563 F(19200000, P_XO, 1, 0, 0),
565 F(50000000, P_GPLL0, 16, 0, 0),
570 .cmd_rcgr = 0x02024,
584 .cmd_rcgr = 0x03000,
597 .cmd_rcgr = 0x03014,
611 .cmd_rcgr = 0x04000,
624 .cmd_rcgr = 0x04024,
638 .cmd_rcgr = 0x05000,
651 .cmd_rcgr = 0x05024,
665 .cmd_rcgr = 0x06000,
678 .cmd_rcgr = 0x06024,
692 .cmd_rcgr = 0x07000,
705 .cmd_rcgr = 0x07024,
723 F(19200000, P_XO, 1, 0, 0),
738 .cmd_rcgr = 0x02044,
752 .cmd_rcgr = 0x03034,
766 F(19200000, P_XO, 1, 0, 0),
771 .cmd_rcgr = 0x51000,
798 F(100000000, P_GPLL0, 8, 0, 0),
799 F(200000000, P_GPLL0, 4, 0, 0),
804 .cmd_rcgr = 0x54000,
818 .cmd_rcgr = 0x55000,
832 F(133330000, P_GPLL0, 6, 0, 0),
833 F(266670000, P_GPLL0, 3, 0, 0),
834 F(320000000, P_GPLL0, 2.5, 0, 0),
839 .cmd_rcgr = 0x57000,
852 F(9600000, P_XO, 2, 0, 0),
854 F(66670000, P_GPLL0, 12, 0, 0),
859 .cmd_rcgr = 0x52000,
873 .cmd_rcgr = 0x53000,
887 F(100000000, P_GPLL0, 8, 0, 0),
888 F(200000000, P_GPLL0, 4, 0, 0),
893 .cmd_rcgr = 0x4e000,
906 .cmd_rcgr = 0x4f000,
919 F(160000000, P_GPLL0, 5, 0, 0),
920 F(320000000, P_GPLL0, 2.5, 0, 0),
921 F(465000000, P_GPLL2, 2, 0, 0),
926 .cmd_rcgr = 0x58018,
939 F(50000000, P_GPLL0, 16, 0, 0),
940 F(80000000, P_GPLL0, 10, 0, 0),
941 F(100000000, P_GPLL0, 8, 0, 0),
942 F(160000000, P_GPLL0, 5, 0, 0),
947 .cmd_rcgr = 0x16004,
982 F(19200000, P_XO, 1, 0, 0),
987 .cmd_rcgr = 0x08004,
1001 .cmd_rcgr = 0x09004,
1015 .cmd_rcgr = 0x0a004,
1029 .cmd_rcgr = 0x4d044,
1042 F(19200000, P_XO, 1, 0, 0),
1047 .cmd_rcgr = 0x4d05c,
1060 F(50000000, P_GPLL0, 16, 0, 0),
1061 F(80000000, P_GPLL0, 10, 0, 0),
1062 F(100000000, P_GPLL0, 8, 0, 0),
1063 F(160000000, P_GPLL0, 5, 0, 0),
1064 F(177780000, P_GPLL0, 4.5, 0, 0),
1065 F(200000000, P_GPLL0, 4, 0, 0),
1066 F(266670000, P_GPLL0, 3, 0, 0),
1067 F(320000000, P_GPLL0, 2.5, 0, 0),
1072 .cmd_rcgr = 0x4d014,
1085 .cmd_rcgr = 0x4d000,
1099 F(19200000, P_XO, 1, 0, 0),
1104 .cmd_rcgr = 0x4d02c,
1117 F(64000000, P_GPLL0, 12.5, 0, 0),
1122 .cmd_rcgr = 0x44010,
1139 F(50000000, P_GPLL0, 16, 0, 0),
1140 F(100000000, P_GPLL0, 8, 0, 0),
1141 F(177770000, P_GPLL0, 4.5, 0, 0),
1146 .cmd_rcgr = 0x42004,
1164 F(50000000, P_GPLL0, 16, 0, 0),
1165 F(100000000, P_GPLL0, 8, 0, 0),
1166 F(200000000, P_GPLL0, 4, 0, 0),
1171 .cmd_rcgr = 0x43004,
1185 F(155000000, P_GPLL2, 6, 0, 0),
1186 F(310000000, P_GPLL2, 3, 0, 0),
1187 F(400000000, P_GPLL0, 2, 0, 0),
1192 .cmd_rcgr = 0x1207c,
1205 F(19200000, P_XO, 1, 0, 0),
1206 F(100000000, P_GPLL0, 8, 0, 0),
1207 F(200000000, P_GPLL0, 4, 0, 0),
1208 F(266500000, P_BIMC, 4, 0, 0),
1209 F(400000000, P_GPLL0, 2, 0, 0),
1210 F(533000000, P_BIMC, 2, 0, 0),
1215 .cmd_rcgr = 0x31028,
1229 F(80000000, P_GPLL0, 10, 0, 0),
1234 .cmd_rcgr = 0x41010,
1247 F(3200000, P_XO, 6, 0, 0),
1248 F(6400000, P_XO, 3, 0, 0),
1249 F(9600000, P_XO, 2, 0, 0),
1250 F(19200000, P_XO, 1, 0, 0),
1252 F(66670000, P_GPLL0, 12, 0, 0),
1253 F(80000000, P_GPLL0, 10, 0, 0),
1254 F(100000000, P_GPLL0, 8, 0, 0),
1259 .cmd_rcgr = 0x1c010,
1273 .halt_reg = 0x1c028,
1275 .enable_reg = 0x1c028,
1276 .enable_mask = BIT(0),
1290 .halt_reg = 0x1c024,
1292 .enable_reg = 0x1c024,
1293 .enable_mask = BIT(0),
1319 F(1600000, P_XO, 12, 0, 0),
1323 F(2400000, P_XO, 8, 0, 0),
1327 F(4800000, P_XO, 4, 0, 0),
1331 F(9600000, P_XO, 2, 0, 0),
1338 .cmd_rcgr = 0x1c054,
1352 .halt_reg = 0x1c068,
1354 .enable_reg = 0x1c068,
1355 .enable_mask = BIT(0),
1369 .cmd_rcgr = 0x1c06c,
1383 .halt_reg = 0x1c080,
1385 .enable_reg = 0x1c080,
1386 .enable_mask = BIT(0),
1400 .cmd_rcgr = 0x1c084,
1414 .halt_reg = 0x1c098,
1416 .enable_reg = 0x1c098,
1417 .enable_mask = BIT(0),
1431 F(19200000, P_XO, 1, 0, 0),
1436 .cmd_rcgr = 0x1c034,
1449 .halt_reg = 0x1c04c,
1451 .enable_reg = 0x1c04c,
1452 .enable_mask = BIT(0),
1466 .halt_reg = 0x1c050,
1468 .enable_reg = 0x1c050,
1469 .enable_mask = BIT(0),
1483 F(9600000, P_XO, 2, 0, 0),
1485 F(19200000, P_XO, 1, 0, 0),
1486 F(11289600, P_EXT_MCLK, 1, 0, 0),
1491 .cmd_rcgr = 0x1c09c,
1505 .halt_reg = 0x1c0b0,
1507 .enable_reg = 0x1c0b0,
1508 .enable_mask = BIT(0),
1522 .halt_reg = 0x1c000,
1524 .enable_reg = 0x1c000,
1525 .enable_mask = BIT(0),
1538 .halt_reg = 0x1c004,
1540 .enable_reg = 0x1c004,
1541 .enable_mask = BIT(0),
1554 F(100000000, P_GPLL0, 8, 0, 0),
1555 F(160000000, P_GPLL0, 5, 0, 0),
1556 F(228570000, P_GPLL0, 3.5, 0, 0),
1561 .cmd_rcgr = 0x4C000,
1575 .halt_reg = 0x01008,
1578 .enable_reg = 0x45004,
1592 .halt_reg = 0x01004,
1594 .enable_reg = 0x01004,
1595 .enable_mask = BIT(0),
1609 .halt_reg = 0x02008,
1611 .enable_reg = 0x02008,
1612 .enable_mask = BIT(0),
1626 .halt_reg = 0x02004,
1628 .enable_reg = 0x02004,
1629 .enable_mask = BIT(0),
1643 .halt_reg = 0x03010,
1645 .enable_reg = 0x03010,
1646 .enable_mask = BIT(0),
1660 .halt_reg = 0x0300c,
1662 .enable_reg = 0x0300c,
1663 .enable_mask = BIT(0),
1677 .halt_reg = 0x04020,
1679 .enable_reg = 0x04020,
1680 .enable_mask = BIT(0),
1694 .halt_reg = 0x0401c,
1696 .enable_reg = 0x0401c,
1697 .enable_mask = BIT(0),
1711 .halt_reg = 0x05020,
1713 .enable_reg = 0x05020,
1714 .enable_mask = BIT(0),
1728 .halt_reg = 0x0501c,
1730 .enable_reg = 0x0501c,
1731 .enable_mask = BIT(0),
1745 .halt_reg = 0x06020,
1747 .enable_reg = 0x06020,
1748 .enable_mask = BIT(0),
1762 .halt_reg = 0x0601c,
1764 .enable_reg = 0x0601c,
1765 .enable_mask = BIT(0),
1779 .halt_reg = 0x07020,
1781 .enable_reg = 0x07020,
1782 .enable_mask = BIT(0),
1796 .halt_reg = 0x0701c,
1798 .enable_reg = 0x0701c,
1799 .enable_mask = BIT(0),
1813 .halt_reg = 0x0203c,
1815 .enable_reg = 0x0203c,
1816 .enable_mask = BIT(0),
1830 .halt_reg = 0x0302c,
1832 .enable_reg = 0x0302c,
1833 .enable_mask = BIT(0),
1847 .halt_reg = 0x1300c,
1850 .enable_reg = 0x45004,
1864 .halt_reg = 0x5101c,
1866 .enable_reg = 0x5101c,
1867 .enable_mask = BIT(0),
1881 .halt_reg = 0x51018,
1883 .enable_reg = 0x51018,
1884 .enable_mask = BIT(0),
1898 .halt_reg = 0x4e040,
1900 .enable_reg = 0x4e040,
1901 .enable_mask = BIT(0),
1915 .halt_reg = 0x4e03c,
1917 .enable_reg = 0x4e03c,
1918 .enable_mask = BIT(0),
1932 .halt_reg = 0x4e048,
1934 .enable_reg = 0x4e048,
1935 .enable_mask = BIT(0),
1949 .halt_reg = 0x4e058,
1951 .enable_reg = 0x4e058,
1952 .enable_mask = BIT(0),
1966 .halt_reg = 0x4e050,
1968 .enable_reg = 0x4e050,
1969 .enable_mask = BIT(0),
1983 .halt_reg = 0x4f040,
1985 .enable_reg = 0x4f040,
1986 .enable_mask = BIT(0),
2000 .halt_reg = 0x4f03c,
2002 .enable_reg = 0x4f03c,
2003 .enable_mask = BIT(0),
2017 .halt_reg = 0x4f048,
2019 .enable_reg = 0x4f048,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x4f058,
2036 .enable_reg = 0x4f058,
2037 .enable_mask = BIT(0),
2051 .halt_reg = 0x4f050,
2053 .enable_reg = 0x4f050,
2054 .enable_mask = BIT(0),
2068 .halt_reg = 0x58050,
2070 .enable_reg = 0x58050,
2071 .enable_mask = BIT(0),
2085 .halt_reg = 0x54018,
2087 .enable_reg = 0x54018,
2088 .enable_mask = BIT(0),
2102 .halt_reg = 0x55018,
2104 .enable_reg = 0x55018,
2105 .enable_mask = BIT(0),
2119 .halt_reg = 0x50004,
2121 .enable_reg = 0x50004,
2122 .enable_mask = BIT(0),
2136 .halt_reg = 0x57020,
2138 .enable_reg = 0x57020,
2139 .enable_mask = BIT(0),
2153 .halt_reg = 0x57024,
2155 .enable_reg = 0x57024,
2156 .enable_mask = BIT(0),
2170 .halt_reg = 0x57028,
2172 .enable_reg = 0x57028,
2173 .enable_mask = BIT(0),
2187 .halt_reg = 0x52018,
2189 .enable_reg = 0x52018,
2190 .enable_mask = BIT(0),
2204 .halt_reg = 0x53018,
2206 .enable_reg = 0x53018,
2207 .enable_mask = BIT(0),
2221 .halt_reg = 0x5600c,
2223 .enable_reg = 0x5600c,
2224 .enable_mask = BIT(0),
2238 .halt_reg = 0x4e01c,
2240 .enable_reg = 0x4e01c,
2241 .enable_mask = BIT(0),
2255 .halt_reg = 0x4f01c,
2257 .enable_reg = 0x4f01c,
2258 .enable_mask = BIT(0),
2272 .halt_reg = 0x5a014,
2274 .enable_reg = 0x5a014,
2275 .enable_mask = BIT(0),
2289 .halt_reg = 0x56004,
2291 .enable_reg = 0x56004,
2292 .enable_mask = BIT(0),
2306 .halt_reg = 0x58040,
2308 .enable_reg = 0x58040,
2309 .enable_mask = BIT(0),
2323 .halt_reg = 0x5803c,
2325 .enable_reg = 0x5803c,
2326 .enable_mask = BIT(0),
2340 .halt_reg = 0x58038,
2342 .enable_reg = 0x58038,
2343 .enable_mask = BIT(0),
2357 .halt_reg = 0x58044,
2359 .enable_reg = 0x58044,
2360 .enable_mask = BIT(0),
2374 .halt_reg = 0x58048,
2376 .enable_reg = 0x58048,
2377 .enable_mask = BIT(0),
2391 .halt_reg = 0x16024,
2394 .enable_reg = 0x45004,
2395 .enable_mask = BIT(0),
2409 .halt_reg = 0x16020,
2412 .enable_reg = 0x45004,
2427 .halt_reg = 0x1601c,
2430 .enable_reg = 0x45004,
2445 .halt_reg = 0x59024,
2447 .enable_reg = 0x59024,
2448 .enable_mask = BIT(0),
2462 .halt_reg = 0x08000,
2464 .enable_reg = 0x08000,
2465 .enable_mask = BIT(0),
2479 .halt_reg = 0x09000,
2481 .enable_reg = 0x09000,
2482 .enable_mask = BIT(0),
2496 .halt_reg = 0x0a000,
2498 .enable_reg = 0x0a000,
2499 .enable_mask = BIT(0),
2513 .halt_reg = 0x4d07c,
2515 .enable_reg = 0x4d07c,
2516 .enable_mask = BIT(0),
2530 .halt_reg = 0x4d080,
2532 .enable_reg = 0x4d080,
2533 .enable_mask = BIT(0),
2547 .halt_reg = 0x4d094,
2549 .enable_reg = 0x4d094,
2550 .enable_mask = BIT(0),
2564 .halt_reg = 0x4d098,
2566 .enable_reg = 0x4d098,
2567 .enable_mask = BIT(0),
2581 .halt_reg = 0x4D088,
2583 .enable_reg = 0x4D088,
2584 .enable_mask = BIT(0),
2598 .halt_reg = 0x4d084,
2600 .enable_reg = 0x4d084,
2601 .enable_mask = BIT(0),
2615 .halt_reg = 0x4d090,
2617 .enable_reg = 0x4d090,
2618 .enable_mask = BIT(0),
2632 .halt_reg = 0x49000,
2634 .enable_reg = 0x49000,
2635 .enable_mask = BIT(0),
2649 .halt_reg = 0x59028,
2651 .enable_reg = 0x59028,
2652 .enable_mask = BIT(0),
2666 .halt_reg = 0x59020,
2668 .enable_reg = 0x59020,
2669 .enable_mask = BIT(0),
2683 .halt_reg = 0x4400c,
2685 .enable_reg = 0x4400c,
2686 .enable_mask = BIT(0),
2700 .halt_reg = 0x44004,
2702 .enable_reg = 0x44004,
2703 .enable_mask = BIT(0),
2717 .halt_reg = 0x13004,
2720 .enable_reg = 0x45004,
2734 .halt_reg = 0x4201c,
2736 .enable_reg = 0x4201c,
2737 .enable_mask = BIT(0),
2751 .halt_reg = 0x42018,
2753 .enable_reg = 0x42018,
2754 .enable_mask = BIT(0),
2768 .halt_reg = 0x4301c,
2770 .enable_reg = 0x4301c,
2771 .enable_mask = BIT(0),
2785 .halt_reg = 0x43018,
2787 .enable_reg = 0x43018,
2788 .enable_mask = BIT(0),
2802 .cmd_rcgr = 0x32004,
2815 .halt_reg = 0x49004,
2817 .enable_reg = 0x49004,
2818 .enable_mask = BIT(0),
2832 .halt_reg = 0x12018,
2834 .enable_reg = 0x4500c,
2848 .halt_reg = 0x12020,
2850 .enable_reg = 0x4500c,
2864 .halt_reg = 0x12044,
2866 .enable_reg = 0x4500c,
2881 .halt_reg = 0x31024,
2883 .enable_reg = 0x31024,
2884 .enable_mask = BIT(0),
2898 .halt_reg = 0x31040,
2900 .enable_reg = 0x31040,
2901 .enable_mask = BIT(0),
2915 .halt_reg = 0x12034,
2917 .enable_reg = 0x4500c,
2932 .halt_reg = 0x1201c,
2934 .enable_reg = 0x4500c,
2949 .halt_reg = 0x12038,
2951 .enable_reg = 0x4500c,
2966 .halt_reg = 0x12014,
2968 .enable_reg = 0x4500c,
2983 .halt_reg = 0x1203c,
2985 .enable_reg = 0x4500c,
3000 .halt_reg = 0x4102c,
3002 .enable_reg = 0x4102c,
3003 .enable_mask = BIT(0),
3017 .halt_reg = 0x41008,
3019 .enable_reg = 0x41008,
3020 .enable_mask = BIT(0),
3034 .halt_reg = 0x41004,
3036 .enable_reg = 0x41004,
3037 .enable_mask = BIT(0),
3051 .halt_reg = 0x4c020,
3053 .enable_reg = 0x4c020,
3054 .enable_mask = BIT(0),
3068 .halt_reg = 0x4c024,
3070 .enable_reg = 0x4c024,
3071 .enable_mask = BIT(0),
3085 .halt_reg = 0x4c01c,
3087 .enable_reg = 0x4c01c,
3088 .enable_mask = BIT(0),
3102 .gdscr = 0x4c018,
3110 .gdscr = 0x4d078,
3118 .gdscr = 0x5701c,
3126 .gdscr = 0x58034,
3134 .gdscr = 0x5901c,
3314 [GCC_BLSP1_BCR] = { 0x01000 },
3315 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3316 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3317 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3318 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3319 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3320 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3321 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3322 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3323 [GCC_IMEM_BCR] = { 0x0e000 },
3324 [GCC_SMMU_BCR] = { 0x12000 },
3325 [GCC_APSS_TCU_BCR] = { 0x12050 },
3326 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3327 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3328 [GCC_PRNG_BCR] = { 0x13000 },
3329 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3330 [GCC_CRYPTO_BCR] = { 0x16000 },
3331 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3332 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3333 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3334 [GCC_DEHR_BCR] = { 0x1f000 },
3335 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3336 [GCC_PCNOC_BCR] = { 0x27018 },
3337 [GCC_TCSR_BCR] = { 0x28000 },
3338 [GCC_QDSS_BCR] = { 0x29000 },
3339 [GCC_DCD_BCR] = { 0x2a000 },
3340 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3341 [GCC_MPM_BCR] = { 0x2c000 },
3342 [GCC_SPMI_BCR] = { 0x2e000 },
3343 [GCC_SPDM_BCR] = { 0x2f000 },
3344 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3345 [GCC_BIMC_BCR] = { 0x31000 },
3346 [GCC_RBCPR_BCR] = { 0x33000 },
3347 [GCC_TLMM_BCR] = { 0x34000 },
3348 [GCC_USB_HS_BCR] = { 0x41000 },
3349 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3350 [GCC_SDCC1_BCR] = { 0x42000 },
3351 [GCC_SDCC2_BCR] = { 0x43000 },
3352 [GCC_PDM_BCR] = { 0x44000 },
3353 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3354 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3355 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3356 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3357 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3358 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3359 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3360 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3361 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3362 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3363 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3364 [GCC_MMSS_BCR] = { 0x4b000 },
3365 [GCC_VENUS0_BCR] = { 0x4c014 },
3366 [GCC_MDSS_BCR] = { 0x4d074 },
3367 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3368 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3369 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3370 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3371 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3372 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3373 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3374 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3375 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3376 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3377 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3378 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3379 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3380 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3381 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3382 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3383 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3384 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3385 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3386 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3387 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3388 [GCC_OXILI_BCR] = { 0x59018 },
3389 [GCC_GMEM_BCR] = { 0x5902c },
3390 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3391 [GCC_MDP_TBU_BCR] = { 0x62000 },
3392 [GCC_GFX_TBU_BCR] = { 0x63000 },
3393 [GCC_GFX_TCU_BCR] = { 0x64000 },
3394 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3395 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3396 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3397 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3398 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3399 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3400 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3401 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3402 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3403 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3410 .max_register = 0x80000,