Lines Matching +full:0 +full:x46000
53 .offset = 0x21000,
56 .enable_reg = 0x0b000,
57 .enable_mask = BIT(0),
83 .offset = 0x21000,
103 { P_XO, 0 },
109 .offset = 0x25000,
113 .enable_reg = 0x0b000,
127 .offset = 0x25000,
141 .offset = 0x37000,
144 .enable_reg = 0x0b000,
158 .offset = 0x37000,
172 .offset = 0x24000,
175 .enable_reg = 0x0b000,
189 .offset = 0x24000,
203 F(24000000, P_XO, 1, 0, 0),
204 F(50000000, P_GPLL0, 16, 0, 0),
205 F(100000000, P_GPLL0, 8, 0, 0),
210 .cmd_rcgr = 0x27000,
223 .offset = 0x4a000,
226 .enable_reg = 0x0b000,
240 .offset = 0x4a000,
254 .offset = 0x22000,
257 .enable_reg = 0x0b000,
271 .offset = 0x22000,
285 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
286 F(320000000, P_GPLL0, 2.5, 0, 0),
287 F(600000000, P_GPLL4, 2, 0, 0),
300 { P_XO, 0 },
308 .cmd_rcgr = 0x29064,
333 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
334 F(240000000, P_GPLL4, 5, 0, 0),
339 .cmd_rcgr = 0x2900c,
365 F(24000000, P_XO, 1, 0, 0),
366 F(300000000, P_BIAS_PLL, 1, 0, 0),
380 { P_XO, 0 },
389 .cmd_rcgr = 0x68080,
402 .halt_reg = 0x30018,
404 .enable_reg = 0x30018,
419 F(24000000, P_XO, 1, 0, 0),
420 F(200000000, P_GPLL0, 4, 0, 0),
430 { P_XO, 0 },
435 .cmd_rcgr = 0x68098,
448 .halt_reg = 0x30000,
450 .enable_reg = 0x30000,
464 F(24000000, P_XO, 1, 0, 0),
465 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
466 F(100000000, P_GPLL0, 8, 0, 0),
467 F(133333333, P_GPLL0, 6, 0, 0),
468 F(160000000, P_GPLL0, 5, 0, 0),
469 F(200000000, P_GPLL0, 4, 0, 0),
470 F(266666667, P_GPLL0, 3, 0, 0),
483 { P_XO, 0 },
490 .cmd_rcgr = 0x76054,
503 F(24000000, P_XO, 1, 0, 0),
504 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
505 F(50000000, P_GPLL0, 16, 0, 0),
506 F(100000000, P_GPLL0, 8, 0, 0),
511 .cmd_rcgr = 0x46000,
524 F(24000000, P_XO, 1, 0, 0),
525 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
526 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
527 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
528 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
529 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
530 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
531 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
548 { P_XO, 0 },
558 .cmd_rcgr = 0x68060,
571 F(24000000, P_XO, 1, 0, 0),
572 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
573 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
574 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
575 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
576 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
577 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
578 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
595 { P_XO, 0 },
605 .cmd_rcgr = 0x68068,
618 F(24000000, P_XO, 1, 0, 0),
619 F(200000000, P_GPLL0, 4, 0, 0),
620 F(240000000, P_GPLL4, 5, 0, 0),
625 F(24000000, P_XO, 1, 0, 0),
626 F(100000000, P_GPLL0, 8, 0, 0),
637 { P_XO, 0 },
643 .cmd_rcgr = 0x75054,
656 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
657 F(100000000, P_GPLL0, 8, 0, 0),
658 F(133330000, P_GPLL0, 6, 0, 0),
659 F(200000000, P_GPLL0, 4, 0, 0),
670 { P_XO, 0 },
676 .cmd_rcgr = 0x3e00c,
690 .reg = 0x46018,
718 F(24000000, P_XO, 1, 0, 0),
719 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
720 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
733 { P_XO, 0 },
741 .cmd_rcgr = 0x68020,
754 F(24000000, P_XO, 1, 0, 0),
755 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
756 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
769 { P_XO, 0 },
777 .cmd_rcgr = 0x68028,
790 .cmd_rcgr = 0x68030,
803 .cmd_rcgr = 0x68038,
816 .cmd_rcgr = 0x68040,
829 .cmd_rcgr = 0x68048,
842 .cmd_rcgr = 0x68050,
855 .cmd_rcgr = 0x68058,
868 .reg = 0x68440,
869 .shift = 0,
884 .reg = 0x68444,
885 .shift = 0,
900 F(24000000, P_XO, 1, 0, 0),
901 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
902 F(200000000, P_GPLL0, 4, 0, 0),
903 F(308570000, P_GPLL6, 3.5, 0, 0),
904 F(400000000, P_GPLL0, 2, 0, 0),
905 F(533000000, P_GPLL0, 1.5, 0, 0),
919 { P_XO, 0 },
927 .cmd_rcgr = 0x38048,
940 F(24000000, P_XO, 1, 0, 0),
941 F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
952 { P_XO, 0 },
958 .cmd_rcgr = 0x68144,
972 .reg = 0x68400,
973 .shift = 0,
988 .reg = 0x68404,
989 .shift = 0,
1004 .reg = 0x68410,
1005 .shift = 0,
1020 .reg = 0x68414,
1021 .shift = 0,
1036 .reg = 0x68420,
1037 .shift = 0,
1052 .reg = 0x68424,
1053 .shift = 0,
1068 .reg = 0x68430,
1069 .shift = 0,
1084 .reg = 0x68434,
1085 .shift = 0,
1100 F(24000000, P_XO, 1, 0, 0),
1101 F(149760000, P_UBI32_PLL, 10, 0, 0),
1102 F(187200000, P_UBI32_PLL, 8, 0, 0),
1103 F(249600000, P_UBI32_PLL, 6, 0, 0),
1104 F(374400000, P_UBI32_PLL, 4, 0, 0),
1105 F(748800000, P_UBI32_PLL, 2, 0, 0),
1106 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1121 { P_XO, 0 },
1130 .cmd_rcgr = 0x68104,
1144 F(24000000, P_XO, 1, 0, 0),
1145 F(100000000, P_GPLL0, 8, 0, 0),
1150 .cmd_rcgr = 0x1c008,
1163 F(24000000, P_XO, 1, 0, 0),
1164 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1165 F(50000000, P_GPLL0, 16, 0, 0),
1170 .cmd_rcgr = 0x0200c,
1184 F(4800000, P_XO, 5, 0, 0),
1188 F(24000000, P_XO, 1, 0, 0),
1190 F(50000000, P_GPLL0, 16, 0, 0),
1195 .cmd_rcgr = 0x02024,
1209 .cmd_rcgr = 0x03000,
1222 .cmd_rcgr = 0x03014,
1236 .cmd_rcgr = 0x04000,
1249 .cmd_rcgr = 0x04014,
1263 .cmd_rcgr = 0x05000,
1276 .cmd_rcgr = 0x05014,
1290 .cmd_rcgr = 0x06000,
1303 .cmd_rcgr = 0x06014,
1317 .cmd_rcgr = 0x07000,
1330 .cmd_rcgr = 0x07014,
1348 F(24000000, P_XO, 1, 0, 0),
1364 .cmd_rcgr = 0x02044,
1378 .cmd_rcgr = 0x03034,
1392 .cmd_rcgr = 0x04034,
1406 .cmd_rcgr = 0x05034,
1420 .cmd_rcgr = 0x06034,
1434 .cmd_rcgr = 0x07034,
1448 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1449 F(80000000, P_GPLL0, 10, 0, 0),
1450 F(100000000, P_GPLL0, 8, 0, 0),
1451 F(160000000, P_GPLL0, 5, 0, 0),
1456 .cmd_rcgr = 0x16004,
1469 F(24000000, P_XO, 1, 0, 0),
1470 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1471 F(100000000, P_GPLL0, 8, 0, 0),
1472 F(200000000, P_GPLL0, 4, 0, 0),
1473 F(266666666, P_GPLL0, 3, 0, 0),
1486 { P_XO, 0 },
1494 .cmd_rcgr = 0x08004,
1508 .cmd_rcgr = 0x09004,
1522 .cmd_rcgr = 0x0a004,
1549 .reg = 0x68118,
1550 .shift = 0,
1565 F(24000000, P_XO, 1, 0, 0),
1575 { P_XO, 0 },
1581 .cmd_rcgr = 0x75024,
1600 { P_PCIE20_PHY0_PIPE, 0 },
1605 .reg = 0x7501c,
1625 F(96000000, P_GPLL2, 12, 0, 0),
1626 F(177777778, P_GPLL0, 4.5, 0, 0),
1627 F(192000000, P_GPLL2, 6, 0, 0),
1628 F(384000000, P_GPLL2, 3, 0, 0),
1641 { P_XO, 0 },
1648 .cmd_rcgr = 0x42004,
1662 F(24000000, P_XO, 1, 0, 0),
1667 .cmd_rcgr = 0x3e05c,
1681 F(24000000, P_XO, 1, 0, 0),
1695 { P_XO, 0 },
1702 .cmd_rcgr = 0x3e020,
1721 { P_USB3PHY_0_PIPE, 0 },
1726 .reg = 0x3e048,
1742 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1743 F(160000000, P_GPLL0, 5, 0, 0),
1744 F(216000000, P_GPLL6, 5, 0, 0),
1745 F(308570000, P_GPLL6, 3.5, 0, 0),
1756 { P_XO, 0 },
1763 .cmd_rcgr = 0x5d000,
1777 F(24000000, P_XO, 1, 0, 0),
1778 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1779 F(100000000, P_GPLL0, 8, 0, 0),
1780 F(200000000, P_GPLL0, 4, 0, 0),
1785 .cmd_rcgr = 0x2902C,
1798 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1799 F(160000000, P_GPLL0, 5, 0, 0),
1800 F(300000000, P_GPLL4, 4, 0, 0),
1812 { P_XO, 0 },
1819 .cmd_rcgr = 0x29048,
1832 .cmd_rcgr = 0x3f020,
1846 .halt_reg = 0x1c020,
1848 .enable_reg = 0x1c020,
1849 .enable_mask = BIT(0),
1862 .halt_reg = 0x4601c,
1865 .enable_reg = 0x0b004,
1879 F(24000000, P_XO, 1, 0, 0),
1880 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1881 F(100000000, P_GPLL0, 8, 0, 0),
1882 F(133333333, P_GPLL0, 6, 0, 0),
1883 F(160000000, P_GPLL0, 5, 0, 0),
1884 F(200000000, P_GPLL0, 4, 0, 0),
1885 F(266666667, P_GPLL0, 3, 0, 0),
1890 .cmd_rcgr = 0x26004,
1903 F(24000000, P_XO, 1, 0, 0),
1904 F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1905 F(533333333, P_GPLL0, 1.5, 0, 0),
1918 { P_XO, 0 },
1925 .cmd_rcgr = 0x68088,
1938 .halt_reg = 0x46020,
1941 .enable_reg = 0x0b004,
1955 .halt_reg = 0x01008,
1958 .enable_reg = 0x0b004,
1972 .halt_reg = 0x02008,
1974 .enable_reg = 0x02008,
1975 .enable_mask = BIT(0),
1988 .halt_reg = 0x02004,
1990 .enable_reg = 0x02004,
1991 .enable_mask = BIT(0),
2004 .halt_reg = 0x03010,
2006 .enable_reg = 0x03010,
2007 .enable_mask = BIT(0),
2020 .halt_reg = 0x0300c,
2022 .enable_reg = 0x0300c,
2023 .enable_mask = BIT(0),
2036 .halt_reg = 0x04010,
2038 .enable_reg = 0x04010,
2039 .enable_mask = BIT(0),
2052 .halt_reg = 0x0400c,
2054 .enable_reg = 0x0400c,
2055 .enable_mask = BIT(0),
2068 .halt_reg = 0x05010,
2070 .enable_reg = 0x05010,
2071 .enable_mask = BIT(0),
2084 .halt_reg = 0x0500c,
2086 .enable_reg = 0x0500c,
2087 .enable_mask = BIT(0),
2100 .halt_reg = 0x06010,
2102 .enable_reg = 0x06010,
2103 .enable_mask = BIT(0),
2116 .halt_reg = 0x0600c,
2118 .enable_reg = 0x0600c,
2119 .enable_mask = BIT(0),
2132 .halt_reg = 0x0700c,
2134 .enable_reg = 0x0700c,
2135 .enable_mask = BIT(0),
2148 .halt_reg = 0x0203c,
2150 .enable_reg = 0x0203c,
2151 .enable_mask = BIT(0),
2164 .halt_reg = 0x0302c,
2166 .enable_reg = 0x0302c,
2167 .enable_mask = BIT(0),
2180 .halt_reg = 0x0402c,
2182 .enable_reg = 0x0402c,
2183 .enable_mask = BIT(0),
2196 .halt_reg = 0x0502c,
2198 .enable_reg = 0x0502c,
2199 .enable_mask = BIT(0),
2212 .halt_reg = 0x0602c,
2214 .enable_reg = 0x0602c,
2215 .enable_mask = BIT(0),
2228 .halt_reg = 0x0702c,
2230 .enable_reg = 0x0702c,
2231 .enable_mask = BIT(0),
2244 .halt_reg = 0x16024,
2247 .enable_reg = 0x0b004,
2248 .enable_mask = BIT(0),
2261 .halt_reg = 0x16020,
2264 .enable_reg = 0x0b004,
2278 .halt_reg = 0x1601c,
2281 .enable_reg = 0x0b004,
2308 .halt_reg = 0x30030,
2310 .enable_reg = 0x30030,
2311 .enable_mask = BIT(0),
2324 .halt_reg = 0x08000,
2326 .enable_reg = 0x08000,
2327 .enable_mask = BIT(0),
2340 .halt_reg = 0x09000,
2342 .enable_reg = 0x09000,
2343 .enable_mask = BIT(0),
2356 .halt_reg = 0x0a000,
2358 .enable_reg = 0x0a000,
2359 .enable_mask = BIT(0),
2372 .halt_reg = 0x58004,
2374 .enable_reg = 0x58004,
2375 .enable_mask = BIT(0),
2388 .halt_reg = 0x68310,
2390 .enable_reg = 0x68310,
2391 .enable_mask = BIT(0),
2404 .halt_reg = 0x68174,
2406 .enable_reg = 0x68174,
2407 .enable_mask = BIT(0),
2420 .halt_reg = 0x68170,
2422 .enable_reg = 0x68170,
2423 .enable_mask = BIT(0),
2436 .halt_reg = 0x68160,
2438 .enable_reg = 0x68160,
2439 .enable_mask = BIT(0),
2452 .halt_reg = 0x68164,
2454 .enable_reg = 0x68164,
2455 .enable_mask = BIT(0),
2468 .halt_reg = 0x68318,
2470 .enable_reg = 0x68318,
2471 .enable_mask = BIT(0),
2484 .halt_reg = 0x6819C,
2486 .enable_reg = 0x6819C,
2487 .enable_mask = BIT(0),
2500 .halt_reg = 0x68198,
2502 .enable_reg = 0x68198,
2503 .enable_mask = BIT(0),
2516 .halt_reg = 0x68168,
2518 .enable_reg = 0x68168,
2519 .enable_mask = BIT(0),
2532 .halt_reg = 0x2606c,
2534 .enable_reg = 0x2606c,
2535 .enable_mask = BIT(0),
2548 .halt_reg = 0x26070,
2550 .enable_reg = 0x26070,
2551 .enable_mask = BIT(0),
2564 F(24000000, P_XO, 1, 0, 0),
2565 F(133333333, P_GPLL0, 6, 0, 0),
2570 F(24000000, P_XO, 1, 0, 0),
2571 F(400000000, P_GPLL0, 2, 0, 0),
2576 .cmd_rcgr = 0x59020,
2597 { P_XO, 0 },
2605 .cmd_rcgr = 0x59120,
2618 F(24000000, P_XO, 1, 0, 0),
2619 F(100000000, P_GPLL0, 8, 0, 0),
2624 .cmd_rcgr = 0x1F020,
2637 F(24000000, P_XO, 1, 0, 0),
2638 F(266666667, P_GPLL0, 3, 0, 0),
2643 .cmd_rcgr = 0x1F040,
2656 F(24000000, P_XO, 1, 0, 0),
2657 F(400000000, P_GPLL0, 2, 0, 0),
2662 .cmd_rcgr = 0x1F008,
2675 F(24000000, P_XO, 1, 0, 0),
2676 F(50000000, P_GPLL0, 16, 0, 0),
2681 .cmd_rcgr = 0x3a00c,
2694 .halt_reg = 0x1F028,
2696 .enable_reg = 0x1F028,
2697 .enable_mask = BIT(0),
2710 .halt_reg = 0x1F048,
2712 .enable_reg = 0x1F048,
2713 .enable_mask = BIT(0),
2726 .halt_reg = 0x1F010,
2728 .enable_reg = 0x1F010,
2729 .enable_mask = BIT(0),
2742 .halt_reg = 0x1F018,
2744 .enable_reg = 0x1F018,
2745 .enable_mask = BIT(0),
2758 .halt_reg = 0x1F01C,
2760 .enable_reg = 0x1F01C,
2761 .enable_mask = BIT(0),
2774 .halt_reg = 0x1F014,
2776 .enable_reg = 0x1F014,
2777 .enable_mask = BIT(0),
2790 .halt_reg = 0x1F038,
2792 .enable_reg = 0x1F038,
2793 .enable_mask = BIT(0),
2806 .halt_reg = 0x12094,
2808 .enable_reg = 0xb00c,
2822 .halt_reg = 0x27020,
2824 .enable_reg = 0x27020,
2825 .enable_mask = BIT(0),
2838 .halt_reg = 0x1D044,
2840 .enable_reg = 0x1D044,
2841 .enable_mask = BIT(0),
2854 .halt_reg = 0x26074,
2856 .enable_reg = 0x26074,
2857 .enable_mask = BIT(0),
2870 .halt_reg = 0x1D03C,
2872 .enable_reg = 0x1D03C,
2873 .enable_mask = BIT(0),
2886 .halt_reg = 0x68240,
2888 .enable_reg = 0x68240,
2889 .enable_mask = BIT(0),
2902 .halt_reg = 0x68244,
2904 .enable_reg = 0x68244,
2905 .enable_mask = BIT(0),
2918 .halt_reg = 0x68248,
2920 .enable_reg = 0x68248,
2921 .enable_mask = BIT(0),
2934 .halt_reg = 0x6824c,
2936 .enable_reg = 0x6824c,
2937 .enable_mask = BIT(0),
2950 .halt_reg = 0x68250,
2952 .enable_reg = 0x68250,
2953 .enable_mask = BIT(0),
2966 .halt_reg = 0x68254,
2968 .enable_reg = 0x68254,
2969 .enable_mask = BIT(0),
2982 .halt_reg = 0x68258,
2984 .enable_reg = 0x68258,
2985 .enable_mask = BIT(0),
2998 .halt_reg = 0x6825c,
3000 .enable_reg = 0x6825c,
3001 .enable_mask = BIT(0),
3014 .halt_reg = 0x68260,
3016 .enable_reg = 0x68260,
3017 .enable_mask = BIT(0),
3030 .halt_reg = 0x68264,
3032 .enable_reg = 0x68264,
3033 .enable_mask = BIT(0),
3046 .halt_reg = 0x68194,
3048 .enable_reg = 0x68194,
3049 .enable_mask = BIT(0),
3062 .halt_reg = 0x68190,
3064 .enable_reg = 0x68190,
3065 .enable_mask = BIT(0),
3078 .halt_reg = 0x68338,
3080 .enable_reg = 0x68338,
3081 .enable_mask = BIT(0),
3094 .halt_reg = 0x6816C,
3096 .enable_reg = 0x6816C,
3097 .enable_mask = BIT(0),
3110 .halt_reg = 0x6830C,
3112 .enable_reg = 0x6830C,
3113 .enable_mask = BIT(0),
3126 .halt_reg = 0x68308,
3128 .enable_reg = 0x68308,
3129 .enable_mask = BIT(0),
3142 .halt_reg = 0x68314,
3144 .enable_reg = 0x68314,
3145 .enable_mask = BIT(0),
3158 .halt_reg = 0x68304,
3160 .enable_reg = 0x68304,
3161 .enable_mask = BIT(0),
3173 .halt_reg = 0x68300,
3175 .enable_reg = 0x68300,
3176 .enable_mask = BIT(0),
3189 .halt_reg = 0x68180,
3191 .enable_reg = 0x68180,
3192 .enable_mask = BIT(0),
3205 .halt_reg = 0x68188,
3207 .enable_reg = 0x68188,
3208 .enable_mask = BIT(0),
3221 .halt_reg = 0x68184,
3223 .enable_reg = 0x68184,
3224 .enable_mask = BIT(0),
3237 .halt_reg = 0x68270,
3239 .enable_reg = 0x68270,
3240 .enable_mask = BIT(0),
3253 .halt_reg = 0x68320,
3255 .enable_reg = 0x68320,
3256 .enable_mask = BIT(0),
3269 .halt_reg = 0x68324,
3271 .enable_reg = 0x68324,
3272 .enable_mask = BIT(0),
3285 .halt_reg = 0x68328,
3287 .enable_reg = 0x68328,
3288 .enable_mask = BIT(0),
3301 .halt_reg = 0x6832c,
3303 .enable_reg = 0x6832c,
3304 .enable_mask = BIT(0),
3317 .halt_reg = 0x68330,
3319 .enable_reg = 0x68330,
3320 .enable_mask = BIT(0),
3333 .halt_reg = 0x6820C,
3336 .enable_reg = 0x6820C,
3337 .enable_mask = BIT(0),
3350 .halt_reg = 0x68200,
3353 .enable_reg = 0x68200,
3354 .enable_mask = BIT(0),
3367 .halt_reg = 0x68204,
3370 .enable_reg = 0x68204,
3371 .enable_mask = BIT(0),
3384 .halt_reg = 0x68210,
3387 .enable_reg = 0x68210,
3388 .enable_mask = BIT(0),
3401 .halt_reg = 0x75010,
3403 .enable_reg = 0x75010,
3404 .enable_mask = BIT(0),
3417 .halt_reg = 0x75014,
3419 .enable_reg = 0x75014,
3420 .enable_mask = BIT(0),
3433 .halt_reg = 0x75008,
3435 .enable_reg = 0x75008,
3436 .enable_mask = BIT(0),
3449 .halt_reg = 0x7500c,
3451 .enable_reg = 0x7500c,
3452 .enable_mask = BIT(0),
3465 .halt_reg = 0x26048,
3467 .enable_reg = 0x26048,
3468 .enable_mask = BIT(0),
3481 .halt_reg = 0x75018,
3484 .enable_reg = 0x75018,
3485 .enable_mask = BIT(0),
3498 .halt_reg = 0x13004,
3501 .enable_reg = 0x0b004,
3515 .halt_reg = 0x29084,
3517 .enable_reg = 0x29084,
3518 .enable_mask = BIT(0),
3531 .halt_reg = 0x57024,
3533 .enable_reg = 0x57024,
3534 .enable_mask = BIT(0),
3547 .halt_reg = 0x57020,
3549 .enable_reg = 0x57020,
3550 .enable_mask = BIT(0),
3563 .halt_reg = 0x4201c,
3565 .enable_reg = 0x4201c,
3566 .enable_mask = BIT(0),
3579 .halt_reg = 0x42018,
3581 .enable_reg = 0x42018,
3582 .enable_mask = BIT(0),
3595 .halt_reg = 0x56008,
3597 .enable_reg = 0x56008,
3598 .enable_mask = BIT(0),
3611 .halt_reg = 0x56010,
3613 .enable_reg = 0x56010,
3614 .enable_mask = BIT(0),
3627 .halt_reg = 0x56014,
3629 .enable_reg = 0x56014,
3630 .enable_mask = BIT(0),
3643 .halt_reg = 0x56018,
3645 .enable_reg = 0x56018,
3646 .enable_mask = BIT(0),
3659 .halt_reg = 0x5601c,
3661 .enable_reg = 0x5601c,
3662 .enable_mask = BIT(0),
3675 .halt_reg = 0x56020,
3677 .enable_reg = 0x56020,
3678 .enable_mask = BIT(0),
3691 .halt_reg = 0x56024,
3693 .enable_reg = 0x56024,
3694 .enable_mask = BIT(0),
3707 .halt_reg = 0x56028,
3709 .enable_reg = 0x56028,
3710 .enable_mask = BIT(0),
3723 .halt_reg = 0x5602c,
3725 .enable_reg = 0x5602c,
3726 .enable_mask = BIT(0),
3739 .halt_reg = 0x56030,
3741 .enable_reg = 0x56030,
3742 .enable_mask = BIT(0),
3755 .halt_reg = 0x56034,
3757 .enable_reg = 0x56034,
3758 .enable_mask = BIT(0),
3771 .halt_reg = 0x5600C,
3773 .enable_reg = 0x5600C,
3774 .enable_mask = BIT(0),
3787 .halt_reg = 0x56108,
3789 .enable_reg = 0x56108,
3790 .enable_mask = BIT(0),
3803 .halt_reg = 0x56110,
3805 .enable_reg = 0x56110,
3806 .enable_mask = BIT(0),
3819 .halt_reg = 0x56114,
3821 .enable_reg = 0x56114,
3822 .enable_mask = BIT(0),
3835 .halt_reg = 0x5610C,
3837 .enable_reg = 0x5610C,
3838 .enable_mask = BIT(0),
3851 .halt_reg = 0x3e044,
3853 .enable_reg = 0x3e044,
3854 .enable_mask = BIT(0),
3867 .halt_reg = 0x3e000,
3869 .enable_reg = 0x3e000,
3870 .enable_mask = BIT(0),
3883 .halt_reg = 0x47014,
3885 .enable_reg = 0x47014,
3886 .enable_mask = BIT(0),
3899 .cmd_rcgr = 0x75070,
3912 .halt_reg = 0x75070,
3914 .enable_reg = 0x75070,
3928 .halt_reg = 0x75048,
3930 .enable_reg = 0x75048,
3931 .enable_mask = BIT(0),
3944 .halt_reg = 0x26040,
3946 .enable_reg = 0x26040,
3947 .enable_mask = BIT(0),
3960 .halt_reg = 0x3e008,
3962 .enable_reg = 0x3e008,
3963 .enable_mask = BIT(0),
3976 .halt_reg = 0x3e080,
3978 .enable_reg = 0x3e080,
3979 .enable_mask = BIT(0),
3992 .halt_reg = 0x3e040,
3995 .enable_reg = 0x3e040,
3996 .enable_mask = BIT(0),
4009 .halt_reg = 0x3e004,
4011 .enable_reg = 0x3e004,
4012 .enable_mask = BIT(0),
4025 .halt_reg = 0x3f000,
4027 .enable_reg = 0x3f000,
4028 .enable_mask = BIT(0),
4041 .halt_reg = 0x3f008,
4043 .enable_reg = 0x3f008,
4044 .enable_mask = BIT(0),
4057 .halt_reg = 0x3f080,
4059 .enable_reg = 0x3f080,
4060 .enable_mask = BIT(0),
4073 .halt_reg = 0x3f004,
4075 .enable_reg = 0x3f004,
4076 .enable_mask = BIT(0),
4089 .halt_reg = 0x56308,
4091 .enable_reg = 0x56308,
4092 .enable_mask = BIT(0),
4105 .halt_reg = 0x5630c,
4107 .enable_reg = 0x5630c,
4108 .enable_mask = BIT(0),
4121 .halt_reg = 0x5d014,
4123 .enable_reg = 0x5d014,
4124 .enable_mask = BIT(0),
4137 .halt_reg = 0x77004,
4139 .enable_reg = 0x77004,
4140 .enable_mask = BIT(0),
4153 .l = 0x3e,
4154 .alpha = 0x57,
4155 .config_ctl_val = 0x240d6aa8,
4156 .config_ctl_hi_val = 0x3c2,
4157 .main_output_mask = BIT(0),
4159 .pre_div_val = 0x0,
4161 .post_div_val = 0x0,
4166 .l = 0x32,
4167 .alpha = 0x0,
4168 .alpha_hi = 0x0,
4169 .config_ctl_val = 0x4001055b,
4170 .main_output_mask = BIT(0),
4171 .pre_div_val = 0x0,
4173 .post_div_val = 0x1 << 8,
4176 .vco_val = 0x0,
4413 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4414 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4415 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4416 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4417 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4418 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4419 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4420 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4421 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4422 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4423 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4424 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4425 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4426 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4427 [GCC_SMMU_BCR] = { 0x12000, 0 },
4428 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4429 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4430 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4431 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4432 [GCC_PRNG_BCR] = { 0x13000, 0 },
4433 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4434 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4435 [GCC_WCSS_BCR] = { 0x18000, 0 },
4436 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4437 [GCC_NSS_BCR] = { 0x19000, 0 },
4438 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4439 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4440 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4441 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4442 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4443 [GCC_TCSR_BCR] = { 0x28000, 0 },
4444 [GCC_QDSS_BCR] = { 0x29000, 0 },
4445 [GCC_DCD_BCR] = { 0x2a000, 0 },
4446 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4447 [GCC_MPM_BCR] = { 0x2c000, 0 },
4448 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4449 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4450 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4451 [GCC_TLMM_BCR] = { 0x34000, 0 },
4452 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4453 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4454 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4455 [GCC_USB0_BCR] = { 0x3e070, 0 },
4456 [GCC_USB1_BCR] = { 0x3f070, 0 },
4457 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4458 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4459 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4460 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4461 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4462 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4463 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4464 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4465 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4466 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4467 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4468 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4469 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4470 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4471 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4472 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4473 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4474 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4475 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4476 [GCC_QPIC_BCR] = { 0x57018, 0 },
4477 [GCC_MDIO_BCR] = { 0x58000, 0 },
4478 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4479 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4480 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4481 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4482 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4483 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4484 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4485 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4486 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4487 [GCC_DCC_BCR] = { 0x77000, 0 },
4488 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4489 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4490 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4491 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4492 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4493 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4494 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4495 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4496 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4497 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4498 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4499 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4500 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4501 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4502 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4503 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4504 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4505 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4506 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4507 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4508 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4509 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4510 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4511 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4512 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4513 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4514 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4515 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4516 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4517 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4518 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4519 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4520 [GCC_PPE_FULL_RESET] = { 0x68014, 0 },
4521 [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
4522 [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4523 [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
4524 [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4525 [GCC_EDMA_HW_RESET] = { 0x68014, 0 },
4526 [GCC_NSSPORT1_RESET] = { 0x68014, 0 },
4527 [GCC_NSSPORT2_RESET] = { 0x68014, 0 },
4528 [GCC_NSSPORT3_RESET] = { 0x68014, 0 },
4529 [GCC_NSSPORT4_RESET] = { 0x68014, 0 },
4530 [GCC_NSSPORT5_RESET] = { 0x68014, 0 },
4531 [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
4532 [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
4533 [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
4534 [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
4535 [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
4536 [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
4537 [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
4538 [GCC_LPASS_BCR] = {0x1F000, 0},
4539 [GCC_UBI32_TBU_BCR] = {0x65000, 0},
4540 [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4541 [GCC_WCSSAON_RESET] = {0x59010, 0},
4542 [GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4543 [GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4544 [GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4545 [GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4546 [GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4547 [GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4548 [GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4549 [GCC_WCSS_DBG_ARES] = {0x59008, 0},
4550 [GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4551 [GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4552 [GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4553 [GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4554 [GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4555 [GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4556 [GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4557 [GCC_Q6_AHB_ARES] = {0x59110, 2},
4558 [GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4559 [GCC_Q6_AXIM_ARES] = {0x59110, 4},
4572 .max_register = 0x7fffc,
4595 regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); in gcc_ipq6018_probe()
4597 regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4599 regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); in gcc_ipq6018_probe()
4601 regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4604 regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); in gcc_ipq6018_probe()