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/Linux-v5.10/tools/testing/selftests/powerpc/pmu/ebb/
Dbusy_loop.S31 li r3, 0x3030
33 li r4, 0x4040
35 li r5, 0x5050
37 li r6, 0x6060
39 li r7, 0x7070
41 li r8, 0x0808
43 li r9, 0x0909
45 li r10, 0x1010
47 li r11, 0x1111
49 li r14, 0x1414
[all …]
/Linux-v5.10/drivers/gpu/drm/meson/
Dmeson_venc.c62 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
63 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
64 #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */
65 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
66 #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */
67 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
76 .video_prog_mode = 0xff,
77 .video_mode = 0x13,
78 .sch_adjust = 0x28,
79 .yc_delay = 0x343,
[all …]
/Linux-v5.10/drivers/net/wireless/ath/ath11k/
Dpci.h12 #define PCIE_SOC_GLOBAL_RESET 0x3008
15 #define WLAON_WARM_SW_ENTRY 0x1f80504
16 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
18 #define PCIE_Q6_COOKIE_ADDR 0x01f80500
19 #define PCIE_Q6_COOKIE_DATA 0xc0000000
22 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
25 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dmcp77.c45 return nvkm_rd32(device, 0x004600); in read_div()
52 u32 ctrl = nvkm_rd32(device, base + 0); in read_pll()
55 u32 post_div = 0; in read_pll()
56 u32 clock = 0; in read_pll()
60 case 0x4020: in read_pll()
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
63 case 0x4028: in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
[all …]
/Linux-v5.10/arch/parisc/include/uapi/asm/
Dsocket.h9 #define SOL_SOCKET 0xffff
11 #define SO_DEBUG 0x0001
12 #define SO_REUSEADDR 0x0004
13 #define SO_KEEPALIVE 0x0008
14 #define SO_DONTROUTE 0x0010
15 #define SO_BROADCAST 0x0020
16 #define SO_LINGER 0x0080
17 #define SO_OOBINLINE 0x0100
18 #define SO_REUSEPORT 0x0200
19 #define SO_SNDBUF 0x1001
[all …]
/Linux-v5.10/drivers/ntb/hw/intel/
Dntb_hw_gen3.h50 #define GEN3_IMBAR1SZ_OFFSET 0x00d0
51 #define GEN3_IMBAR2SZ_OFFSET 0x00d1
52 #define GEN3_EMBAR1SZ_OFFSET 0x00d2
53 #define GEN3_EMBAR2SZ_OFFSET 0x00d3
54 #define GEN3_DEVCTRL_OFFSET 0x0098
55 #define GEN3_DEVSTS_OFFSET 0x009a
56 #define GEN3_UNCERRSTS_OFFSET 0x014c
57 #define GEN3_CORERRSTS_OFFSET 0x0158
58 #define GEN3_LINK_STATUS_OFFSET 0x01a2
60 #define GEN3_NTBCNTL_OFFSET 0x0000
[all …]
/Linux-v5.10/lib/
Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/Linux-v5.10/drivers/watchdog/
Dpika_wdt.c40 module_param(heartbeat, int, 0);
45 module_param(nowayout, bool, 0);
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
117 if (test_and_set_bit(0, &pikawdt_private.open)) in pikawdt_open()
134 clear_bit(0, &pikawdt_private.open); in pikawdt_release()
135 pikawdt_private.expect_close = 0; in pikawdt_release()
136 return 0; in pikawdt_release()
146 return 0; in pikawdt_write()
[all …]
/Linux-v5.10/drivers/net/fddi/skfp/h/
Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath11k.yaml161 reg = <0xCD00000 0x4040>,
162 <0x4AB000 0x20>;
169 reg = <0xc000000 0x2000000>;
170 interrupts = <0 320 1>,
171 <0 319 1>,
172 <0 318 1>,
173 <0 317 1>,
174 <0 316 1>,
175 <0 315 1>,
176 <0 314 1>,
[all …]
/Linux-v5.10/arch/powerpc/include/asm/
Dspu.h23 #define MFC_PUT_CMD 0x20
24 #define MFC_PUTS_CMD 0x28
25 #define MFC_PUTR_CMD 0x30
26 #define MFC_PUTF_CMD 0x22
27 #define MFC_PUTB_CMD 0x21
28 #define MFC_PUTFS_CMD 0x2A
29 #define MFC_PUTBS_CMD 0x29
30 #define MFC_PUTRF_CMD 0x32
31 #define MFC_PUTRB_CMD 0x31
32 #define MFC_PUTL_CMD 0x24
[all …]
/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dsm8150.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x200>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dqcs404.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
35 #size-cells = <0>;
40 reg = <0x100>;
54 reg = <0x101>;
68 reg = <0x102>;
82 reg = <0x103>;
101 CPU_SLEEP_0: cpu-sleep-0 {
104 arm,psci-suspend-param = <0x40000003>;
158 reg = <0 0x80000000 0 0>;
[all …]
Dipq6018.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
64 reg = <0x2>;
76 reg = <0x3>;
86 cache-level = <0x2>;
134 syscon = <&tcsr_mutex_regs 0 0x80>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/ti/
Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x40f00000 0x00 0x20000>;
42 ranges = <0x00 0x00 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x00 0x43000014 0x00 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x00 0x00 0x41c00000 0x100000>;
[all …]
Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
25 reg = <0x00 0x40a00000 0x00 0x100>;
36 reg = <0x00 0x41c00000 0x00 0x80000>;
37 ranges = <0x0 0x00 0x41c00000 0x80000>;
44 reg = <0x0 0x40b00000 0x0 0x100>;
47 #size-cells = <0>;
55 reg = <0x0 0x40300000 0x0 0x400>;
60 #size-cells = <0>;
[all …]
Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x0 0x00 0x41c00000 0x100000>;
[all …]
/Linux-v5.10/drivers/media/i2c/
Dov5670.c12 #define OV5670_REG_CHIP_ID 0x300a
13 #define OV5670_CHIP_ID 0x005670
15 #define OV5670_REG_MODE_SELECT 0x0100
16 #define OV5670_MODE_STANDBY 0x00
17 #define OV5670_MODE_STREAMING 0x01
19 #define OV5670_REG_SOFTWARE_RST 0x0103
20 #define OV5670_SOFTWARE_RST 0x01
23 #define OV5670_REG_VTS 0x380e
24 #define OV5670_VTS_30FPS 0x0808 /* default for 30 fps */
25 #define OV5670_VTS_MAX 0xffff
[all …]
Dov5675.c24 #define OV5675_REG_CHIP_ID 0x300a
25 #define OV5675_CHIP_ID 0x5675
27 #define OV5675_REG_MODE_SELECT 0x0100
28 #define OV5675_MODE_STANDBY 0x00
29 #define OV5675_MODE_STREAMING 0x01
32 #define OV5675_REG_VTS 0x380e
33 #define OV5675_VTS_30FPS 0x07e4
34 #define OV5675_VTS_30FPS_MIN 0x07e4
35 #define OV5675_VTS_MAX 0x7fff
38 #define OV5675_REG_HTS 0x380c
[all …]
/Linux-v5.10/arch/c6x/platforms/
Dcache.c16 #define IMCR_CCFG 0x0000
17 #define IMCR_L1PCFG 0x0020
18 #define IMCR_L1PCC 0x0024
19 #define IMCR_L1DCFG 0x0040
20 #define IMCR_L1DCC 0x0044
21 #define IMCR_L2ALLOC0 0x2000
22 #define IMCR_L2ALLOC1 0x2004
23 #define IMCR_L2ALLOC2 0x2008
24 #define IMCR_L2ALLOC3 0x200c
25 #define IMCR_L2WBAR 0x4000
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dimx28-pinfunc.h19 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
20 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
21 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
22 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
23 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
24 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
25 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
26 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
27 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
28 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/Linux-v5.10/arch/sh/include/asm/
Dhd64461.h10 * (please note manual reference 0x10000000 = 0xb0000000)
14 #define HD64461_PCC_WINDOW 0x01000000
16 /* Area 6 - Slot 0 - memory and/or IO card */
17 #define HD64461_IOBASE 0xb0000000
19 #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
20 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
21 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
22 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
25 #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
26 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
[all …]
/Linux-v5.10/include/linux/mfd/wm831x/
Dcore.h25 #define WM831X_RESET_ID 0x00
26 #define WM831X_REVISION 0x01
27 #define WM831X_PARENT_ID 0x4000
28 #define WM831X_SYSVDD_CONTROL 0x4001
29 #define WM831X_THERMAL_MONITORING 0x4002
30 #define WM831X_POWER_STATE 0x4003
31 #define WM831X_WATCHDOG 0x4004
32 #define WM831X_ON_PIN_CONTROL 0x4005
33 #define WM831X_RESET_CONTROL 0x4006
34 #define WM831X_CONTROL_INTERFACE 0x4007
[all …]
/Linux-v5.10/arch/alpha/include/asm/
Dcore_mcpcia.h58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
70 * 10 11 Longword 0000 0x058
[all …]
/Linux-v5.10/drivers/pci/controller/dwc/
Dpcie-artpec6.c48 #define PCIECFG 0x18
60 #define PCIECFG_MACRO_ENABLE BIT(0)
65 #define PCIESTAT 0x1c
69 #define NOCCFG 0x40
75 #define PHY_STATUS 0x118
76 #define PHY_COSPLLLOCK BIT(0)
78 #define PHY_TX_ASIC_OUT 0x4040
79 #define PHY_TX_ASIC_OUT_TX_ACK BIT(0)
81 #define PHY_RX_ASIC_OUT 0x405c
82 #define PHY_RX_ASIC_OUT_ACK BIT(0)
[all …]

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