62 #define HHI_GCLK_MPEG2		0x148 /* 0x52 offset in data sheet */
63 #define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
64 #define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbb offset in data sheet */
65 #define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
66 #define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbc offset in data sheet */
67 #define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */
76 	.video_prog_mode = 0xff,
77 	.video_mode = 0x13,
78 	.sch_adjust = 0x28,
79 	.yc_delay = 0x343,
87 	.video_contrast = 0,
88 	.video_brightness = 0,
89 	.video_hue = 0,
90 	.analog_sync_adj = 0x8080,
99 	.macv_max_amp = 0xb,
100 	.video_prog_mode = 0xf0,
101 	.video_mode = 0x8,
102 	.sch_adjust = 0x20,
103 	.yc_delay = 0x333,
112 	.video_brightness = 0,
113 	.video_hue = 0,
114 	.analog_sync_adj = 0x9c00,
195 		.macv_max_amp = 0xb,
196 		.video_prog_mode = 0xf0,
197 		.video_mode = 0x8,
198 		.sch_adjust = 0x20,
199 		.yc_delay = 0,
215 		.macv_max_amp = 0x7,
216 		.video_prog_mode = 0xff,
217 		.video_mode = 0x13,
218 		.sch_adjust = 0x28,
219 		.yc_delay = 0x333,
231 		.dvi_settings = 0x21,
232 		.video_mode = 0x4000,
233 		.video_mode_adv = 0x9,
234 		.video_prog_mode = 0,
240 		.video_filt_ctrl = 0x2052,
246 		.hspuls_begin = 0x22,
247 		.hspuls_end = 0xa0,
249 		.vspuls_begin = 0,
251 		.vspuls_bline = 0,
265 		.vso_bline = 0,
269 		.sy2_val = 0x1d8,
277 		.dvi_settings = 0x21,
278 		.video_mode = 0x4000,
279 		.video_mode_adv = 0x9,
280 		.video_prog_mode = 0,
286 		.video_filt_ctrl = 0x52,
292 		.hspuls_begin = 0,
293 		.hspuls_end = 0x80,
295 		.vspuls_begin = 0,
297 		.vspuls_bline = 0,
307 		.hso_begin = 0x80,
308 		.hso_end = 0,
309 		.vso_begin = 0,
311 		.vso_bline = 0,
315 		.sy2_val = 0x1d8,
323 		.dvi_settings = 0x2029,
324 		.video_mode = 0x4040,
325 		.video_mode_adv = 0x19,
354 		.vso_bline = 0,
365 		.dvi_settings = 0x202d,
366 		.video_mode = 0x4040,
367 		.video_mode_adv = 0x19,
368 		.video_prog_mode = 0x100,
370 		.video_sync_mode = 0x407,
372 		.video_yc_dly = 0,
399 		.vso_bline = 0,
410 		.dvi_settings = 0x2029,
411 		.video_mode = 0x5ffc,
412 		.video_mode_adv = 0x19,
413 		.video_prog_mode = 0x100,
415 		.video_sync_mode = 0x207,
420 		.video_ofld_voav_ofst = 0x11,
430 		.vspuls_bline = 0,
440 		.eqpuls_bline = 0,
448 		.vso_bline = 0,
459 		.dvi_settings = 0x202d,
460 		.video_mode = 0x5ffc,
461 		.video_mode_adv = 0x19,
462 		.video_prog_mode = 0x100,
464 		.video_sync_mode = 0x7,
469 		.video_ofld_voav_ofst = 0x11,
479 		.vspuls_bline = 0,
489 		.eqpuls_bline = 0,
497 		.vso_bline = 0,
508 		.dvi_settings = 0xd,
509 		.video_mode = 0x4040,
510 		.video_mode_adv = 0x18,
511 		.video_prog_mode = 0x100,
513 		.video_sync_mode = 0x7,
515 		.video_yc_dly = 0,
519 		.video_filt_ctrl = 0x1052,
530 		.vspuls_bline = 0,
538 		.eqpuls_bline = 0,
546 		.vso_bline = 0,
557 		.dvi_settings = 0x1,
558 		.video_mode = 0x4040,
559 		.video_mode_adv = 0x18,
560 		.video_prog_mode = 0x100,
565 		.video_filt_ctrl = 0x1052,
576 		.vspuls_bline = 0,
590 		.vso_bline = 0,
601 		.dvi_settings = 0xd,
602 		.video_mode = 0x4040,
603 		.video_mode_adv = 0x18,
604 		.video_prog_mode = 0x100,
606 		.video_sync_mode = 0x7,
608 		.video_yc_dly = 0,
622 		.vspuls_bline = 0,
630 		.eqpuls_bline = 0,
638 		.vso_bline = 0,
649 		.dvi_settings = 0x1,
650 		.video_mode = 0x4040,
651 		.video_mode_adv = 0x18,
652 		.video_prog_mode = 0x100,
657 		.video_filt_ctrl = 0x1052,
668 		.vspuls_bline = 0,
682 		.vso_bline = 0,
693 		.dvi_settings = 0x1,
694 		.video_mode = 0x4040,
695 		.video_mode_adv = 0x8,
699 		.video_filt_ctrl = 0x1000,
710 		.vspuls_bline = 0,
735 		.dvi_settings = 0x1,
736 		.video_mode = 0x4040,
737 		.video_mode_adv = 0x8,
741 		.video_filt_ctrl = 0x1000,
752 		.vspuls_bline = 0,
777 		.dvi_settings = 0x1,
778 		.video_mode = 0x4040,
779 		.video_mode_adv = 0x8,
783 		.video_filt_ctrl = 0x1000,
794 		.vspuls_bline = 0,
843 	{ 0, NULL}, /* sentinel */
896 	memset(dmt_mode, 0, sizeof(*dmt_mode));  in meson_venc_hdmi_get_dmt_vmode()
898 	dmt_mode->encp.dvi_settings = 0x21;  in meson_venc_hdmi_get_dmt_vmode()
899 	dmt_mode->encp.video_mode = 0x4040;  in meson_venc_hdmi_get_dmt_vmode()
900 	dmt_mode->encp.video_mode_adv = 0x18;  in meson_venc_hdmi_get_dmt_vmode()
908 	dmt_mode->encp.hso_begin = 0;  in meson_venc_hdmi_get_dmt_vmode()
912 	dmt_mode->encp.vso_bline = 0;  in meson_venc_hdmi_get_dmt_vmode()
959 	unsigned long total_pixels_venc = 0;  in meson_venc_hdmi_mode_set()
960 	unsigned long active_pixels_venc = 0;  in meson_venc_hdmi_mode_set()
961 	unsigned long front_porch_venc = 0;  in meson_venc_hdmi_mode_set()
962 	unsigned long hsync_pixels_venc = 0;  in meson_venc_hdmi_mode_set()
963 	unsigned long de_h_begin = 0;  in meson_venc_hdmi_mode_set()
964 	unsigned long de_h_end = 0;  in meson_venc_hdmi_mode_set()
965 	unsigned long de_v_begin_even = 0;  in meson_venc_hdmi_mode_set()
966 	unsigned long de_v_end_even = 0;  in meson_venc_hdmi_mode_set()
967 	unsigned long de_v_begin_odd = 0;  in meson_venc_hdmi_mode_set()
968 	unsigned long de_v_end_odd = 0;  in meson_venc_hdmi_mode_set()
969 	unsigned long hs_begin = 0;  in meson_venc_hdmi_mode_set()
970 	unsigned long hs_end = 0;  in meson_venc_hdmi_mode_set()
971 	unsigned long vs_adjust = 0;  in meson_venc_hdmi_mode_set()
972 	unsigned long vs_bline_evn = 0;  in meson_venc_hdmi_mode_set()
973 	unsigned long vs_eline_evn = 0;  in meson_venc_hdmi_mode_set()
974 	unsigned long vs_bline_odd = 0;  in meson_venc_hdmi_mode_set()
975 	unsigned long vs_eline_odd = 0;  in meson_venc_hdmi_mode_set()
976 	unsigned long vso_begin_evn = 0;  in meson_venc_hdmi_mode_set()
977 	unsigned long vso_begin_odd = 0;  in meson_venc_hdmi_mode_set()
1043 	writel_bits_relaxed(0xff, 0xff,  in meson_venc_hdmi_mode_set()
1046 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));  in meson_venc_hdmi_mode_set()
1047 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));  in meson_venc_hdmi_mode_set()
1054 		writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,  in meson_venc_hdmi_mode_set()
1061 		writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));  in meson_venc_hdmi_mode_set()
1064 		writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));  in meson_venc_hdmi_mode_set()
1065 		writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));  in meson_venc_hdmi_mode_set()
1092 		 * Demux shifting 0x2  in meson_venc_hdmi_mode_set()
1108 		writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));  in meson_venc_hdmi_mode_set()
1116 		writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));  in meson_venc_hdmi_mode_set()
1124 		 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y  in meson_venc_hdmi_mode_set()
1127 			       ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),  in meson_venc_hdmi_mode_set()
1191 			vs_adjust  = 0;  in meson_venc_hdmi_mode_set()
1434 			de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)  in meson_venc_hdmi_mode_set()
1454 			vs_adjust  = 0;  in meson_venc_hdmi_mode_set()
1569 	writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,  in meson_venci_cvbs_mode_set()
1576 	writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));  in meson_venci_cvbs_mode_set()
1579 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));  in meson_venci_cvbs_mode_set()
1580 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));  in meson_venci_cvbs_mode_set()
1607 	 * Demux shifting 0x2  in meson_venci_cvbs_mode_set()
1622 	writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));  in meson_venci_cvbs_mode_set()
1624 	/* 0x3 Y, C, and Component Y delay */  in meson_venci_cvbs_mode_set()
1644 	writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));  in meson_venci_cvbs_mode_set()
1647 	writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));  in meson_venci_cvbs_mode_set()
1655 	 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y  in meson_venci_cvbs_mode_set()
1658 		       ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),  in meson_venci_cvbs_mode_set()
1662 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));  in meson_venci_cvbs_mode_set()
1695 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));  in meson_venci_cvbs_mode_set()
1696 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));  in meson_venci_cvbs_mode_set()
1697 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));  in meson_venci_cvbs_mode_set()
1698 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));  in meson_venci_cvbs_mode_set()
1699 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));  in meson_venci_cvbs_mode_set()
1700 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));  in meson_venci_cvbs_mode_set()
1709 	/* Select ENCI DACs 0, 1, 4, and 5 */  in meson_venci_cvbs_mode_set()
1710 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));  in meson_venci_cvbs_mode_set()
1711 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));  in meson_venci_cvbs_mode_set()
1730 	writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));  in meson_venci_cvbs_mode_set()
1732 	/* 0 in Macrovision register 0 */  in meson_venci_cvbs_mode_set()
1733 	writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));  in meson_venci_cvbs_mode_set()
1757 	regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);  in meson_venc_disable_vsync()
1758 	writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));  in meson_venc_disable_vsync()
1765 		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);  in meson_venc_init()
1768 		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);  in meson_venc_init()
1773 	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));  in meson_venc_init()
1776 	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);  in meson_venc_init()
1780 			    VPU_HDMI_ENCP_DATA_TO_HDMI, 0,  in meson_venc_init()
1784 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));  in meson_venc_init()
1785 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));  in meson_venc_init()
1786 	writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));  in meson_venc_init()