Lines Matching +full:0 +full:x4040
22 #clock-cells = <0>;
28 #clock-cells = <0>;
35 #size-cells = <0>;
40 reg = <0x100>;
54 reg = <0x101>;
68 reg = <0x102>;
82 reg = <0x103>;
101 CPU_SLEEP_0: cpu-sleep-0 {
104 arm,psci-suspend-param = <0x40000003>;
158 reg = <0 0x80000000 0 0>;
172 reg = <0 0x85900000 0 0x500000>;
177 reg = <0 0x85e00000 0 0x100000>;
182 reg = <0 0x85f00000 0 0x200000>;
187 reg = <0 0x86100000 0 0x300000>;
192 reg = <0 0x86400000 0 0x1100000>;
197 reg = <0 0x87500000 0 0x1a00000>;
202 reg = <0 0x88f00000 0 0x600000>;
207 reg = <0 0x89500000 0 0x100000>;
212 reg = <0 0x9f800000 0 0x800000>;
222 mboxes = <&apcs_glb 0>;
300 syscon = <&tcsr_mutex_regs 0 0x1000>;
304 soc: soc@0 {
307 ranges = <0 0 0 0xffffffff>;
312 reg = <0x00800000 0x30000>;
323 reg = <0x00060000 0x6000>;
328 reg = <0x00078000 0x400>;
329 #phy-cells = <0>;
342 reg = <0x0007a000 0x200>;
343 #phy-cells = <0>;
356 reg = <0x0007c000 0x200>;
357 #phy-cells = <0>;
370 reg = <0x000a4000 0x1000>;
374 reg = <0x1f8 0x14>;
377 reg = <0x13c 0x4>;
381 reg = <0x231 0x4>;
385 reg = <0x232 0x4>;
389 reg = <0x233 0x4>;
393 reg = <0x229 0x4>;
397 reg = <0x22a 0x4>;
401 reg = <0x22b 0x4>;
402 bits = <0 6>;
405 reg = <0x22b 0x4>;
409 reg = <0x22d 0x4>;
413 reg = <0x230 0x4>;
414 bits = <0 12>;
417 reg = <0x228 0x4>;
418 bits = <0 3>;
421 reg = <0x228 0x4>;
425 reg = <0x229 0x4>;
426 bits = <0 3>;
429 reg = <0x218 0x4>;
436 reg = <0x000e3000 0x1000>;
442 reg = <0x00400000 0x80000>;
452 reg = <0x004a9000 0x1000>, /* TM */
453 <0x004a8000 0x1000>; /* SROT */
463 reg = <0x00500000 0x15080>;
472 reg = <0x00580000 0x23080>;
482 reg = <0x00b00000 0x4040>;
485 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
512 qcom,halt-regs = <&tcsr 0x19004>;
516 qcom,smem-states = <&cdsp_smp2p_out 0>;
533 reg = <0x07678800 0x400>;
549 reg = <0x07580000 0xcd00>;
554 snps,hird-threshold = /bits/ 8 <0x10>;
562 reg = <0x079b8800 0x400>;
578 reg = <0x078c0000 0xcc00>;
583 snps,hird-threshold = /bits/ 8 <0x10>;
591 reg = <0x01000000 0x200000>,
592 <0x01300000 0x200000>,
593 <0x07b00000 0x200000>;
596 gpio-ranges = <&tlmm 0 0 120>;
704 reg = <0x01800000 0x80000>;
714 reg = <0x01905000 0x20000>;
719 reg = <0x01937000 0x25000>;
724 reg = <0x0200f000 0x001000>,
725 <0x02400000 0x800000>,
726 <0x02c00000 0x800000>,
727 <0x03800000 0x200000>,
728 <0x0200a000 0x002100>;
732 qcom,ee = <0>;
733 qcom,channel = <0>;
735 #size-cells = <0>;
742 reg = <0x07400000 0x4040>;
745 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
757 qcom,smem-states = <&wcss_smp2p_out 0>;
774 reg = <0x07786000 0xb8>;
782 #phy-cells = <0>;
789 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
806 reg = <0x07884000 0x25000>;
811 qcom,ee = <0>;
817 reg = <0x078af000 0x200>;
821 dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
824 pinctrl-0 = <&blsp1_uart0_default>;
830 reg = <0x078b0000 0x200>;
837 pinctrl-0 = <&blsp1_uart1_default>;
843 reg = <0x078b1000 0x200>;
850 pinctrl-0 = <&blsp1_uart2_default>;
856 reg = <0x07a80000 0x10000>,
857 <0x07a96000 0x100>;
877 reg = <0xa000000 0x800000>;
897 reg = <0x078b2000 0x200>;
904 pinctrl-0 = <&blsp1_uart3_default>;
910 reg = <0x078b5000 0x600>;
916 pinctrl-0 = <&blsp1_i2c0_default>;
918 #size-cells = <0>;
924 reg = <0x078b5000 0x600>;
930 pinctrl-0 = <&blsp1_spi0_default>;
932 #size-cells = <0>;
938 reg = <0x078b6000 0x600>;
944 pinctrl-0 = <&blsp1_i2c1_default>;
946 #size-cells = <0>;
952 reg = <0x078b6000 0x600>;
958 pinctrl-0 = <&blsp1_spi1_default>;
960 #size-cells = <0>;
966 reg = <0x078b7000 0x600>;
972 pinctrl-0 = <&blsp1_i2c2_default>;
974 #size-cells = <0>;
980 reg = <0x078b7000 0x600>;
986 pinctrl-0 = <&blsp1_spi2_default>;
988 #size-cells = <0>;
994 reg = <0x078b8000 0x600>;
1000 pinctrl-0 = <&blsp1_i2c3_default>;
1002 #size-cells = <0>;
1008 reg = <0x078b8000 0x600>;
1014 pinctrl-0 = <&blsp1_spi3_default>;
1016 #size-cells = <0>;
1022 reg = <0x078b9000 0x600>;
1028 pinctrl-0 = <&blsp1_i2c4_default>;
1030 #size-cells = <0>;
1036 reg = <0x078b9000 0x600>;
1042 pinctrl-0 = <&blsp1_spi4_default>;
1044 #size-cells = <0>;
1050 reg = <0x07ac4000 0x17000>;
1055 qcom,ee = <0>;
1061 reg = <0x07aef000 0x200>;
1065 dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
1068 pinctrl-0 = <&blsp2_uart0_default>;
1074 reg = <0x07af5000 0x600>;
1080 pinctrl-0 = <&blsp2_i2c0_default>;
1082 #size-cells = <0>;
1088 reg = <0x07af5000 0x600>;
1094 pinctrl-0 = <&blsp2_spi0_default>;
1096 #size-cells = <0>;
1102 reg = <0x08600000 0x1000>;
1107 ranges = <0 0x08600000 0x1000>;
1111 reg = <0x94c 0xc8>;
1119 reg = <0x0b000000 0x1000>,
1120 <0x0b002000 0x1000>;
1125 reg = <0x0b011000 0x1000>;
1129 #clock-cells = <0>;
1134 reg = <0x0b016000 0x30>;
1135 #clock-cells = <0>;
1143 reg = <0x0b017000 0x1000>;
1149 reg = <0x0b018000 0x1000>;
1150 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
1154 #power-domain-cells = <0>;
1191 reg = <0x0b120000 0x1000>;
1195 frame-number = <0>;
1198 reg = <0x0b121000 0x1000>,
1199 <0x0b122000 0x1000>;
1205 reg = <0x0b123000 0x1000>;
1212 reg = <0x0b124000 0x1000>;
1219 reg = <0x0b125000 0x1000>;
1226 reg = <0x0b126000 0x1000>;
1233 reg = <0xb127000 0x1000>;
1240 reg = <0x0b128000 0x1000>;
1247 reg = <0x0c700000 0x4040>;
1250 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1262 qcom,smem-states = <&adsp_smp2p_out 0>;
1279 reg = <0x10000000 0xf1d>,
1280 <0x10000f20 0xa8>,
1281 <0x07780000 0x2000>,
1282 <0x10001000 0x2000>;
1285 linux,pci-domain = <0>;
1286 bus-range = <0x00 0xff>;
1291 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
1292 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
1297 interrupt-map-mask = <0 0 0 0x7>;
1298 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1299 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1300 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1301 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1330 interrupts = <GIC_PPI 2 0xff08>,
1331 <GIC_PPI 3 0xff08>,
1332 <GIC_PPI 4 0xff08>,
1333 <GIC_PPI 1 0xff08>;
1341 qcom,local-pid = <0>;
1361 qcom,local-pid = <0>;
1381 qcom,local-pid = <0>;
1401 thermal-sensors = <&tsens 0>;