Lines Matching +full:0 +full:x4040
16 #define IMCR_CCFG 0x0000
17 #define IMCR_L1PCFG 0x0020
18 #define IMCR_L1PCC 0x0024
19 #define IMCR_L1DCFG 0x0040
20 #define IMCR_L1DCC 0x0044
21 #define IMCR_L2ALLOC0 0x2000
22 #define IMCR_L2ALLOC1 0x2004
23 #define IMCR_L2ALLOC2 0x2008
24 #define IMCR_L2ALLOC3 0x200c
25 #define IMCR_L2WBAR 0x4000
26 #define IMCR_L2WWC 0x4004
27 #define IMCR_L2WIBAR 0x4010
28 #define IMCR_L2WIWC 0x4014
29 #define IMCR_L2IBAR 0x4018
30 #define IMCR_L2IWC 0x401c
31 #define IMCR_L1PIBAR 0x4020
32 #define IMCR_L1PIWC 0x4024
33 #define IMCR_L1DWIBAR 0x4030
34 #define IMCR_L1DWIWC 0x4034
35 #define IMCR_L1DWBAR 0x4040
36 #define IMCR_L1DWWC 0x4044
37 #define IMCR_L1DIBAR 0x4048
38 #define IMCR_L1DIWC 0x404c
39 #define IMCR_L2WB 0x5000
40 #define IMCR_L2WBINV 0x5004
41 #define IMCR_L2INV 0x5008
42 #define IMCR_L1PINV 0x5028
43 #define IMCR_L1DWB 0x5040
44 #define IMCR_L1DWBINV 0x5044
45 #define IMCR_L1DINV 0x5048
46 #define IMCR_MAR_BASE 0x8000
47 #define IMCR_MAR96_111 0x8180
48 #define IMCR_MAR128_191 0x8200
49 #define IMCR_MAR224_239 0x8380
50 #define IMCR_L2MPFAR 0xa000
51 #define IMCR_L2MPFSR 0xa004
52 #define IMCR_L2MPFCR 0xa008
53 #define IMCR_L2MPLK0 0xa100
54 #define IMCR_L2MPLK1 0xa104
55 #define IMCR_L2MPLK2 0xa108
56 #define IMCR_L2MPLK3 0xa10c
57 #define IMCR_L2MPLKCMD 0xa110
58 #define IMCR_L2MPLKSTAT 0xa114
59 #define IMCR_L2MPPA_BASE 0xa200
60 #define IMCR_L1PMPFAR 0xa400
61 #define IMCR_L1PMPFSR 0xa404
62 #define IMCR_L1PMPFCR 0xa408
63 #define IMCR_L1PMPLK0 0xa500
64 #define IMCR_L1PMPLK1 0xa504
65 #define IMCR_L1PMPLK2 0xa508
66 #define IMCR_L1PMPLK3 0xa50c
67 #define IMCR_L1PMPLKCMD 0xa510
68 #define IMCR_L1PMPLKSTAT 0xa514
69 #define IMCR_L1PMPPA_BASE 0xa600
70 #define IMCR_L1DMPFAR 0xac00
71 #define IMCR_L1DMPFSR 0xac04
72 #define IMCR_L1DMPFCR 0xac08
73 #define IMCR_L1DMPLK0 0xad00
74 #define IMCR_L1DMPLK1 0xad04
75 #define IMCR_L1DMPLK2 0xad08
76 #define IMCR_L1DMPLK3 0xad0c
77 #define IMCR_L1DMPLKCMD 0xad10
78 #define IMCR_L1DMPLKSTAT 0xad14
79 #define IMCR_L1DMPPA_BASE 0xae00
80 #define IMCR_L2PDWAKE0 0xc040
81 #define IMCR_L2PDWAKE1 0xc044
82 #define IMCR_L2PDSLEEP0 0xc050
83 #define IMCR_L2PDSLEEP1 0xc054
84 #define IMCR_L2PDSTAT0 0xc060
85 #define IMCR_L2PDSTAT1 0xc064
90 #define L2MODE_0K_CACHE 0x0
91 #define L2MODE_32K_CACHE 0x1
92 #define L2MODE_64K_CACHE 0x2
93 #define L2MODE_128K_CACHE 0x3
94 #define L2MODE_256K_CACHE 0x7
96 #define L2PRIO_URGENT 0x0
97 #define L2PRIO_HIGH 0x1
98 #define L2PRIO_MEDIUM 0x2
99 #define L2PRIO_LOW 0x3
101 #define CCFG_ID 0x100 /* Invalidate L1P bit */
102 #define CCFG_IP 0x200 /* Invalidate L1D bit */
114 } while (0)
138 unsigned int wc = 0; in cache_block_operation()
159 if (wcnt > 0xffff) in cache_block_operation()
160 wc = 0xffff; in cache_block_operation()
165 imcr_set(wc_reg, wc & 0xffff); in cache_block_operation()
183 unsigned int wc = 0; in cache_block_operation_nowait()
191 if (wcnt > 0xffff) in cache_block_operation_nowait()
192 wc = 0xffff; in cache_block_operation_nowait()
197 imcr_set(wc_reg, wc & 0xffff); in cache_block_operation_nowait()
202 if (wcnt > 0xffff) in cache_block_operation_nowait()
218 imcr_set(IMCR_L1PCFG, 0); in L1_cache_off()
221 imcr_set(IMCR_L1DCFG, 0); in L1_cache_off()
432 cache_base = of_iomap(node, 0); in c6x_cache_init()