Lines Matching +full:0 +full:x4040
19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x0 0x00 0x41c00000 0x100000>;
75 reg = <0x00 0x42300000 0x00 0x100>;
82 clocks = <&k3_clks 287 0>;
88 reg = <0x00 0x40a00000 0x00 0x100>;
95 clocks = <&k3_clks 149 0>;
112 reg = <0x0 0x42110000 0x0 0x100>;
120 ti,davinci-gpio-unbanked = <0>;
122 clocks = <&k3_clks 113 0>;
128 reg = <0x0 0x42100000 0x0 0x100>;
136 ti,davinci-gpio-unbanked = <0>;
138 clocks = <&k3_clks 114 0>;
144 reg = <0x0 0x40b00000 0x0 0x100>;
147 #size-cells = <0>;
149 clocks = <&k3_clks 194 0>;
155 reg = <0x0 0x40b10000 0x0 0x100>;
158 #size-cells = <0>;
160 clocks = <&k3_clks 195 0>;
166 reg = <0x0 0x42120000 0x0 0x100>;
169 #size-cells = <0>;
171 clocks = <&k3_clks 197 0>;
177 reg = <0x0 0x47000000 0x0 0x100>;
184 reg = <0x0 0x47040000 0x0 0x100>,
185 <0x5 0x00000000 0x1 0x0000000>;
189 cdns,trigger-address = <0x0>;
190 clocks = <&k3_clks 103 0>;
191 assigned-clocks = <&k3_clks 103 0>;
196 #size-cells = <0>;
201 reg = <0x0 0x47050000 0x0 0x100>,
202 <0x7 0x00000000 0x1 0x00000000>;
206 cdns,trigger-address = <0x0>;
207 clocks = <&k3_clks 104 0>;
210 #size-cells = <0>;
216 reg = <0x0 0x40200000 0x0 0x1000>;
218 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
219 clocks = <&k3_clks 0 1>;
220 assigned-clocks = <&k3_clks 0 3>;
223 dmas = <&main_udmap 0x7400>,
224 <&main_udmap 0x7401>;
235 reg = <0x0 0x40210000 0x0 0x1000>;
242 dmas = <&main_udmap 0x7402>,
243 <&main_udmap 0x7403>;
264 reg = <0x0 0x2b800000 0x0 0x400000>,
265 <0x0 0x2b000000 0x0 0x400000>,
266 <0x0 0x28590000 0x0 0x100>,
267 <0x0 0x2a500000 0x0 0x40000>;
270 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
278 reg = <0x0 0x285c0000 0x0 0x100>,
279 <0x0 0x2a800000 0x0 0x40000>,
280 <0x0 0x2aa00000 0x0 0x40000>;
289 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
290 <0x0f>; /* TX_HCHAN */
291 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
292 <0x0b>; /* RX_HCHAN */
293 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
301 reg = <0x0 0x46000000 0x0 0x200000>;
303 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
309 dmas = <&mcu_udmap 0xf000>,
310 <&mcu_udmap 0xf001>,
311 <&mcu_udmap 0xf002>,
312 <&mcu_udmap 0xf003>,
313 <&mcu_udmap 0xf004>,
314 <&mcu_udmap 0xf005>,
315 <&mcu_udmap 0xf006>,
316 <&mcu_udmap 0xf007>,
317 <&mcu_udmap 0x7000>;
324 #size-cells = <0>;
330 ti,syscon-efuse = <&mcu_conf 0x200>;
337 reg = <0x0 0xf00 0x0 0x100>;
339 #size-cells = <0>;
347 reg = <0x0 0x3d000 0x0 0x400>;