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12

/Linux-v5.10/Documentation/devicetree/bindings/timer/
Dingenic,tcu.yaml31 pattern: "^timer@[0-9a-f]+$"
104 minimum: 0x00
105 maximum: 0xff
106 default: 0xfc
230 reg = <0x10002000 0x1000>;
233 ranges = <0x0 0x10002000 0x1000>;
248 watchdog: watchdog@0 {
250 reg = <0x0 0xc>;
258 reg = <0x40 0x80>;
276 reg = <0xe0 0x20>;
/Linux-v5.10/arch/mips/boot/dts/ingenic/
Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/Linux-v5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt6797.c18 * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
19 * iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
24 PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
28 PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
32 PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
36 PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
55 .gpio_m = 0,
/Linux-v5.10/arch/arm/boot/dts/
Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
76 offset = <0x08>;
77 mask = <0x01>;
78 label = "versatile:0";
[all …]
Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
118 #clock-cells = <0>;
[all …]
Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
81 #clock-cells = <0>;
89 #clock-cells = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
113 pclk: pclk@0 {
114 #clock-cells = <0>;
[all …]
Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
Darm-realview-pb11mp.dts45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
53 #size-cells = <0>;
56 MP11_0: cpu@0 {
59 reg = <0>;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
97 reg = <0x1f002000 0x1000>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt6797.txt46 Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
54 are from 0 to 15.
57 are from 0 to 63.
58 - mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
60 - mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
67 reg = <0 0x10005000 0 0x1000>,
68 <0 0x10002000 0 0x400>,
69 <0 0x10002400 0 0x400>,
70 <0 0x10002800 0 0x400>,
71 <0 0x10002C00 0 0x400>;
/Linux-v5.10/arch/arm/mach-mediatek/
Dplatsmp.c17 #define MTK_SMP_REG_SIZE 0x1000
27 0x80002000, 0x3fc,
28 { 0x534c4131, 0x4c415332, 0x41534c33 },
29 { 0x3f8, 0x3f8, 0x3f8 },
33 0x10002000, 0x34,
34 { 0x534c4131, 0x4c415332, 0x41534c33 },
35 { 0x38, 0x3c, 0x40 },
39 0x10202000, 0x34,
40 { 0x534c4131, 0x4c415332, 0x41534c33 },
41 { 0x38, 0x3c, 0x40 },
[all …]
/Linux-v5.10/arch/mips/include/asm/mach-ralink/
Drt3883.h13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
[all …]
/Linux-v5.10/arch/arm64/boot/dts/mediatek/
Dmt6797.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]
Dmt7622.dtsi69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
88 reg = <0x0 0x1>;
103 #clock-cells = <0>;
108 #clock-cells = <0>;
132 reg = <0 0x43000000 0 0x30000>;
142 thermal-sensors = <&thermal 0>;
208 reg = <0 0x10000000 0 0x1000>;
215 reg = <0 0x10001000 0 0x250>;
[all …]
/Linux-v5.10/arch/powerpc/boot/dts/
Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/ice/
Dice_flow.c34 ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_TCP, 0, sizeof(__be16)),
38 ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP, 0, sizeof(__be16)),
42 ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_SCTP, 0, sizeof(__be16)),
56 0x1DC00000, 0x04000800, 0x00000000, 0x00000000,
57 0x00000000, 0x00000000, 0x00000000, 0x00000000,
58 0x00000000, 0x00000000, 0x00000000, 0x00000000,
59 0x00000000, 0x00000000, 0x00000000, 0x00000000,
60 0x00000000, 0x00000000, 0x00000000, 0x00000000,
61 0x00000000, 0x00000000, 0x00000000, 0x00000000,
62 0x00000000, 0x00000000, 0x00000000, 0x00000000,
[all …]
/Linux-v5.10/arch/mips/include/asm/mach-au1x00/
Dau1000.h105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
[all …]

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