Lines Matching +full:0 +full:x10002000

44 		/* 128 MiB memory @ 0x0 */
45 		reg = <0x00000000 0x08000000>;
66 		#clock-cells = <0>;
72 		#clock-cells = <0>;
78 		#clock-cells = <0>;
86 		#clock-cells = <0>;
94 		#clock-cells = <0>;
102 		#clock-cells = <0>;
110 		#clock-cells = <0>;
118 		#clock-cells = <0>;
126 	pclk: pclk@0 {
127 		#clock-cells = <0>;
129 		clock-frequency = <0>;
135 		reg = <0x40000000 0x04000000>;
145 		reg = <0x44000000 0x04000000>;
155 		reg = <0x4e000000 0x10000>;
166 		reg = <0x4f000000 0x20000>;
173 		#size-cells = <0>;
177 			#size-cells = <0>;
179 			port@0 {
180 				reg = <0>;
222 			reg = <0x10000000 0x1000>;
226 				offset = <0x08>;
227 				mask = <0x01>;
228 				label = "versatile:0";
234 				offset = <0x08>;
235 				mask = <0x02>;
242 				offset = <0x08>;
243 				mask = <0x04>;
250 				offset = <0x08>;
251 				mask = <0x08>;
257 				offset = <0x08>;
258 				mask = <0x10>;
264 				offset = <0x08>;
265 				mask = <0x20>;
271 				offset = <0x08>;
272 				mask = <0x40>;
278 				offset = <0x08>;
279 				mask = <0x80>;
283 			oscclk0: osc0@0c {
285 				#clock-cells = <0>;
286 				lock-offset = <0x20>;
287 				vco-offset = <0x0C>;
292 				#clock-cells = <0>;
293 				lock-offset = <0x20>;
294 				vco-offset = <0x10>;
299 				#clock-cells = <0>;
300 				lock-offset = <0x20>;
301 				vco-offset = <0x14>;
306 				#clock-cells = <0>;
307 				lock-offset = <0x20>;
308 				vco-offset = <0x18>;
313 				#clock-cells = <0>;
314 				lock-offset = <0x20>;
315 				vco-offset = <0x1c>;
322 			reg = <0x10001000 0x1000>;
330 			assigned-clocks = <&sp810_syscon0 0>,
342 			#size-cells = <0>;
344 			reg = <0x10002000 0x1000>;
348 				reg = <0x68>;
354 			reg = <0x10009000 0x1000>;
361 			reg = <0x1000a000 0x1000>;
368 			reg = <0x1000b000 0x1000>;
375 			reg = <0x1000d000 0x1000>;
382 			reg = <0x1000f000 0x1000>;
390 			reg = <0x10010000 0x1000>;
398 			reg = <0x10011000 0x1000>;
399 			clocks = <&sp810_syscon0 0>,
409 			reg = <0x10012000 0x1000>;
420 			reg = <0x10013000 0x1000>;
431 			reg = <0x10014000 0x1000>;
442 			reg = <0x10015000 0x1000>;
453 			#size-cells = <0>;
455 			reg = <0x10016000 0x1000>;
460 			reg = <0x10017000 0x1000>;
467 			reg = <0x10018000 0x1000>;
474 			reg = <0x10019000 0x1000>;
481 			reg = <0x1001a000 0x1000>;
489 			assigned-clocks = <&sp810_syscon1 0>,
510 			reg = <0x10004000 0x1000>;
517 			reg = <0x10005000 0x1000>;
527 			cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
533 			reg = <0x10006000 0x1000>;
540 			reg = <0x10007000 0x1000>;
547 			reg = <0x1000c000 0x1000>;
562 			reg = <0x10020000 0x1000>;
572 					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;