Lines Matching +full:0 +full:x10002000
69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
88 reg = <0x0 0x1>;
103 #clock-cells = <0>;
108 #clock-cells = <0>;
132 reg = <0 0x43000000 0 0x30000>;
142 thermal-sensors = <&thermal 0>;
208 reg = <0 0x10000000 0 0x1000>;
215 reg = <0 0x10001000 0 0x250>;
228 reg = <0 0x10002000 0 0x1000>;
237 reg = <0 0x10006000 0 0x1000>;
249 reg = <0 0x10009000 0 0x1000>;
263 reg = <0 0x10200620 0 0x20>;
269 reg = <0 0x10206000 0 0x1000>;
274 reg = <0x198 0xc>;
281 reg = <0 0x10209000 0 0x1000>;
288 reg = <0 0x10210000 0 0x1000>;
295 reg = <0 0x1020f000 0 0x1000>;
302 reg = <0 0x10211000 0 0x1000>,
303 <0 0x10005000 0 0x1000>;
307 gpio-ranges = <&pio 0 0 103>;
317 reg = <0 0x10212000 0 0x800>;
323 reg = <0 0x10212800 0 0x200>;
334 reg = <0 0x10310000 0 0x1000>,
335 <0 0x10320000 0 0x1000>,
336 <0 0x10340000 0 0x2000>,
337 <0 0x10360000 0 0x2000>;
344 reg = <0 0x10390000 0 0x1000>;
345 ranges = <0 0 0x10390000 0x10000>;
350 reg = <0x1000 0x1000>;
356 reg = <0x4000 0x1000>;
362 reg = <0x5000 0x1000>;
367 reg = <0x9000 0x5000>;
378 reg = <0 0x11001000 0 0x1000>;
387 reg = <0 0x11002000 0 0x400>;
398 reg = <0 0x11003000 0 0x400>;
409 reg = <0 0x11004000 0 0x400>;
420 reg = <0 0x11005000 0 0x400>;
430 reg = <0 0x11006000 0 0x1000>;
447 reg = <0 0x11007000 0 0x90>,
448 <0 0x11000100 0 0x80>;
455 #size-cells = <0>;
461 reg = <0 0x11008000 0 0x90>,
462 <0 0x11000180 0 0x80>;
469 #size-cells = <0>;
475 reg = <0 0x11009000 0 0x90>,
476 <0 0x11000200 0 0x80>;
483 #size-cells = <0>;
489 reg = <0 0x1100a000 0 0x100>;
496 #size-cells = <0>;
503 reg = <0 0x1100b000 0 0x1000>;
504 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
519 reg = <0 0x1100c000 0 0x1000>;
537 reg = <0 0x1100D000 0 0x1000>;
544 #size-cells = <0>;
550 reg = <0 0x1100e000 0 0x1000>;
560 reg = <0 0x11014000 0 0xe0>;
565 #size-cells = <0>;
571 reg = <0 0x11016000 0 0x100>;
578 #size-cells = <0>;
585 reg = <0 0x11019000 0 0x400>;
595 reg = <0 0x11220000 0 0x2000>;
678 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
684 reg = <0 0x11230000 0 0x1000>;
696 reg = <0 0x11240000 0 0x1000>;
706 reg = <0 0x18000000 0 0x100000>;
718 reg = <0 0x1a000000 0 0x1000>;
726 reg = <0 0x1a0c0000 0 0x01000>,
727 <0 0x1a0c4700 0 0x0100>;
746 reg = <0 0x1a0c4000 0 0x700>;
753 reg = <0 0x1a0c4800 0 0x0100>;
760 reg = <0 0x1a0c4900 0 0x0700>;
767 reg = <0 0x1a0c5000 0 0x0100>;
777 reg = <0 0x1a100800 0 0x1000>;
785 reg = <0 0x1a140000 0 0x1000>,
786 <0 0x1a143000 0 0x1000>,
787 <0 0x1a145000 0 0x1000>;
809 bus-range = <0x00 0xff>;
810 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
813 pcie0: pcie@0,0 {
814 reg = <0x0000 0 0 0 0>;
821 interrupt-map-mask = <0 0 0 7>;
822 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
823 <0 0 0 2 &pcie_intc0 1>,
824 <0 0 0 3 &pcie_intc0 2>,
825 <0 0 0 4 &pcie_intc0 3>;
828 #address-cells = <0>;
833 pcie1: pcie@1,0 {
834 reg = <0x0800 0 0 0 0>;
841 interrupt-map-mask = <0 0 0 7>;
842 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
843 <0 0 0 2 &pcie_intc1 1>,
844 <0 0 0 3 &pcie_intc1 2>,
845 <0 0 0 4 &pcie_intc1 3>;
848 #address-cells = <0>;
857 reg = <0 0x1a200000 0 0x1100>;
868 ports-implemented = <0x1>;
886 reg = <0 0x1a243000 0 0x0100>;
896 reg = <0 0x1b000000 0 0x1000>;
903 reg = <0 0x1b007000 0 0x1000>;
915 reg = <0 0x1b100000 0 0x20000>;
938 #size-cells = <0>;
945 reg = <0 0x1b128000 0 0x3000>;