Lines Matching +full:0 +full:x10002000
24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
76 offset = <0x08>;
77 mask = <0x01>;
78 label = "versatile:0";
84 offset = <0x08>;
85 mask = <0x02>;
92 offset = <0x08>;
93 mask = <0x04>;
100 offset = <0x08>;
101 mask = <0x08>;
107 offset = <0x08>;
108 mask = <0x10>;
114 offset = <0x08>;
115 mask = <0x20>;
121 offset = <0x08>;
122 mask = <0x40>;
128 offset = <0x08>;
129 mask = <0x80>;
136 #clock-cells = <0>;
143 #clock-cells = <0>;
151 #clock-cells = <0>;
162 reg = <0x34000000 0x04000000>;
171 #size-cells = <0>;
173 reg = <0x10002000 0x1000>;
177 reg = <0x68>;
183 reg = <0x10010000 0x10000>;
189 reg = <0x10008000 0x1000>;
202 reg = <0x10140000 0x1000>;
203 clear-mask = <0xffffffff>;
204 valid-mask = <0xffffffff>;
211 reg = <0x10003000 0x1000>;
214 clear-mask = <0xffffffff>;
219 valid-mask = <0x0760031b>;
224 reg = <0x10130000 0x1000>;
232 reg = <0x101f1000 0x1000>;
240 reg = <0x101f2000 0x1000>;
248 reg = <0x101f3000 0x1000>;
256 reg = <0x10100000 0x1000>;
263 reg = <0x10110000 0x1000>;
270 reg = <0x10120000 0x1000>;
291 port@0 {
293 #size-cells = <0>;
295 clcd_pads_panel: endpoint@0 {
296 reg = <0>;
298 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
303 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
310 reg = <0x101e0000 0x1000>;
317 reg = <0x101e1000 0x1000>;
318 interrupts = <0>;
325 reg = <0x101e2000 0x1000>;
333 reg = <0x101e3000 0x1000>;
341 reg = <0x101e4000 0x1000>;
353 reg = <0x101e5000 0x1000>;
365 reg = <0x101e8000 0x1000>;
373 reg = <0x101f0000 0x1000>;
381 reg = <0x101f4000 0x1000>;
391 ranges = <0 0x10000000 0x10000>;
393 sysreg@0 {
395 reg = <0x00000 0x1000>;
397 panel: display@0 {
410 reg = <0x4000 0x1000>;
417 reg = <0x5000 0x1000>;
424 reg = <0x6000 0x1000>;
432 reg = <0x7000 0x1000>;