1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4/ {
5	model = "ARM Versatile AB";
6	compatible = "arm,versatile-ab";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	aliases {
12		serial0 = &uart0;
13		serial1 = &uart1;
14		serial2 = &uart2;
15		i2c0 = &i2c0;
16	};
17
18	chosen {
19		stdout-path = &uart0;
20	};
21
22	memory {
23		device_type = "memory";
24		reg = <0x0 0x08000000>;
25	};
26
27	xtal24mhz: xtal24mhz@24M {
28		#clock-cells = <0>;
29		compatible = "fixed-clock";
30		clock-frequency = <24000000>;
31	};
32
33	bridge {
34		compatible = "ti,ths8134b", "ti,ths8134";
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		ports {
39			#address-cells = <1>;
40			#size-cells = <0>;
41
42			port@0 {
43				reg = <0>;
44
45				vga_bridge_in: endpoint {
46					remote-endpoint = <&clcd_pads_vga_dac>;
47				};
48			};
49
50			port@1 {
51				reg = <1>;
52
53				vga_bridge_out: endpoint {
54					remote-endpoint = <&vga_con_in>;
55				};
56			};
57		};
58	};
59
60	vga {
61		compatible = "vga-connector";
62
63		port {
64			vga_con_in: endpoint {
65				remote-endpoint = <&vga_bridge_out>;
66			};
67		};
68	};
69
70	core-module@10000000 {
71		compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
72		reg = <0x10000000 0x200>;
73
74		led@08.0 {
75			compatible = "register-bit-led";
76			offset = <0x08>;
77			mask = <0x01>;
78			label = "versatile:0";
79			linux,default-trigger = "heartbeat";
80			default-state = "on";
81		};
82		led@08.1 {
83			compatible = "register-bit-led";
84			offset = <0x08>;
85			mask = <0x02>;
86			label = "versatile:1";
87			linux,default-trigger = "mmc0";
88			default-state = "off";
89		};
90		led@08.2 {
91			compatible = "register-bit-led";
92			offset = <0x08>;
93			mask = <0x04>;
94			label = "versatile:2";
95			linux,default-trigger = "cpu0";
96			default-state = "off";
97		};
98		led@08.3 {
99			compatible = "register-bit-led";
100			offset = <0x08>;
101			mask = <0x08>;
102			label = "versatile:3";
103			default-state = "off";
104		};
105		led@08.4 {
106			compatible = "register-bit-led";
107			offset = <0x08>;
108			mask = <0x10>;
109			label = "versatile:4";
110			default-state = "off";
111		};
112		led@08.5 {
113			compatible = "register-bit-led";
114			offset = <0x08>;
115			mask = <0x20>;
116			label = "versatile:5";
117			default-state = "off";
118		};
119		led@08.6 {
120			compatible = "register-bit-led";
121			offset = <0x08>;
122			mask = <0x40>;
123			label = "versatile:6";
124			default-state = "off";
125		};
126		led@08.7 {
127			compatible = "register-bit-led";
128			offset = <0x08>;
129			mask = <0x80>;
130			label = "versatile:7";
131			default-state = "off";
132		};
133
134		/* OSC1 on AB, OSC4 on PB */
135		osc1: cm_aux_osc@24M {
136			#clock-cells = <0>;
137			compatible = "arm,versatile-cm-auxosc";
138			clocks = <&xtal24mhz>;
139		};
140
141		/* The timer clock is the 24 MHz oscillator divided to 1MHz */
142		timclk: timclk@1M {
143			#clock-cells = <0>;
144			compatible = "fixed-factor-clock";
145			clock-div = <24>;
146			clock-mult = <1>;
147			clocks = <&xtal24mhz>;
148		};
149
150		pclk: pclk@24M {
151			#clock-cells = <0>;
152			compatible = "fixed-factor-clock";
153			clock-div = <1>;
154			clock-mult = <1>;
155			clocks = <&xtal24mhz>;
156		};
157	};
158
159	flash@34000000 {
160		/* 64 MiB NOR flash in non-interleaved chips */
161		compatible = "arm,versatile-flash", "cfi-flash";
162		reg = <0x34000000 0x04000000>;
163		bank-width = <4>;
164		partitions {
165			compatible = "arm,arm-firmware-suite";
166		};
167	};
168
169	i2c0: i2c@10002000 {
170		#address-cells = <1>;
171		#size-cells = <0>;
172		compatible = "arm,versatile-i2c";
173		reg = <0x10002000 0x1000>;
174
175		rtc@68 {
176			compatible = "dallas,ds1338";
177			reg = <0x68>;
178		};
179	};
180
181	net@10010000 {
182		compatible = "smsc,lan91c111";
183		reg = <0x10010000 0x10000>;
184		interrupts = <25>;
185	};
186
187	lcd@10008000 {
188		compatible = "arm,versatile-lcd";
189		reg = <0x10008000 0x1000>;
190	};
191
192	amba {
193		compatible = "simple-bus";
194		#address-cells = <1>;
195		#size-cells = <1>;
196		ranges;
197
198		vic: intc@10140000 {
199			compatible = "arm,versatile-vic";
200			interrupt-controller;
201			#interrupt-cells = <1>;
202			reg = <0x10140000 0x1000>;
203			clear-mask = <0xffffffff>;
204			valid-mask = <0xffffffff>;
205		};
206
207		sic: intc@10003000 {
208			compatible = "arm,versatile-sic";
209			interrupt-controller;
210			#interrupt-cells = <1>;
211			reg = <0x10003000 0x1000>;
212			interrupt-parent = <&vic>;
213			interrupts = <31>; /* Cascaded to vic */
214			clear-mask = <0xffffffff>;
215			/*
216			 * Valid interrupt lines mask according to
217			 * table 4-36 page 4-50 of ARM DUI 0225D
218			 */
219			valid-mask = <0x0760031b>;
220		};
221
222		dma@10130000 {
223			compatible = "arm,pl081", "arm,primecell";
224			reg = <0x10130000 0x1000>;
225			interrupts = <17>;
226			clocks = <&pclk>;
227			clock-names = "apb_pclk";
228		};
229
230		uart0: uart@101f1000 {
231			compatible = "arm,pl011", "arm,primecell";
232			reg = <0x101f1000 0x1000>;
233			interrupts = <12>;
234			clocks = <&xtal24mhz>, <&pclk>;
235			clock-names = "uartclk", "apb_pclk";
236		};
237
238		uart1: uart@101f2000 {
239			compatible = "arm,pl011", "arm,primecell";
240			reg = <0x101f2000 0x1000>;
241			interrupts = <13>;
242			clocks = <&xtal24mhz>, <&pclk>;
243			clock-names = "uartclk", "apb_pclk";
244		};
245
246		uart2: uart@101f3000 {
247			compatible = "arm,pl011", "arm,primecell";
248			reg = <0x101f3000 0x1000>;
249			interrupts = <14>;
250			clocks = <&xtal24mhz>, <&pclk>;
251			clock-names = "uartclk", "apb_pclk";
252		};
253
254		smc@10100000 {
255			compatible = "arm,primecell";
256			reg = <0x10100000 0x1000>;
257			clocks = <&pclk>;
258			clock-names = "apb_pclk";
259		};
260
261		mpmc@10110000 {
262			compatible = "arm,primecell";
263			reg = <0x10110000 0x1000>;
264			clocks = <&pclk>;
265			clock-names = "apb_pclk";
266		};
267
268		display@10120000 {
269			compatible = "arm,pl110", "arm,primecell";
270			reg = <0x10120000 0x1000>;
271			interrupts = <16>;
272			clocks = <&osc1>, <&pclk>;
273			clock-names = "clcdclk", "apb_pclk";
274			/* 800x600 16bpp @ 36MHz works fine */
275			max-memory-bandwidth = <54000000>;
276
277			/*
278			 * This port is routed through a PLD (Programmable
279			 * Logic Device) that routes the output from the CLCD
280			 * (after transformations) to the VGA DAC and also an
281			 * external panel connector. The PLD is essential for
282			 * supporting RGB565/BGR565.
283			 *
284			 * The signals from the port thus reaches two endpoints.
285			 * The PLD is managed through a few special bits in the
286			 * FPGA "sysreg".
287			 *
288			 * This arrangement can be clearly seen in
289			 * ARM DUI 0225D, page 3-41, figure 3-19.
290			 */
291			port@0 {
292				#address-cells = <1>;
293				#size-cells = <0>;
294
295				clcd_pads_panel: endpoint@0 {
296					reg = <0>;
297					remote-endpoint = <&panel_in>;
298					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
299				};
300				clcd_pads_vga_dac: endpoint@1 {
301					reg = <1>;
302					remote-endpoint = <&vga_bridge_in>;
303					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
304				};
305			};
306		};
307
308		sctl@101e0000 {
309			compatible = "arm,primecell";
310			reg = <0x101e0000 0x1000>;
311			clocks = <&pclk>;
312			clock-names = "apb_pclk";
313		};
314
315		watchdog@101e1000 {
316			compatible = "arm,primecell";
317			reg = <0x101e1000 0x1000>;
318			interrupts = <0>;
319			clocks = <&pclk>;
320			clock-names = "apb_pclk";
321		};
322
323		timer@101e2000 {
324			compatible = "arm,sp804", "arm,primecell";
325			reg = <0x101e2000 0x1000>;
326			interrupts = <4>;
327			clocks = <&timclk>, <&timclk>, <&pclk>;
328			clock-names = "timer0", "timer1", "apb_pclk";
329		};
330
331		timer@101e3000 {
332			compatible = "arm,sp804", "arm,primecell";
333			reg = <0x101e3000 0x1000>;
334			interrupts = <5>;
335			clocks = <&timclk>, <&timclk>, <&pclk>;
336			clock-names = "timer0", "timer1", "apb_pclk";
337		};
338
339		gpio0: gpio@101e4000 {
340			compatible = "arm,pl061", "arm,primecell";
341			reg = <0x101e4000 0x1000>;
342			gpio-controller;
343			interrupts = <6>;
344			#gpio-cells = <2>;
345			interrupt-controller;
346			#interrupt-cells = <2>;
347			clocks = <&pclk>;
348			clock-names = "apb_pclk";
349		};
350
351		gpio1: gpio@101e5000 {
352			compatible = "arm,pl061", "arm,primecell";
353			reg = <0x101e5000 0x1000>;
354			interrupts = <7>;
355			gpio-controller;
356			#gpio-cells = <2>;
357			interrupt-controller;
358			#interrupt-cells = <2>;
359			clocks = <&pclk>;
360			clock-names = "apb_pclk";
361		};
362
363		rtc@101e8000 {
364			compatible = "arm,pl030", "arm,primecell";
365			reg = <0x101e8000 0x1000>;
366			interrupts = <10>;
367			clocks = <&pclk>;
368			clock-names = "apb_pclk";
369		};
370
371		sci@101f0000 {
372			compatible = "arm,primecell";
373			reg = <0x101f0000 0x1000>;
374			interrupts = <15>;
375			clocks = <&pclk>;
376			clock-names = "apb_pclk";
377		};
378
379		spi@101f4000 {
380			compatible = "arm,pl022", "arm,primecell";
381			reg = <0x101f4000 0x1000>;
382			interrupts = <11>;
383			clocks = <&xtal24mhz>, <&pclk>;
384			clock-names = "SSPCLK", "apb_pclk";
385		};
386
387		fpga {
388			compatible = "arm,versatile-fpga", "simple-bus";
389			#address-cells = <1>;
390			#size-cells = <1>;
391			ranges = <0 0x10000000 0x10000>;
392
393			sysreg@0 {
394				compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
395				reg = <0x00000 0x1000>;
396
397				panel: display@0 {
398					compatible = "arm,versatile-tft-panel";
399
400					port {
401						panel_in: endpoint {
402							remote-endpoint = <&clcd_pads_panel>;
403						};
404					};
405				};
406			};
407
408			aaci@4000 {
409				compatible = "arm,primecell";
410				reg = <0x4000 0x1000>;
411				interrupts = <24>;
412				clocks = <&pclk>;
413				clock-names = "apb_pclk";
414			};
415			mmc@5000 {
416				compatible = "arm,pl180", "arm,primecell";
417				reg = <0x5000 0x1000>;
418				interrupts-extended = <&vic 22 &sic 1>;
419				clocks = <&xtal24mhz>, <&pclk>;
420				clock-names = "mclk", "apb_pclk";
421			};
422			kmi@6000 {
423				compatible = "arm,pl050", "arm,primecell";
424				reg = <0x6000 0x1000>;
425				interrupt-parent = <&sic>;
426				interrupts = <3>;
427				clocks = <&xtal24mhz>, <&pclk>;
428				clock-names = "KMIREFCLK", "apb_pclk";
429			};
430			kmi@7000 {
431				compatible = "arm,pl050", "arm,primecell";
432				reg = <0x7000 0x1000>;
433				interrupt-parent = <&sic>;
434				interrupts = <4>;
435				clocks = <&xtal24mhz>, <&pclk>;
436				clock-names = "KMIREFCLK", "apb_pclk";
437			};
438		};
439	};
440};
441