1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/ingenic,tcu.h>
3#include <dt-bindings/clock/x1000-cgu.h>
4#include <dt-bindings/dma/x1000-dma.h>
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <1>;
9	compatible = "ingenic,x1000", "ingenic,x1000e";
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18			reg = <0>;
19
20			clocks = <&cgu X1000_CLK_CPU>;
21			clock-names = "cpu";
22		};
23	};
24
25	cpuintc: interrupt-controller {
26		#address-cells = <0>;
27		#interrupt-cells = <1>;
28		interrupt-controller;
29		compatible = "mti,cpu-interrupt-controller";
30	};
31
32	intc: interrupt-controller@10001000 {
33		compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
34		reg = <0x10001000 0x50>;
35
36		interrupt-controller;
37		#interrupt-cells = <1>;
38
39		interrupt-parent = <&cpuintc>;
40		interrupts = <2>;
41	};
42
43	exclk: ext {
44		compatible = "fixed-clock";
45		#clock-cells = <0>;
46	};
47
48	rtclk: rtc {
49		compatible = "fixed-clock";
50		#clock-cells = <0>;
51		clock-frequency = <32768>;
52	};
53
54	cgu: x1000-cgu@10000000 {
55		compatible = "ingenic,x1000-cgu";
56		reg = <0x10000000 0x100>;
57
58		#clock-cells = <1>;
59
60		clocks = <&exclk>, <&rtclk>;
61		clock-names = "ext", "rtc";
62	};
63
64	tcu: timer@10002000 {
65		compatible = "ingenic,x1000-tcu", "simple-mfd";
66		reg = <0x10002000 0x1000>;
67		#address-cells = <1>;
68		#size-cells = <1>;
69		ranges = <0x0 0x10002000 0x1000>;
70
71		#clock-cells = <1>;
72
73		clocks = <&cgu X1000_CLK_RTCLK>,
74			 <&cgu X1000_CLK_EXCLK>,
75			 <&cgu X1000_CLK_PCLK>;
76		clock-names = "rtc", "ext", "pclk";
77
78		interrupt-controller;
79		#interrupt-cells = <1>;
80
81		interrupt-parent = <&intc>;
82		interrupts = <27 26 25>;
83
84		wdt: watchdog@0 {
85			compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog";
86			reg = <0x0 0x10>;
87
88			clocks = <&tcu TCU_CLK_WDT>;
89			clock-names = "wdt";
90		};
91	};
92
93	rtc: rtc@10003000 {
94		compatible = "ingenic,x1000-rtc", "ingenic,jz4780-rtc";
95		reg = <0x10003000 0x4c>;
96
97		interrupt-parent = <&intc>;
98		interrupts = <32>;
99
100		clocks = <&cgu X1000_CLK_RTCLK>;
101		clock-names = "rtc";
102	};
103
104	pinctrl: pin-controller@10010000 {
105		compatible = "ingenic,x1000-pinctrl";
106		reg = <0x10010000 0x800>;
107		#address-cells = <1>;
108		#size-cells = <0>;
109
110		gpa: gpio@0 {
111			compatible = "ingenic,x1000-gpio";
112			reg = <0>;
113
114			gpio-controller;
115			gpio-ranges = <&pinctrl 0 0 32>;
116			#gpio-cells = <2>;
117
118			interrupt-controller;
119			#interrupt-cells = <2>;
120
121			interrupt-parent = <&intc>;
122			interrupts = <17>;
123		};
124
125		gpb: gpio@1 {
126			compatible = "ingenic,x1000-gpio";
127			reg = <1>;
128
129			gpio-controller;
130			gpio-ranges = <&pinctrl 0 32 32>;
131			#gpio-cells = <2>;
132
133			interrupt-controller;
134			#interrupt-cells = <2>;
135
136			interrupt-parent = <&intc>;
137			interrupts = <16>;
138		};
139
140		gpc: gpio@2 {
141			compatible = "ingenic,x1000-gpio";
142			reg = <2>;
143
144			gpio-controller;
145			gpio-ranges = <&pinctrl 0 64 32>;
146			#gpio-cells = <2>;
147
148			interrupt-controller;
149			#interrupt-cells = <2>;
150
151			interrupt-parent = <&intc>;
152			interrupts = <15>;
153		};
154
155		gpd: gpio@3 {
156			compatible = "ingenic,x1000-gpio";
157			reg = <3>;
158
159			gpio-controller;
160			gpio-ranges = <&pinctrl 0 96 32>;
161			#gpio-cells = <2>;
162
163			interrupt-controller;
164			#interrupt-cells = <2>;
165
166			interrupt-parent = <&intc>;
167			interrupts = <14>;
168		};
169	};
170
171	uart0: serial@10030000 {
172		compatible = "ingenic,x1000-uart";
173		reg = <0x10030000 0x100>;
174
175		interrupt-parent = <&intc>;
176		interrupts = <51>;
177
178		clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
179		clock-names = "baud", "module";
180
181		status = "disabled";
182	};
183
184	uart1: serial@10031000 {
185		compatible = "ingenic,x1000-uart";
186		reg = <0x10031000 0x100>;
187
188		interrupt-parent = <&intc>;
189		interrupts = <50>;
190
191		clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
192		clock-names = "baud", "module";
193
194		status = "disabled";
195	};
196
197	uart2: serial@10032000 {
198		compatible = "ingenic,x1000-uart";
199		reg = <0x10032000 0x100>;
200
201		interrupt-parent = <&intc>;
202		interrupts = <49>;
203
204		clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
205		clock-names = "baud", "module";
206
207		status = "disabled";
208	};
209
210	i2c0: i2c-controller@10050000 {
211		compatible = "ingenic,x1000-i2c";
212		reg = <0x10050000 0x1000>;
213		#address-cells = <1>;
214		#size-cells = <0>;
215
216		interrupt-parent = <&intc>;
217		interrupts = <60>;
218
219		clocks = <&cgu X1000_CLK_I2C0>;
220
221		status = "disabled";
222	};
223
224	i2c1: i2c-controller@10051000 {
225		compatible = "ingenic,x1000-i2c";
226		reg = <0x10051000 0x1000>;
227		#address-cells = <1>;
228		#size-cells = <0>;
229
230		interrupt-parent = <&intc>;
231		interrupts = <59>;
232
233		clocks = <&cgu X1000_CLK_I2C1>;
234
235		status = "disabled";
236	};
237
238	i2c2: i2c-controller@10052000 {
239		compatible = "ingenic,x1000-i2c";
240		reg = <0x10052000 0x1000>;
241		#address-cells = <1>;
242		#size-cells = <0>;
243
244		interrupt-parent = <&intc>;
245		interrupts = <58>;
246
247		clocks = <&cgu X1000_CLK_I2C2>;
248
249		status = "disabled";
250	};
251
252	pdma: dma-controller@13420000 {
253		compatible = "ingenic,x1000-dma";
254		reg = <0x13420000 0x400>, <0x13421000 0x40>;
255		#dma-cells = <2>;
256
257		interrupt-parent = <&intc>;
258		interrupts = <10>;
259
260		clocks = <&cgu X1000_CLK_PDMA>;
261	};
262
263	msc0: mmc@13450000 {
264		compatible = "ingenic,x1000-mmc";
265		reg = <0x13450000 0x1000>;
266
267		interrupt-parent = <&intc>;
268		interrupts = <37>;
269
270		clocks = <&cgu X1000_CLK_MSC0>;
271		clock-names = "mmc";
272
273		cap-sd-highspeed;
274		cap-mmc-highspeed;
275		cap-sdio-irq;
276
277		dmas = <&pdma X1000_DMA_MSC0_RX 0xffffffff>,
278			   <&pdma X1000_DMA_MSC0_TX 0xffffffff>;
279		dma-names = "rx", "tx";
280
281		status = "disabled";
282	};
283
284	msc1: mmc@13460000 {
285		compatible = "ingenic,x1000-mmc";
286		reg = <0x13460000 0x1000>;
287
288		interrupt-parent = <&intc>;
289		interrupts = <36>;
290
291		clocks = <&cgu X1000_CLK_MSC1>;
292		clock-names = "mmc";
293
294		cap-sd-highspeed;
295		cap-mmc-highspeed;
296		cap-sdio-irq;
297
298		dmas = <&pdma X1000_DMA_MSC1_RX 0xffffffff>,
299			   <&pdma X1000_DMA_MSC1_TX 0xffffffff>;
300		dma-names = "rx", "tx";
301
302		status = "disabled";
303	};
304
305	mac: ethernet@134b0000 {
306		compatible = "ingenic,x1000-mac", "snps,dwmac";
307		reg = <0x134b0000 0x2000>;
308
309		interrupt-parent = <&intc>;
310		interrupts = <55>;
311		interrupt-names = "macirq";
312
313		clocks = <&cgu X1000_CLK_MAC>;
314		clock-names = "stmmaceth";
315
316		status = "disabled";
317
318		mdio: mdio {
319			compatible = "snps,dwmac-mdio";
320			#address-cells = <1>;
321			#size-cells = <0>;
322
323			status = "disabled";
324		};
325	};
326};
327