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Searched +full:- +full:refclk (Results 1 – 25 of 250) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dpllgt215.c36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
43 lM = max(lM, (int)info->vco1.min_m); in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
45 hM = min(hM, (int)info->vco1.max_m); in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
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/Linux-v5.10/Documentation/devicetree/bindings/usb/
Dusb3503.txt1 SMSC USB3503 High-Speed Hub Controller
4 - compatible: Should be "smsc,usb3503" or "smsc,usb3503a".
7 - reg: Specifies the i2c slave address, it is required and should be 0x08
9 - connect-gpios: Should specify GPIO for connect.
10 - disabled-ports: Should specify the ports unused.
14 - intn-gpios: Should specify GPIO for interrupt.
15 - reset-gpios: Should specify GPIO for reset.
16 - initial-mode: Should specify initial mode.
18 - refclk: Clock used for driving REFCLK signal (optional, if not provided
22 clock-names in order to assign it
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Docteon-usb.txt7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
33 The main node must have one child node which describes the built-in
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Ddwc3-cavium.txt4 - compatible: Should contain "cavium,octeon-7130-usb-uctl"
13 compatible = "cavium,octeon-7130-usb-uctl";
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
19 refclk-type-ss = "dlmc_ref_clk0";
20 refclk-type-hs = "dlmc_ref_clk0";
23 compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3";
25 interrupt-parent = <0x00000010>;
/Linux-v5.10/drivers/phy/ti/
Dphy-dm816x-usb.c56 struct clk *refclk; member
64 otg->host = host; in dm816x_usb_phy_set_host()
66 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_host()
74 otg->gadget = gadget; in dm816x_usb_phy_set_peripheral()
76 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_peripheral()
86 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
87 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
90 regmap_update_bits(phy->syscon, phy->usb_ctrl, in dm816x_usb_phy_init()
95 regmap_read(phy->syscon, phy->usb_ctrl, &val); in dm816x_usb_phy_init()
97 dev_info(phy->dev, in dm816x_usb_phy_init()
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Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
171 struct clk *refclk; member
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
241 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
266 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
302 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
304 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
306 for (; dpll_map->rate; dpll_map++) { in ti_pipe3_get_dpll_params()
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/Linux-v5.10/drivers/gpu/drm/gma500/
Dgma_display.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2006-2011 Intel Corporation
44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
91 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
92 extern void gma_clock(int refclk, struct gma_clock_t *clock);
97 struct drm_crtc *crtc, int target, int refclk,
Doaktrail_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
38 int refclk, struct gma_clock_t *best_clock);
42 int refclk, struct gma_clock_t *best_clock);
81 int refclk) in mrst_limit() argument
84 struct drm_device *dev = crtc->dev; in mrst_limit()
85 struct drm_psb_private *dev_priv = dev->dev_private; in mrst_limit()
89 switch (dev_priv->core_freq) { in mrst_limit()
104 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); in mrst_limit()
110 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
111 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
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Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
24 int refclk, struct gma_clock_t *best_clock);
56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
117 ret__ = -ETIMEDOUT; \
216 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
287 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
289 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
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/Linux-v5.10/drivers/net/ethernet/arc/
Demac_rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
32 struct clk *refclk; member
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
77 .compatible = "rockchip,rk3036-emac",
81 .compatible = "rockchip,rk3066-emac",
85 .compatible = "rockchip,rk3188-emac",
95 struct device *dev = &pdev->dev; in emac_rockchip_probe()
103 if (!pdev->dev.of_node) in emac_rockchip_probe()
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/Linux-v5.10/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
103 /* Refclk selection parameters */
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
184 * struct xpsgtr_phy - representation of a lane
191 * @refclk: reference clock index
200 unsigned int refclk; member
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/Linux-v5.10/arch/mips/bcm63xx/
Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
389 return clk->rate; in clk_get_rate()
409 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
410 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
426 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
427 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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/Linux-v5.10/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
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/Linux-v5.10/drivers/net/phy/
Dsmsc.c1 // SPDX-License-Identifier: GPL-2.0+
25 /* Vendor-specific PHY Definitions */
48 struct clk *refclk; member
53 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_intr()
57 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in smsc_phy_config_intr()
59 if (priv->energy_enable) in smsc_phy_config_intr()
77 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_init()
80 if (!priv->energy_enable) in smsc_phy_config_init()
126 switch (phydev->mdix_ctrl) { in lan87xx_config_aneg()
151 phydev->mdix = phydev->mdix_ctrl; in lan87xx_config_aneg()
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/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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/Linux-v5.10/drivers/net/ethernet/ti/
Dcpts.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
32 #define cpts_read32(c, r) readl_relaxed(&c->reg->r)
33 #define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r)
37 return (event->high >> PORT_NUMBER_SHIFT) & PORT_NUMBER_MASK; in cpts_event_port()
42 return time_after(jiffies, event->tmo); in event_expired()
47 return (event->high >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; in event_type()
60 return -1; in cpts_fifo_pop()
69 list_for_each_safe(this, next, &cpts->events) { in cpts_purge_events()
72 list_del_init(&event->list); in cpts_purge_events()
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/Linux-v5.10/arch/arm/boot/dts/
Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
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Dkeystone-k2hk-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2hk.dtsi"
13 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
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Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
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Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dmarvell,berlin.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 clock node should be a sub-node of the chip controller node. Marvell Berlin2
13 - compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
14 - #clock-cells: must be 1
15 - clocks: must be the input parent clock phandle
16 - clock-names: name of the input parent clock
17 Allowed clock-names for the reference clocks are
18 "refclk" for the SoCs oscillator input on all SoCs,
19 and SoC-specific input clocks for
26 compatible = "marvell,berlin2q-clk";
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/Linux-v5.10/drivers/clk/berlin/
Dbg2.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/berlin2.h>
19 #include "berlin2-avpll.h"
20 #include "berlin2-div.h"
21 #include "berlin2-pll.h"
77 * - audio_fast_pll is unknown
78 * - audiohd_pll is unknown
79 * - video0_pll is unknown
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Dbg2q.c1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/berlin2q.h>
19 #include "berlin2-div.h"
20 #include "berlin2-pll.h"
45 REFCLK, enumerator
52 [REFCLK] = "refclk",
291 clk_data->num = MAX_CLKS; in berlin2q_clock_setup()
292 hws = clk_data->hws; in berlin2q_clock_setup()
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/Linux-v5.10/sound/soc/meson/
Daxg-spdifin.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 #include <sound/soc-dai.h>
55 struct clk *refclk; member
80 regmap_read(priv->map, SPDIFIN_STAT0, &stat); in axg_spdifin_get_rate()
90 rate = priv->conf->mode_rates[mode]; in axg_spdifin_get_rate()
101 regmap_update_bits(priv->map, SPDIFIN_CTRL0, in axg_spdifin_prepare()
107 regmap_update_bits(priv->map, SPDIFIN_CTRL0, in axg_spdifin_prepare()
109 regmap_update_bits(priv->map, SPDIFIN_CTRL0, in axg_spdifin_prepare()
121 ret = clk_prepare_enable(priv->refclk); in axg_spdifin_startup()
123 dev_err(dai->dev, in axg_spdifin_startup()
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/Linux-v5.10/drivers/phy/
Dphy-pistachio-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <dt-bindings/phy/phy-pistachio-usb.h>
38 unsigned int refclk; member
59 ret = clk_prepare_enable(p_phy->phy_clk); in pistachio_usb_phy_power_on()
61 dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret); in pistachio_usb_phy_power_on()
65 regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL, in pistachio_usb_phy_power_on()
68 p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT); in pistachio_usb_phy_power_on()
70 rate = clk_get_rate(p_phy->phy_clk); in pistachio_usb_phy_power_on()
71 if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) { in pistachio_usb_phy_power_on()
72 dev_err(p_phy->dev, "Unsupported rate for XO crystal: %ld\n", in pistachio_usb_phy_power_on()
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