Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
171 struct clk *refclk; member
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
241 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
266 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
302 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
304 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
306 for (; dpll_map->rate; dpll_map++) { in ti_pipe3_get_dpll_params()
307 if (rate == dpll_map->rate) in ti_pipe3_get_dpll_params()
308 return &dpll_map->params; in ti_pipe3_get_dpll_params()
311 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); in ti_pipe3_get_dpll_params()
324 if (!phy->phy_power_syscon) { in ti_pipe3_power_off()
325 omap_control_phy_power(phy->control_dev, 0); in ti_pipe3_power_off()
329 ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_off()
344 if (!phy->phy_power_syscon) { in ti_pipe3_power_on()
345 omap_control_phy_power(phy->control_dev, 1); in ti_pipe3_power_on()
349 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_power_on()
351 dev_err(phy->dev, "Invalid clock rate\n"); in ti_pipe3_power_on()
352 return -EINVAL; in ti_pipe3_power_on()
357 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_on()
364 if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) { in ti_pipe3_power_on()
371 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_on()
376 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_on()
380 if (phy->mode == PIPE3_MODE_PCIE) in ti_pipe3_power_on()
394 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_dpll_wait_lock()
399 dev_err(phy->dev, "DPLL failed to lock\n"); in ti_pipe3_dpll_wait_lock()
400 return -EBUSY; in ti_pipe3_dpll_wait_lock()
410 return -EINVAL; in ti_pipe3_dpll_program()
412 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in ti_pipe3_dpll_program()
414 val |= dpll_params->n << PLL_REGN_SHIFT; in ti_pipe3_dpll_program()
415 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in ti_pipe3_dpll_program()
417 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_pipe3_dpll_program()
419 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; in ti_pipe3_dpll_program()
420 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); in ti_pipe3_dpll_program()
422 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in ti_pipe3_dpll_program()
424 val |= dpll_params->m << PLL_REGM_SHIFT; in ti_pipe3_dpll_program()
425 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in ti_pipe3_dpll_program()
427 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); in ti_pipe3_dpll_program()
429 val |= dpll_params->mf << PLL_REGM_F_SHIFT; in ti_pipe3_dpll_program()
430 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); in ti_pipe3_dpll_program()
432 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); in ti_pipe3_dpll_program()
434 val |= dpll_params->sd << PLL_SD_SHIFT; in ti_pipe3_dpll_program()
435 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); in ti_pipe3_dpll_program()
437 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); in ti_pipe3_dpll_program()
445 struct pipe3_settings *s = &phy->settings; in ti_pipe3_calibrate()
447 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); in ti_pipe3_calibrate()
449 val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); in ti_pipe3_calibrate()
450 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); in ti_pipe3_calibrate()
452 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); in ti_pipe3_calibrate()
456 val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | in ti_pipe3_calibrate()
457 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT | in ti_pipe3_calibrate()
458 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT | in ti_pipe3_calibrate()
459 s->dig_lbw << MEM_CDR_LBW_SHIFT | in ti_pipe3_calibrate()
460 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT | in ti_pipe3_calibrate()
461 s->dig_stl << MEM_CDR_STL_SHIFT | in ti_pipe3_calibrate()
462 s->dig_thr << MEM_CDR_THR_SHIFT | in ti_pipe3_calibrate()
463 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT | in ti_pipe3_calibrate()
464 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT; in ti_pipe3_calibrate()
465 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); in ti_pipe3_calibrate()
467 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); in ti_pipe3_calibrate()
469 val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; in ti_pipe3_calibrate()
470 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); in ti_pipe3_calibrate()
472 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); in ti_pipe3_calibrate()
474 val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; in ti_pipe3_calibrate()
475 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); in ti_pipe3_calibrate()
477 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); in ti_pipe3_calibrate()
480 val |= s->eq_lev << MEM_EQLEV_SHIFT | in ti_pipe3_calibrate()
481 s->eq_ftc << MEM_EQFTC_SHIFT | in ti_pipe3_calibrate()
482 s->eq_ctl << MEM_EQCTL_SHIFT | in ti_pipe3_calibrate()
483 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT | in ti_pipe3_calibrate()
484 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT; in ti_pipe3_calibrate()
485 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); in ti_pipe3_calibrate()
487 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_calibrate()
488 val = ti_pipe3_readl(phy->phy_rx, in ti_pipe3_calibrate()
491 ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES, in ti_pipe3_calibrate()
506 * 18-1804. in ti_pipe3_init()
508 if (phy->mode == PIPE3_MODE_PCIE) { in ti_pipe3_init()
509 if (!phy->pcs_syscon) { in ti_pipe3_init()
510 omap_control_pcie_pcs(phy->control_dev, 0x96); in ti_pipe3_init()
515 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, in ti_pipe3_init()
521 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_pipe3_init()
524 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); in ti_pipe3_init()
528 /* SATA has issues if re-programmed when locked */ in ti_pipe3_init()
529 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_init()
530 if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) in ti_pipe3_init()
537 return -EINVAL; in ti_pipe3_init()
554 if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) in ti_pipe3_exit()
558 if (phy->mode != PIPE3_MODE_PCIE) { in ti_pipe3_exit()
560 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_pipe3_exit()
562 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); in ti_pipe3_exit()
568 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_exit()
574 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", in ti_pipe3_exit()
576 return -EBUSY; in ti_pipe3_exit()
581 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_exit()
582 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, in ti_pipe3_exit()
584 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, in ti_pipe3_exit()
605 struct device *dev = phy->dev; in ti_pipe3_get_clk()
607 phy->refclk = devm_clk_get(dev, "refclk"); in ti_pipe3_get_clk()
608 if (IS_ERR(phy->refclk)) { in ti_pipe3_get_clk()
609 dev_err(dev, "unable to get refclk\n"); in ti_pipe3_get_clk()
610 /* older DTBs have missing refclk in SATA PHY in ti_pipe3_get_clk()
613 if (phy->mode != PIPE3_MODE_SATA) in ti_pipe3_get_clk()
614 return PTR_ERR(phy->refclk); in ti_pipe3_get_clk()
617 if (phy->mode != PIPE3_MODE_SATA) { in ti_pipe3_get_clk()
618 phy->wkupclk = devm_clk_get(dev, "wkupclk"); in ti_pipe3_get_clk()
619 if (IS_ERR(phy->wkupclk)) { in ti_pipe3_get_clk()
621 return PTR_ERR(phy->wkupclk); in ti_pipe3_get_clk()
624 phy->wkupclk = ERR_PTR(-ENODEV); in ti_pipe3_get_clk()
627 if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) { in ti_pipe3_get_clk()
628 phy->sys_clk = devm_clk_get(dev, "sysclk"); in ti_pipe3_get_clk()
629 if (IS_ERR(phy->sys_clk)) { in ti_pipe3_get_clk()
631 return -EINVAL; in ti_pipe3_get_clk()
635 if (phy->mode == PIPE3_MODE_PCIE) { in ti_pipe3_get_clk()
650 clk = devm_clk_get(dev, "phy-div"); in ti_pipe3_get_clk()
652 dev_err(dev, "unable to get phy-div clk\n"); in ti_pipe3_get_clk()
657 phy->div_clk = devm_clk_get(dev, "div-clk"); in ti_pipe3_get_clk()
658 if (IS_ERR(phy->div_clk)) { in ti_pipe3_get_clk()
659 dev_err(dev, "unable to get div-clk\n"); in ti_pipe3_get_clk()
660 return PTR_ERR(phy->div_clk); in ti_pipe3_get_clk()
663 phy->div_clk = ERR_PTR(-ENODEV); in ti_pipe3_get_clk()
671 struct device *dev = phy->dev; in ti_pipe3_get_sysctrl()
672 struct device_node *node = dev->of_node; in ti_pipe3_get_sysctrl()
676 phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node, in ti_pipe3_get_sysctrl()
677 "syscon-phy-power"); in ti_pipe3_get_sysctrl()
678 if (IS_ERR(phy->phy_power_syscon)) { in ti_pipe3_get_sysctrl()
680 "can't get syscon-phy-power, using control device\n"); in ti_pipe3_get_sysctrl()
681 phy->phy_power_syscon = NULL; in ti_pipe3_get_sysctrl()
684 "syscon-phy-power", 1, in ti_pipe3_get_sysctrl()
685 &phy->power_reg)) { in ti_pipe3_get_sysctrl()
687 return -EINVAL; in ti_pipe3_get_sysctrl()
691 if (!phy->phy_power_syscon) { in ti_pipe3_get_sysctrl()
692 control_node = of_parse_phandle(node, "ctrl-module", 0); in ti_pipe3_get_sysctrl()
695 return -EINVAL; in ti_pipe3_get_sysctrl()
701 return -EINVAL; in ti_pipe3_get_sysctrl()
704 phy->control_dev = &control_pdev->dev; in ti_pipe3_get_sysctrl()
707 if (phy->mode == PIPE3_MODE_PCIE) { in ti_pipe3_get_sysctrl()
708 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node, in ti_pipe3_get_sysctrl()
709 "syscon-pcs"); in ti_pipe3_get_sysctrl()
710 if (IS_ERR(phy->pcs_syscon)) { in ti_pipe3_get_sysctrl()
712 "can't get syscon-pcs, using omap control\n"); in ti_pipe3_get_sysctrl()
713 phy->pcs_syscon = NULL; in ti_pipe3_get_sysctrl()
716 "syscon-pcs", 1, in ti_pipe3_get_sysctrl()
717 &phy->pcie_pcs_reg)) { in ti_pipe3_get_sysctrl()
720 return -EINVAL; in ti_pipe3_get_sysctrl()
725 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_get_sysctrl()
726 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node, in ti_pipe3_get_sysctrl()
727 "syscon-pllreset"); in ti_pipe3_get_sysctrl()
728 if (IS_ERR(phy->dpll_reset_syscon)) { in ti_pipe3_get_sysctrl()
730 "can't get syscon-pllreset, sata dpll won't idle\n"); in ti_pipe3_get_sysctrl()
731 phy->dpll_reset_syscon = NULL; in ti_pipe3_get_sysctrl()
734 "syscon-pllreset", 1, in ti_pipe3_get_sysctrl()
735 &phy->dpll_reset_reg)) { in ti_pipe3_get_sysctrl()
738 return -EINVAL; in ti_pipe3_get_sysctrl()
749 struct device *dev = phy->dev; in ti_pipe3_get_tx_rx_base()
754 phy->phy_rx = devm_ioremap_resource(dev, res); in ti_pipe3_get_tx_rx_base()
755 if (IS_ERR(phy->phy_rx)) in ti_pipe3_get_tx_rx_base()
756 return PTR_ERR(phy->phy_rx); in ti_pipe3_get_tx_rx_base()
760 phy->phy_tx = devm_ioremap_resource(dev, res); in ti_pipe3_get_tx_rx_base()
762 return PTR_ERR_OR_ZERO(phy->phy_tx); in ti_pipe3_get_tx_rx_base()
768 struct device *dev = phy->dev; in ti_pipe3_get_pll_base()
771 if (phy->mode == PIPE3_MODE_PCIE) in ti_pipe3_get_pll_base()
776 phy->pll_ctrl_base = devm_ioremap_resource(dev, res); in ti_pipe3_get_pll_base()
777 return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); in ti_pipe3_get_pll_base()
785 struct device *dev = &pdev->dev; in ti_pipe3_probe()
792 return -ENOMEM; in ti_pipe3_probe()
796 return -EINVAL; in ti_pipe3_probe()
798 data = (struct pipe3_data *)match->data; in ti_pipe3_probe()
801 return -EINVAL; in ti_pipe3_probe()
804 phy->dev = dev; in ti_pipe3_probe()
805 phy->mode = data->mode; in ti_pipe3_probe()
806 phy->dpll_map = data->dpll_map; in ti_pipe3_probe()
807 phy->settings = data->settings; in ti_pipe3_probe()
829 * Prevent auto-disable of refclk for SATA PHY due to Errata i783 in ti_pipe3_probe()
831 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_probe()
832 if (!IS_ERR(phy->refclk)) { in ti_pipe3_probe()
833 clk_prepare_enable(phy->refclk); in ti_pipe3_probe()
834 phy->sata_refclk_enabled = true; in ti_pipe3_probe()
854 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_remove()
855 clk_disable_unprepare(phy->refclk); in ti_pipe3_remove()
856 phy->sata_refclk_enabled = false; in ti_pipe3_remove()
858 pm_runtime_disable(&pdev->dev); in ti_pipe3_remove()
867 if (!IS_ERR(phy->refclk)) { in ti_pipe3_enable_clocks()
868 ret = clk_prepare_enable(phy->refclk); in ti_pipe3_enable_clocks()
870 dev_err(phy->dev, "Failed to enable refclk %d\n", ret); in ti_pipe3_enable_clocks()
875 if (!IS_ERR(phy->wkupclk)) { in ti_pipe3_enable_clocks()
876 ret = clk_prepare_enable(phy->wkupclk); in ti_pipe3_enable_clocks()
878 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); in ti_pipe3_enable_clocks()
883 if (!IS_ERR(phy->div_clk)) { in ti_pipe3_enable_clocks()
884 ret = clk_prepare_enable(phy->div_clk); in ti_pipe3_enable_clocks()
886 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); in ti_pipe3_enable_clocks()
894 if (!IS_ERR(phy->wkupclk)) in ti_pipe3_enable_clocks()
895 clk_disable_unprepare(phy->wkupclk); in ti_pipe3_enable_clocks()
898 if (!IS_ERR(phy->refclk)) in ti_pipe3_enable_clocks()
899 clk_disable_unprepare(phy->refclk); in ti_pipe3_enable_clocks()
906 if (!IS_ERR(phy->wkupclk)) in ti_pipe3_disable_clocks()
907 clk_disable_unprepare(phy->wkupclk); in ti_pipe3_disable_clocks()
908 if (!IS_ERR(phy->refclk)) in ti_pipe3_disable_clocks()
909 clk_disable_unprepare(phy->refclk); in ti_pipe3_disable_clocks()
910 if (!IS_ERR(phy->div_clk)) in ti_pipe3_disable_clocks()
911 clk_disable_unprepare(phy->div_clk); in ti_pipe3_disable_clocks()
916 .compatible = "ti,phy-usb3",
920 .compatible = "ti,omap-usb3",
924 .compatible = "ti,phy-pipe3-sata",
928 .compatible = "ti,phy-pipe3-pcie",
939 .name = "ti-pipe3",