Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/berlin2q.h>
19 #include "berlin2-div.h"
20 #include "berlin2-pll.h"
45 REFCLK, enumerator
52 [REFCLK] = "refclk",
291 clk_data->num = MAX_CLKS; in berlin2q_clock_setup()
292 hws = clk_data->hws; in berlin2q_clock_setup()
309 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2q_clock_setup()
311 clk_names[REFCLK] = __clk_get_name(clk); in berlin2q_clock_setup()
317 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
322 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
338 for (k = 0; k < dd->num_parents; k++) in berlin2q_clock_setup()
339 parent_names[k] = clk_names[dd->parent_ids[k]]; in berlin2q_clock_setup()
341 hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase, in berlin2q_clock_setup()
342 dd->name, dd->div_flags, parent_names, in berlin2q_clock_setup()
343 dd->num_parents, dd->flags, &lock); in berlin2q_clock_setup()
350 hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name, in berlin2q_clock_setup()
351 gd->parent_name, gd->flags, gbase + REG_CLKENABLE, in berlin2q_clock_setup()
352 gd->bit_idx, 0, &lock); in berlin2q_clock_setup()
372 /* register clk-provider */ in berlin2q_clock_setup()
381 CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",