Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
24 int refclk, struct gma_clock_t *best_clock);
56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
117 ret__ = -ETIMEDOUT; \
216 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
287 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
289 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
292 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
295 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
311 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
312 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
326 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
327 return -EINVAL; in cdv_dpll_set_clock_cdv()
364 int refclk) in cdv_intel_limit() argument
369 * Now only single-channel LVDS is supported on CDV. If it is in cdv_intel_limit()
370 * incorrect, please add the dual-channel LVDS. in cdv_intel_limit()
372 if (refclk == 96000) in cdv_intel_limit()
378 if (refclk == 27000) in cdv_intel_limit()
383 if (refclk == 27000) in cdv_intel_limit()
392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
394 clock->m = clock->m2 + 2; in cdv_intel_clock()
395 clock->p = clock->p1 * clock->p2; in cdv_intel_clock()
396 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
397 clock->dot = clock->vco / clock->p; in cdv_intel_clock()
402 int refclk, in cdv_intel_find_dp_pll() argument
410 switch (refclk) { in cdv_intel_find_dp_pll()
447 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
458 struct drm_psb_private *dev_priv = dev->dev_private; in cdv_intel_pipe_enabled()
461 crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in cdv_intel_pipe_enabled()
464 if (crtc->primary->fb == NULL || !gma_crtc->active) in cdv_intel_pipe_enabled()
473 /* Disable self-refresh before adjust WM */ in cdv_disable_sr()
482 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
492 struct drm_psb_private *dev_priv = dev->dev_private; in cdv_update_wm()
518 if (gma_crtc->pipe == 1 && in cdv_update_wm()
533 /* enable self-refresh for single pipe active */ in cdv_update_wm()
550 dev_priv->ops->disable_sr(dev); in cdv_update_wm()
556 * or -1 if the panel fitter is not present or not in use
566 return -1; in cdv_intel_panel_fitter_pipe()
576 struct drm_device *dev = crtc->dev; in cdv_intel_crtc_mode_set()
577 struct drm_psb_private *dev_priv = dev->dev_private; in cdv_intel_crtc_mode_set()
579 int pipe = gma_crtc->pipe; in cdv_intel_crtc_mode_set()
580 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_mode_set()
581 int refclk; in cdv_intel_crtc_mode_set() local
587 struct drm_mode_config *mode_config = &dev->mode_config; in cdv_intel_crtc_mode_set()
593 list_for_each_entry(connector, &mode_config->connector_list, head) { in cdv_intel_crtc_mode_set()
597 if (!connector->encoder in cdv_intel_crtc_mode_set()
598 || connector->encoder->crtc != crtc) in cdv_intel_crtc_mode_set()
601 ddi_select = gma_encoder->ddi_select; in cdv_intel_crtc_mode_set()
602 switch (gma_encoder->type) { in cdv_intel_crtc_mode_set()
624 if (dev_priv->dplla_96mhz) in cdv_intel_crtc_mode_set()
625 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
626 refclk = 96000; in cdv_intel_crtc_mode_set()
628 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
629 refclk = 27000; in cdv_intel_crtc_mode_set()
632 * Based on the spec the low-end SKU has only CRT/LVDS. So it is in cdv_intel_crtc_mode_set()
634 * On the high-end SKU, it will use the 27/100M reference clk in cdv_intel_crtc_mode_set()
640 refclk = 27000; in cdv_intel_crtc_mode_set()
642 refclk = 100000; in cdv_intel_crtc_mode_set()
645 if (is_lvds && dev_priv->lvds_use_ssc) { in cdv_intel_crtc_mode_set()
646 refclk = dev_priv->lvds_ssc_freq * 1000; in cdv_intel_crtc_mode_set()
647 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
652 limit = gma_crtc->clock_funcs->limit(crtc, refclk); in cdv_intel_crtc_mode_set()
654 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in cdv_intel_crtc_mode_set()
658 adjusted_mode->clock, clock.dot); in cdv_intel_crtc_mode_set()
687 pipeconf = REG_READ(map->conf); in cdv_intel_crtc_mode_set()
691 switch (dev_priv->edp.bpp) { in cdv_intel_crtc_mode_set()
706 /* the BPC will be 6 if it is 18-bit LVDS panel */ in cdv_intel_crtc_mode_set()
725 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
726 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
743 /* Set the B0-B3 data pairs corresponding to in cdv_intel_crtc_mode_set()
745 * set the DPLLs for dual-channel mode or not. in cdv_intel_crtc_mode_set()
752 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
770 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
771 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
772 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
776 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
777 dev_err(dev->dev, "Failed to get DPLL lock\n"); in cdv_intel_crtc_mode_set()
778 return -EBUSY; in cdv_intel_crtc_mode_set()
782 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; in cdv_intel_crtc_mode_set()
783 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U… in cdv_intel_crtc_mode_set()
786 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in cdv_intel_crtc_mode_set()
787 ((adjusted_mode->crtc_htotal - 1) << 16)); in cdv_intel_crtc_mode_set()
788 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in cdv_intel_crtc_mode_set()
789 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in cdv_intel_crtc_mode_set()
790 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in cdv_intel_crtc_mode_set()
791 ((adjusted_mode->crtc_hsync_end - 1) << 16)); in cdv_intel_crtc_mode_set()
792 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in cdv_intel_crtc_mode_set()
793 ((adjusted_mode->crtc_vtotal - 1) << 16)); in cdv_intel_crtc_mode_set()
794 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in cdv_intel_crtc_mode_set()
795 ((adjusted_mode->crtc_vblank_end - 1) << 16)); in cdv_intel_crtc_mode_set()
796 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in cdv_intel_crtc_mode_set()
797 ((adjusted_mode->crtc_vsync_end - 1) << 16)); in cdv_intel_crtc_mode_set()
801 REG_WRITE(map->size, in cdv_intel_crtc_mode_set()
802 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); in cdv_intel_crtc_mode_set()
803 REG_WRITE(map->pos, 0); in cdv_intel_crtc_mode_set()
804 REG_WRITE(map->src, in cdv_intel_crtc_mode_set()
805 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); in cdv_intel_crtc_mode_set()
806 REG_WRITE(map->conf, pipeconf); in cdv_intel_crtc_mode_set()
807 REG_READ(map->conf); in cdv_intel_crtc_mode_set()
811 REG_WRITE(map->cntr, dspcntr); in cdv_intel_crtc_mode_set()
816 crtc->helper_private; in cdv_intel_crtc_mode_set()
817 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in cdv_intel_crtc_mode_set()
825 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
829 static void i8xx_clock(int refclk, struct gma_clock_t *clock) in i8xx_clock() argument
831 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in i8xx_clock()
832 clock->p = clock->p1 * clock->p2; in i8xx_clock()
833 clock->vco = refclk * clock->m / (clock->n + 2); in i8xx_clock()
834 clock->dot = clock->vco / clock->p; in i8xx_clock()
841 struct drm_psb_private *dev_priv = dev->dev_private; in cdv_intel_crtc_clock_get()
843 int pipe = gma_crtc->pipe; in cdv_intel_crtc_clock_get()
844 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_clock_get()
849 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in cdv_intel_crtc_clock_get()
852 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
854 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
856 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
860 dpll = p->dpll; in cdv_intel_crtc_clock_get()
862 fp = p->fp0; in cdv_intel_crtc_clock_get()
864 fp = p->fp1; in cdv_intel_crtc_clock_get()
867 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
881 dev_err(dev->dev, "PLL %d\n", dpll); in cdv_intel_crtc_clock_get()
921 int pipe = gma_crtc->pipe; in cdv_intel_crtc_mode_get()
922 struct drm_psb_private *dev_priv = dev->dev_private; in cdv_intel_crtc_mode_get()
923 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in cdv_intel_crtc_mode_get()
924 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_mode_get()
932 htot = REG_READ(map->htotal); in cdv_intel_crtc_mode_get()
933 hsync = REG_READ(map->hsync); in cdv_intel_crtc_mode_get()
934 vtot = REG_READ(map->vtotal); in cdv_intel_crtc_mode_get()
935 vsync = REG_READ(map->vsync); in cdv_intel_crtc_mode_get()
938 htot = p->htotal; in cdv_intel_crtc_mode_get()
939 hsync = p->hsync; in cdv_intel_crtc_mode_get()
940 vtot = p->vtotal; in cdv_intel_crtc_mode_get()
941 vsync = p->vsync; in cdv_intel_crtc_mode_get()
948 mode->clock = cdv_intel_crtc_clock_get(dev, crtc); in cdv_intel_crtc_mode_get()
949 mode->hdisplay = (htot & 0xffff) + 1; in cdv_intel_crtc_mode_get()
950 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
951 mode->hsync_start = (hsync & 0xffff) + 1; in cdv_intel_crtc_mode_get()
952 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
953 mode->vdisplay = (vtot & 0xffff) + 1; in cdv_intel_crtc_mode_get()
954 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
955 mode->vsync_start = (vsync & 0xffff) + 1; in cdv_intel_crtc_mode_get()
956 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()