Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0-only
38 int refclk, struct gma_clock_t *best_clock);
42 int refclk, struct gma_clock_t *best_clock);
81 int refclk) in mrst_limit() argument
84 struct drm_device *dev = crtc->dev; in mrst_limit()
85 struct drm_psb_private *dev_priv = dev->dev_private; in mrst_limit()
89 switch (dev_priv->core_freq) { in mrst_limit()
104 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); in mrst_limit()
110 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
111 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
113 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
119 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
120 clock->p1, clock->p2); in mrst_print_pll()
125 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
134 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
135 for (clock.n = limit->n.min; clock.n <= limit->n.max; in mrst_sdvo_find_best_pll()
137 for (clock.p1 = limit->p1.min; in mrst_sdvo_find_best_pll()
138 clock.p1 <= limit->p1.max; clock.p1++) { in mrst_sdvo_find_best_pll()
140 clock.p = clock.p1 * limit->p2.p2_slow; in mrst_sdvo_find_best_pll()
144 if (target_vco > limit->vco.max) in mrst_sdvo_find_best_pll()
147 if (target_vco < limit->vco.min) in mrst_sdvo_find_best_pll()
150 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
152 freq_error = 10000 - in mrst_sdvo_find_best_pll()
155 if (freq_error < -min_error) { in mrst_sdvo_find_best_pll()
162 freq_error = -freq_error; in mrst_sdvo_find_best_pll()
178 * Returns a set of divisors for the desired target clock with the given refclk,
183 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
191 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_lvds_find_best_pll()
192 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; in mrst_lvds_find_best_pll()
196 mrst_lvds_clock(refclk, &clock); in mrst_lvds_find_best_pll()
198 this_err = abs(clock.dot - target); in mrst_lvds_find_best_pll()
216 struct drm_device *dev = crtc->dev; in oaktrail_crtc_dpms()
217 struct drm_psb_private *dev_priv = dev->dev_private; in oaktrail_crtc_dpms()
219 int pipe = gma_crtc->pipe; in oaktrail_crtc_dpms()
220 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_crtc_dpms()
242 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
244 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
245 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
250 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
253 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
261 temp = REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
263 REG_WRITE_WITH_AUX(map->conf, in oaktrail_crtc_dpms()
268 temp = REG_READ_WITH_AUX(map->cntr, i); in oaktrail_crtc_dpms()
270 REG_WRITE_WITH_AUX(map->cntr, in oaktrail_crtc_dpms()
274 REG_WRITE_WITH_AUX(map->base, in oaktrail_crtc_dpms()
275 REG_READ_WITH_AUX(map->base, i), i); in oaktrail_crtc_dpms()
294 temp = REG_READ_WITH_AUX(map->cntr, i); in oaktrail_crtc_dpms()
296 REG_WRITE_WITH_AUX(map->cntr, in oaktrail_crtc_dpms()
299 REG_WRITE_WITH_AUX(map->base, in oaktrail_crtc_dpms()
300 REG_READ(map->base), i); in oaktrail_crtc_dpms()
301 REG_READ_WITH_AUX(map->base, i); in oaktrail_crtc_dpms()
305 temp = REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
307 REG_WRITE_WITH_AUX(map->conf, in oaktrail_crtc_dpms()
309 REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
314 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
318 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
342 * or -1 if the panel fitter is not present or not in use
352 return -1; in oaktrail_panel_fitter_pipe()
362 struct drm_device *dev = crtc->dev; in oaktrail_crtc_mode_set()
364 struct drm_psb_private *dev_priv = dev->dev_private; in oaktrail_crtc_mode_set()
365 int pipe = gma_crtc->pipe; in oaktrail_crtc_mode_set()
366 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_crtc_mode_set()
367 int refclk = 0; in oaktrail_crtc_mode_set() local
374 struct drm_mode_config *mode_config = &dev->mode_config; in oaktrail_crtc_mode_set()
387 memcpy(&gma_crtc->saved_mode, in oaktrail_crtc_mode_set()
390 memcpy(&gma_crtc->saved_adjusted_mode, in oaktrail_crtc_mode_set()
394 list_for_each_entry(connector, &mode_config->connector_list, head) { in oaktrail_crtc_mode_set()
395 if (!connector->encoder || connector->encoder->crtc != crtc) in oaktrail_crtc_mode_set()
400 switch (gma_encoder->type) { in oaktrail_crtc_mode_set()
422 REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) | in oaktrail_crtc_mode_set()
423 (mode->crtc_vdisplay - 1), i); in oaktrail_crtc_mode_set()
427 drm_object_property_get_value(&connector->base, in oaktrail_crtc_mode_set()
428 dev->mode_config.scaling_mode_property, &scalingType); in oaktrail_crtc_mode_set()
436 offsetX = (adjusted_mode->crtc_hdisplay - in oaktrail_crtc_mode_set()
437 mode->crtc_hdisplay) / 2; in oaktrail_crtc_mode_set()
438 offsetY = (adjusted_mode->crtc_vdisplay - in oaktrail_crtc_mode_set()
439 mode->crtc_vdisplay) / 2; in oaktrail_crtc_mode_set()
442 REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) | in oaktrail_crtc_mode_set()
443 ((adjusted_mode->crtc_htotal - 1) << 16), i); in oaktrail_crtc_mode_set()
444 REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) | in oaktrail_crtc_mode_set()
445 ((adjusted_mode->crtc_vtotal - 1) << 16), i); in oaktrail_crtc_mode_set()
446 REG_WRITE_WITH_AUX(map->hblank, in oaktrail_crtc_mode_set()
447 (adjusted_mode->crtc_hblank_start - offsetX - 1) | in oaktrail_crtc_mode_set()
448 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i); in oaktrail_crtc_mode_set()
449 REG_WRITE_WITH_AUX(map->hsync, in oaktrail_crtc_mode_set()
450 (adjusted_mode->crtc_hsync_start - offsetX - 1) | in oaktrail_crtc_mode_set()
451 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i); in oaktrail_crtc_mode_set()
452 REG_WRITE_WITH_AUX(map->vblank, in oaktrail_crtc_mode_set()
453 (adjusted_mode->crtc_vblank_start - offsetY - 1) | in oaktrail_crtc_mode_set()
454 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i); in oaktrail_crtc_mode_set()
455 REG_WRITE_WITH_AUX(map->vsync, in oaktrail_crtc_mode_set()
456 (adjusted_mode->crtc_vsync_start - offsetY - 1) | in oaktrail_crtc_mode_set()
457 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i); in oaktrail_crtc_mode_set()
461 REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in oaktrail_crtc_mode_set()
462 ((adjusted_mode->crtc_htotal - 1) << 16), i); in oaktrail_crtc_mode_set()
463 REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in oaktrail_crtc_mode_set()
464 ((adjusted_mode->crtc_vtotal - 1) << 16), i); in oaktrail_crtc_mode_set()
465 REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in oaktrail_crtc_mode_set()
466 ((adjusted_mode->crtc_hblank_end - 1) << 16), i); in oaktrail_crtc_mode_set()
467 REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in oaktrail_crtc_mode_set()
468 ((adjusted_mode->crtc_hsync_end - 1) << 16), i); in oaktrail_crtc_mode_set()
469 REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in oaktrail_crtc_mode_set()
470 ((adjusted_mode->crtc_vblank_end - 1) << 16), i); in oaktrail_crtc_mode_set()
471 REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in oaktrail_crtc_mode_set()
472 ((adjusted_mode->crtc_vsync_end - 1) << 16), i); in oaktrail_crtc_mode_set()
479 crtc->helper_private; in oaktrail_crtc_mode_set()
480 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in oaktrail_crtc_mode_set()
484 pipeconf = REG_READ(map->conf); in oaktrail_crtc_mode_set()
487 dspcntr = REG_READ(map->cntr); in oaktrail_crtc_mode_set()
501 refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000; in oaktrail_crtc_mode_set()
502 limit = mrst_limit(crtc, refclk); in oaktrail_crtc_mode_set()
503 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, in oaktrail_crtc_mode_set()
504 refclk, &clock); in oaktrail_crtc_mode_set()
508 clock.p1 = (1L << (clock.p1 - 1)); in oaktrail_crtc_mode_set()
509 clock.m -= 2; in oaktrail_crtc_mode_set()
510 clock.n = (1L << (clock.n - 1)); in oaktrail_crtc_mode_set()
521 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8; in oaktrail_crtc_mode_set()
535 adjusted_mode->clock / mode->clock; in oaktrail_crtc_mode_set()
539 (sdvo_pixel_multiply - in oaktrail_crtc_mode_set()
546 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; in oaktrail_crtc_mode_set()
548 dpll |= (1 << (clock.p1 - 2)) << 17; in oaktrail_crtc_mode_set()
554 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
555 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
556 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
563 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
564 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
565 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
569 /* write it again -- the BIOS does, after all */ in oaktrail_crtc_mode_set()
570 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
571 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
575 REG_WRITE_WITH_AUX(map->conf, pipeconf, i); in oaktrail_crtc_mode_set()
576 REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_mode_set()
579 REG_WRITE_WITH_AUX(map->cntr, dspcntr, i); in oaktrail_crtc_mode_set()
591 struct drm_device *dev = crtc->dev; in oaktrail_pipe_set_base()
592 struct drm_psb_private *dev_priv = dev->dev_private; in oaktrail_pipe_set_base()
594 struct drm_framebuffer *fb = crtc->primary->fb; in oaktrail_pipe_set_base()
595 int pipe = gma_crtc->pipe; in oaktrail_pipe_set_base()
596 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_pipe_set_base()
604 dev_dbg(dev->dev, "No FB bound\n"); in oaktrail_pipe_set_base()
611 start = to_gtt_range(fb->obj[0])->offset; in oaktrail_pipe_set_base()
612 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; in oaktrail_pipe_set_base()
614 REG_WRITE(map->stride, fb->pitches[0]); in oaktrail_pipe_set_base()
616 dspcntr = REG_READ(map->cntr); in oaktrail_pipe_set_base()
619 switch (fb->format->cpp[0] * 8) { in oaktrail_pipe_set_base()
624 if (fb->format->depth == 15) in oaktrail_pipe_set_base()
634 dev_err(dev->dev, "Unknown color depth\n"); in oaktrail_pipe_set_base()
635 ret = -EINVAL; in oaktrail_pipe_set_base()
638 REG_WRITE(map->cntr, dspcntr); in oaktrail_pipe_set_base()
640 REG_WRITE(map->base, offset); in oaktrail_pipe_set_base()
641 REG_READ(map->base); in oaktrail_pipe_set_base()
642 REG_WRITE(map->surf, start); in oaktrail_pipe_set_base()
643 REG_READ(map->surf); in oaktrail_pipe_set_base()