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/Kernel-v11.1.0/portable/GCC/ARM7_AT91SAM7S/
D	ioat91sam7x256.h	242 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 243 #define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) / (AIC) Priority … 244 #define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest pr… 245 #define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest p… 246 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt… 247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal … 248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External … 249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal … 250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External … 251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal … [all …]
D	AT91SAM7X256.h	242 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 243 #define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) / (AIC) Priority … 244 #define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest pr… 245 #define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest p… 246 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt… 247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal … 248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External … 249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal … 250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External … 251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal … [all …]
/Kernel-v11.1.0/portable/IAR/AtmelSAM7S64/
D	AT91SAM7X256_inc.h	56 #define AIC_SMR ( 0 ) /* Source Mode Register / 74 / -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 75 #define AT91C_AIC_PRIOR ( 0x7 << 0 ) / (AIC) Priority Level / 76 #define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) / (AIC) Lowest priority level / 77 #define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) / (AIC) Highest priority level / 78 #define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) / (AIC) Interrupt Source Type / 79 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) / (AIC) Internal Sources Code Labe… 80 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Labe… 81 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Labe… 82 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Labe… [all …]
D	AT91SAM7X128_inc.h	56 #define AIC_SMR ( 0 ) /* Source Mode Register / 74 / -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 75 #define AT91C_AIC_PRIOR ( 0x7 << 0 ) / (AIC) Priority Level / 76 #define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) / (AIC) Lowest priority level / 77 #define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) / (AIC) Highest priority level / 78 #define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) / (AIC) Interrupt Source Type / 79 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) / (AIC) Internal Sources Code Labe… 80 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Labe… 81 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Labe… 82 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Labe… [all …]
D	AT91SAM7S64_inc.h	38 #define SYSC_AIC_SMR ( 0 ) /* Source Mode Register / 137 / -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- / 138 #define AT91C_SYSC_PSTDBY ( 0x1 << 0 ) / (SYSC) Voltage Regulator Power Mode / 144 #define AIC_SMR ( 0 ) / Source Mode Register / 162 / -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 163 #define AT91C_AIC_PRIOR ( 0x7 << 0 ) / (AIC) Priority Level / 164 #define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) / (AIC) Lowest priority level / 165 #define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) / (AIC) Highest priority level / 166 #define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) / (AIC) Interrupt Source Type / 167 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( 0x0 << 5 ) / (AIC) Internal Sources Code La… [all …]
D	AT91SAM7X128.h	242 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 243 #define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) / (AIC) Priority … 244 #define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest pr… 245 #define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest p… 246 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt… 247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal … 248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External … 249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal … 250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External … 251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal … [all …]
D	AT91SAM7X256.h	242 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 243 #define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) / (AIC) Priority … 244 #define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest pr… 245 #define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest p… 246 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt… 247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal … 248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External … 249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal … 250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External … 251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal … [all …]
D	AT91SAM7S64.h	163 /* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- / 164 #define AT91C_SYSC_PSTDBY ( ( unsigned int ) 0x1 << 0 ) / (SYSC) Voltage Regulator Power Mode / 193 / -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- / 194 #define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) / (AIC) Priorit… 195 #define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest … 196 #define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest… 197 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interru… 198 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Interna… 199 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Interna… 200 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Externa… [all …]
/Kernel-v11.1.0/portable/GCC/ARM_AARCH64/
D	portASM.S	`52 MSR SPSEL, #0 55 STP X0, X1, [SP, #-0x10]! 56 STP X2, X3, [SP, #-0x10]! 57 STP X4, X5, [SP, #-0x10]! 58 STP X6, X7, [SP, #-0x10]! 59 STP X8, X9, [SP, #-0x10]! 60 STP X10, X11, [SP, #-0x10]! 61 STP X12, X13, [SP, #-0x10]! 62 STP X14, X15, [SP, #-0x10]! 63 STP X16, X17, [SP, #-0x10]! [all …]`
/Kernel-v11.1.0/portable/GCC/ARM_AARCH64_SRE/
D	portASM.S	`50 MSR SPSEL, #0 53 STP X0, X1, [SP, #-0x10]! 54 STP X2, X3, [SP, #-0x10]! 55 STP X4, X5, [SP, #-0x10]! 56 STP X6, X7, [SP, #-0x10]! 57 STP X8, X9, [SP, #-0x10]! 58 STP X10, X11, [SP, #-0x10]! 59 STP X12, X13, [SP, #-0x10]! 60 STP X14, X15, [SP, #-0x10]! 61 STP X16, X17, [SP, #-0x10]! [all …]`
D	port.c	48 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 49 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" 76 #define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) 80 #define portUNMASK_VALUE ( 0xFFUL ) 87 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) 90 #define portSP_ELx ( ( StackType_t ) 0x01 ) 91 #define portSP_EL0 ( ( StackType_t ) 0x00 ) 94 #define portEL1 ( ( StackType_t ) 0x04 ) 97 #define portEL3 ( ( StackType_t ) 0x0c ) 103 #define portAPSR_MODE_BITS_MASK ( 0x0C ) [all …]
/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/
D	xtensa_loadstore_handler.S	`16 * 16 0 21 * 23 0 48 .word 0 70 s32i a0, sp, 0x04 // Since a0 contains value of a1 71 s32i a2, sp, 0x08 72 s32i a3, sp, 0x0c 73 s32i a4, sp, 0x10 98 l32i a4, a2, 0 110 l32i a4, a4, 0 // perform the actual read 114 extui a4, a4, 0, 8 // mask off bits needed for an l8 [all …]`
/Kernel-v11.1.0/portable/GCC/ARM_CRx_MPU/
D	portmacro_asm.h	`50 * setting configENABLE_FPU to 0. Floating point context stored in TCB 66 * using the Current Program Status Register (CPSR) Mode bits, [4:0]. The only 79 #define USER_MODE 0x10U 80 #define FIQ_MODE 0x11U 81 #define IRQ_MODE 0x12U 82 #define SVC_MODE 0x13U 83 #define MON_MODE 0x16U 84 #define ABT_MODE 0x17U 85 #define HYP_MODE 0x1AU 86 #define UND_MODE 0x1BU [all …]`
/Kernel-v11.1.0/.github/
D	uncrustify.cfg	`1 # Uncrustify-0.69.0 7 string_escape_char2 = 0 # unsigned number 231 indent_continue = 0 # number 232 indent_continue_class_head = 0 # unsigned number 234 indent_param = 0 # unsigned number 235 indent_with_tabs = 0 # unsigned number 238 indent_xml_string = 0 # unsigned number 239 indent_brace = 0 # unsigned number 250 indent_namespace_level = 0 # unsigned number 251 indent_namespace_limit = 0 # unsigned number [all …]`
/Kernel-v11.1.0/portable/IAR/V850ES/
D	portasm_Hx2.s85	`49 #define CG_SECURITY0 0FFH 50 #define CG_SECURITY1 0FFH 51 #define CG_SECURITY2 0FFH 52 #define CG_SECURITY3 0FFH 53 #define CG_SECURITY4 0FFH 54 #define CG_SECURITY5 0FFH 55 #define CG_SECURITY6 0FFH 56 #define CG_SECURITY7 0FFH 57 #define CG_SECURITY8 0FFH 58 #define CG_SECURITY9 0FFH [all …]`
D	port.c	41 #define portPSW ( ( StackType_t ) 0x00000000 ) 66 pxTopOfStack = ( StackType_t ) 0x20202020; / Initial Value of R20 / in pxPortInitialiseStack() 68 pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 / in pxPortInitialiseStack() 70 pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 / in pxPortInitialiseStack() 72 pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 / in pxPortInitialiseStack() 74 pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 / in pxPortInitialiseStack() 76 #if ( __DATA_MODEL__ == 0 ) \|\| ( __DATA_MODEL__ == 1 ) in pxPortInitialiseStack() 77 pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 / in pxPortInitialiseStack() 80 pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 / in pxPortInitialiseStack() 82 pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */ in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/GCC/ARM_CM0/
D	portmacro.h	49 … defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. 71 #define portMAX_DELAY ( TickType_t ) 0xffff 74 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 123 #define portPRIVILEGE_BIT ( 0x80000000UL ) 125 #define portPRIVILEGE_BIT ( 0x0UL ) 130 #define configS_C_B_FLASH ( 0x07UL ) 135 #define configS_C_B_SRAM ( 0x07UL ) 143 #define portFIRST_CONFIGURABLE_REGION ( 0UL ) 150 #define portMPU_REGION_SIZE_256B ( 0x07UL << 1UL ) 151 #define portMPU_REGION_SIZE_512B ( 0x08UL << 1UL ) [all …]
/Kernel-v11.1.0/portable/CCS/ARM_Cortex-R4/
D	port.c	41 #define portRTI_GCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) ) 42 #define portRTI_TBCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) ) 43 #define portRTI_COMPCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) ) 44 #define portRTI_CNT0_FRC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) ) 45 #define portRTI_CNT0_UC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) ) 46 #define portRTI_CNT0_CPUC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) ) 47 #define portRTI_CNT0_COMP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) ) 48 #define portRTI_CNT0_UDCP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) ) 49 #define portRTI_SETINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) ) 50 #define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) ) [all …]
/Kernel-v11.1.0/portable/Softune/MB91460/
D	port.c	`44 ORCCR #0x20 ;Switch to user stack 51 ANDCCR #0xDF ;Switch back to system stack 53 ORCCR #0x20 ;Switch to user stack 56 ANDCCR #0xDF ;Switch back to system stack 58 ORCCR #0x20 ;Switch to user stack 65 … ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR 71 ORCCR #0x20 ;Switch to user stack 75 ANDCCR #0xDF ;Switch to system stack 78 ORCCR #0x20 ;Switch to user stack 80 ANDCCR #0xDF ;Switch to system stack [all …]`
/Kernel-v11.1.0/portable/GCC/ARM_CM3_MPU/
D	port.c	53 #define portNVIC_SYSTICK_CLK ( 0 ) 57 …_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h … 65 #define portNVIC_SYSTICK_CTRL_REG ( ( ( volatile uint32_t ) 0xe000e010 ) ) 66 #define portNVIC_SYSTICK_LOAD_REG ( ( ( volatile uint32_t ) 0xe000e014 ) ) 67 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( ( ( volatile uint32_t ) 0xe000e018 ) ) 68 #define portNVIC_SHPR3_REG ( ( ( volatile uint32_t ) 0xe000ed20 ) ) 69 #define portNVIC_SHPR2_REG ( ( ( volatile uint32_t ) 0xe000ed1c ) ) 70 #define portNVIC_SYS_CTRL_STATE_REG ( ( ( volatile uint32_t ) 0xe000ed24 ) ) 74 #define portMPU_TYPE_REG ( ( ( volatile uint32_t ) 0xe000ed90 ) ) 75 #define portMPU_REGION_BASE_ADDRESS_REG ( ( ( volatile uint32_t ) 0xe000ed9C ) ) [all …]
/Kernel-v11.1.0/portable/RVDS/ARM_CM4_MPU/
D	port.c	50 …_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h … 58 #define portNVIC_SYSTICK_CTRL_REG ( ( ( volatile uint32_t ) 0xe000e010 ) ) 59 #define portNVIC_SYSTICK_LOAD_REG ( ( ( volatile uint32_t ) 0xe000e014 ) ) 60 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( ( ( volatile uint32_t ) 0xe000e018 ) ) 61 #define portNVIC_SHPR3_REG ( ( ( volatile uint32_t ) 0xe000ed20 ) ) 62 #define portNVIC_SHPR2_REG ( ( ( volatile uint32_t ) 0xe000ed1c ) ) 63 #define portNVIC_SYS_CTRL_STATE_REG ( ( ( volatile uint32_t ) 0xe000ed24 ) ) 68 #define portCPUID ( ( ( volatile uint32_t ) 0xE000ed00 ) ) 69 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) 70 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) [all …]
/Kernel-v11.1.0/portable/GCC/H8S2329/
D	port.c	42 #define portINITIAL_CCR ( ( StackType_t ) 0x00 ) 45 #define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 ) 46 #define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 ) 48 #define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 ) 49 #define portTIMER_CHANNEL ( ( uint8_t ) 0x02 ) 50 #define portMSTP13 ( ( uint16_t ) 0x2000 ) 84 pxTopOfStack = 0xaa; in pxPortInitialiseStack() 86 pxTopOfStack = 0xbb; in pxPortInitialiseStack() 88 pxTopOfStack = 0xcc; in pxPortInitialiseStack() 90 pxTopOfStack = 0xdd; in pxPortInitialiseStack() [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM35P_NTZ/non_secure/
D	port.c	60 * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 63 * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 66 * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 76 #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) 77 #define portUSE_PSPLIM_REGISTER 0 92 #define portNVIC_SYSTICK_CTRL_REG ( ( ( volatile uint32_t ) 0xe000e010 ) ) 93 #define portNVIC_SYSTICK_LOAD_REG ( ( ( volatile uint32_t ) 0xe000e014 ) ) 94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( ( ( volatile uint32_t ) 0xe000e018 ) ) 95 #define portNVIC_SHPR3_REG ( ( ( volatile uint32_t ) 0xe000ed20 ) ) 96 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM33_NTZ/non_secure/
D	port.c	60 * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 63 * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 66 * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 76 #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) 77 #define portUSE_PSPLIM_REGISTER 0 92 #define portNVIC_SYSTICK_CTRL_REG ( ( ( volatile uint32_t ) 0xe000e010 ) ) 93 #define portNVIC_SYSTICK_LOAD_REG ( ( ( volatile uint32_t ) 0xe000e014 ) ) 94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( ( ( volatile uint32_t ) 0xe000e018 ) ) 95 #define portNVIC_SHPR3_REG ( ( ( volatile uint32_t ) 0xe000ed20 ) ) 96 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) [all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM35P/non_secure/
D	port.c	60 * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 63 * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 66 * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 76 #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) 77 #define portUSE_PSPLIM_REGISTER 0 92 #define portNVIC_SYSTICK_CTRL_REG ( ( ( volatile uint32_t ) 0xe000e010 ) ) 93 #define portNVIC_SYSTICK_LOAD_REG ( ( ( volatile uint32_t ) 0xe000e014 ) ) 94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( ( ( volatile uint32_t ) 0xe000e018 ) ) 95 #define portNVIC_SHPR3_REG ( ( ( volatile uint32_t ) 0xe000ed20 ) ) 96 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) [all …]

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