1 /* ---------------------------------------------------------------------------- */ 2 /* ATMEL Microcontroller Software Support - ROUSSET - */ 3 /* ---------------------------------------------------------------------------- */ 4 /* The software is delivered "AS IS" without warranty or condition of any */ 5 /* kind, either express, implied or statutory. This includes without */ 6 /* limitation any warranty or condition with respect to merchantability or */ 7 /* fitness for any particular purpose, or against the infringements of */ 8 /* intellectual property rights of others. */ 9 /* ---------------------------------------------------------------------------- */ 10 /* File Name : AT91SAM7S64.h */ 11 /* Object : AT91SAM7S64 definitions */ 12 /* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */ 13 /* */ 14 /* CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */ 15 /* CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */ 16 /* CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */ 17 /* CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// */ 18 /* CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ 19 /* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */ 20 /* CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ 21 /* CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */ 22 /* CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */ 23 /* CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */ 24 /* CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// */ 25 /* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ 26 /* CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// */ 27 /* CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */ 28 /* CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */ 29 /* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ 30 /* ---------------------------------------------------------------------------- */ 31 32 /* Hardware register definition */ 33 34 /* ***************************************************************************** */ 35 /* SOFTWARE API DEFINITION FOR System Peripherals */ 36 /* ***************************************************************************** */ 37 /* *** Register offset in AT91S_SYSC structure *** */ 38 #define SYSC_AIC_SMR ( 0 ) /* Source Mode Register */ 39 #define SYSC_AIC_SVR ( 128 ) /* Source Vector Register */ 40 #define SYSC_AIC_IVR ( 256 ) /* IRQ Vector Register */ 41 #define SYSC_AIC_FVR ( 260 ) /* FIQ Vector Register */ 42 #define SYSC_AIC_ISR ( 264 ) /* Interrupt Status Register */ 43 #define SYSC_AIC_IPR ( 268 ) /* Interrupt Pending Register */ 44 #define SYSC_AIC_IMR ( 272 ) /* Interrupt Mask Register */ 45 #define SYSC_AIC_CISR ( 276 ) /* Core Interrupt Status Register */ 46 #define SYSC_AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ 47 #define SYSC_AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ 48 #define SYSC_AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ 49 #define SYSC_AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ 50 #define SYSC_AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ 51 #define SYSC_AIC_SPU ( 308 ) /* Spurious Vector Register */ 52 #define SYSC_AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ 53 #define SYSC_AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ 54 #define SYSC_AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ 55 #define SYSC_AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ 56 #define SYSC_DBGU_CR ( 512 ) /* Control Register */ 57 #define SYSC_DBGU_MR ( 516 ) /* Mode Register */ 58 #define SYSC_DBGU_IER ( 520 ) /* Interrupt Enable Register */ 59 #define SYSC_DBGU_IDR ( 524 ) /* Interrupt Disable Register */ 60 #define SYSC_DBGU_IMR ( 528 ) /* Interrupt Mask Register */ 61 #define SYSC_DBGU_CSR ( 532 ) /* Channel Status Register */ 62 #define SYSC_DBGU_RHR ( 536 ) /* Receiver Holding Register */ 63 #define SYSC_DBGU_THR ( 540 ) /* Transmitter Holding Register */ 64 #define SYSC_DBGU_BRGR ( 544 ) /* Baud Rate Generator Register */ 65 #define SYSC_DBGU_C1R ( 576 ) /* Chip ID1 Register */ 66 #define SYSC_DBGU_C2R ( 580 ) /* Chip ID2 Register */ 67 #define SYSC_DBGU_FNTR ( 584 ) /* Force NTRST Register */ 68 #define SYSC_DBGU_RPR ( 768 ) /* Receive Pointer Register */ 69 #define SYSC_DBGU_RCR ( 772 ) /* Receive Counter Register */ 70 #define SYSC_DBGU_TPR ( 776 ) /* Transmit Pointer Register */ 71 #define SYSC_DBGU_TCR ( 780 ) /* Transmit Counter Register */ 72 #define SYSC_DBGU_RNPR ( 784 ) /* Receive Next Pointer Register */ 73 #define SYSC_DBGU_RNCR ( 788 ) /* Receive Next Counter Register */ 74 #define SYSC_DBGU_TNPR ( 792 ) /* Transmit Next Pointer Register */ 75 #define SYSC_DBGU_TNCR ( 796 ) /* Transmit Next Counter Register */ 76 #define SYSC_DBGU_PTCR ( 800 ) /* PDC Transfer Control Register */ 77 #define SYSC_DBGU_PTSR ( 804 ) /* PDC Transfer Status Register */ 78 #define SYSC_PIOA_PER ( 1024 ) /* PIO Enable Register */ 79 #define SYSC_PIOA_PDR ( 1028 ) /* PIO Disable Register */ 80 #define SYSC_PIOA_PSR ( 1032 ) /* PIO Status Register */ 81 #define SYSC_PIOA_OER ( 1040 ) /* Output Enable Register */ 82 #define SYSC_PIOA_ODR ( 1044 ) /* Output Disable Registerr */ 83 #define SYSC_PIOA_OSR ( 1048 ) /* Output Status Register */ 84 #define SYSC_PIOA_IFER ( 1056 ) /* Input Filter Enable Register */ 85 #define SYSC_PIOA_IFDR ( 1060 ) /* Input Filter Disable Register */ 86 #define SYSC_PIOA_IFSR ( 1064 ) /* Input Filter Status Register */ 87 #define SYSC_PIOA_SODR ( 1072 ) /* Set Output Data Register */ 88 #define SYSC_PIOA_CODR ( 1076 ) /* Clear Output Data Register */ 89 #define SYSC_PIOA_ODSR ( 1080 ) /* Output Data Status Register */ 90 #define SYSC_PIOA_PDSR ( 1084 ) /* Pin Data Status Register */ 91 #define SYSC_PIOA_IER ( 1088 ) /* Interrupt Enable Register */ 92 #define SYSC_PIOA_IDR ( 1092 ) /* Interrupt Disable Register */ 93 #define SYSC_PIOA_IMR ( 1096 ) /* Interrupt Mask Register */ 94 #define SYSC_PIOA_ISR ( 1100 ) /* Interrupt Status Register */ 95 #define SYSC_PIOA_MDER ( 1104 ) /* Multi-driver Enable Register */ 96 #define SYSC_PIOA_MDDR ( 1108 ) /* Multi-driver Disable Register */ 97 #define SYSC_PIOA_MDSR ( 1112 ) /* Multi-driver Status Register */ 98 #define SYSC_PIOA_PPUDR ( 1120 ) /* Pull-up Disable Register */ 99 #define SYSC_PIOA_PPUER ( 1124 ) /* Pull-up Enable Register */ 100 #define SYSC_PIOA_PPUSR ( 1128 ) /* Pad Pull-up Status Register */ 101 #define SYSC_PIOA_ASR ( 1136 ) /* Select A Register */ 102 #define SYSC_PIOA_BSR ( 1140 ) /* Select B Register */ 103 #define SYSC_PIOA_ABSR ( 1144 ) /* AB Select Status Register */ 104 #define SYSC_PIOA_OWER ( 1184 ) /* Output Write Enable Register */ 105 #define SYSC_PIOA_OWDR ( 1188 ) /* Output Write Disable Register */ 106 #define SYSC_PIOA_OWSR ( 1192 ) /* Output Write Status Register */ 107 #define SYSC_PMC_SCER ( 3072 ) /* System Clock Enable Register */ 108 #define SYSC_PMC_SCDR ( 3076 ) /* System Clock Disable Register */ 109 #define SYSC_PMC_SCSR ( 3080 ) /* System Clock Status Register */ 110 #define SYSC_PMC_PCER ( 3088 ) /* Peripheral Clock Enable Register */ 111 #define SYSC_PMC_PCDR ( 3092 ) /* Peripheral Clock Disable Register */ 112 #define SYSC_PMC_PCSR ( 3096 ) /* Peripheral Clock Status Register */ 113 #define SYSC_PMC_MOR ( 3104 ) /* Main Oscillator Register */ 114 #define SYSC_PMC_MCFR ( 3108 ) /* Main Clock Frequency Register */ 115 #define SYSC_PMC_PLLR ( 3116 ) /* PLL Register */ 116 #define SYSC_PMC_MCKR ( 3120 ) /* Master Clock Register */ 117 #define SYSC_PMC_PCKR ( 3136 ) /* Programmable Clock Register */ 118 #define SYSC_PMC_IER ( 3168 ) /* Interrupt Enable Register */ 119 #define SYSC_PMC_IDR ( 3172 ) /* Interrupt Disable Register */ 120 #define SYSC_PMC_SR ( 3176 ) /* Status Register */ 121 #define SYSC_PMC_IMR ( 3180 ) /* Interrupt Mask Register */ 122 #define SYSC_RSTC_RCR ( 3328 ) /* Reset Control Register */ 123 #define SYSC_RSTC_RSR ( 3332 ) /* Reset Status Register */ 124 #define SYSC_RSTC_RMR ( 3336 ) /* Reset Mode Register */ 125 #define SYSC_RTTC_RTMR ( 3360 ) /* Real-time Mode Register */ 126 #define SYSC_RTTC_RTAR ( 3364 ) /* Real-time Alarm Register */ 127 #define SYSC_RTTC_RTVR ( 3368 ) /* Real-time Value Register */ 128 #define SYSC_RTTC_RTSR ( 3372 ) /* Real-time Status Register */ 129 #define SYSC_PITC_PIMR ( 3376 ) /* Period Interval Mode Register */ 130 #define SYSC_PITC_PISR ( 3380 ) /* Period Interval Status Register */ 131 #define SYSC_PITC_PIVR ( 3384 ) /* Period Interval Value Register */ 132 #define SYSC_PITC_PIIR ( 3388 ) /* Period Interval Image Register */ 133 #define SYSC_WDTC_WDCR ( 3392 ) /* Watchdog Control Register */ 134 #define SYSC_WDTC_WDMR ( 3396 ) /* Watchdog Mode Register */ 135 #define SYSC_WDTC_WDSR ( 3400 ) /* Watchdog Status Register */ 136 #define SYSC_SYSC_VRPM ( 3424 ) /* Voltage Regulator Power Mode Register */ 137 /* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */ 138 #define AT91C_SYSC_PSTDBY ( 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */ 139 140 /* ***************************************************************************** */ 141 /* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ 142 /* ***************************************************************************** */ 143 /* *** Register offset in AT91S_AIC structure *** */ 144 #define AIC_SMR ( 0 ) /* Source Mode Register */ 145 #define AIC_SVR ( 128 ) /* Source Vector Register */ 146 #define AIC_IVR ( 256 ) /* IRQ Vector Register */ 147 #define AIC_FVR ( 260 ) /* FIQ Vector Register */ 148 #define AIC_ISR ( 264 ) /* Interrupt Status Register */ 149 #define AIC_IPR ( 268 ) /* Interrupt Pending Register */ 150 #define AIC_IMR ( 272 ) /* Interrupt Mask Register */ 151 #define AIC_CISR ( 276 ) /* Core Interrupt Status Register */ 152 #define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ 153 #define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ 154 #define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ 155 #define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ 156 #define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ 157 #define AIC_SPU ( 308 ) /* Spurious Vector Register */ 158 #define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ 159 #define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ 160 #define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ 161 #define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ 162 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ 163 #define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */ 164 #define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */ 165 #define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */ 166 #define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */ 167 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */ 168 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */ 169 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */ 170 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */ 171 /* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ 172 #define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */ 173 #define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */ 174 /* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ 175 #define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */ 176 #define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */ 177 178 /* ***************************************************************************** */ 179 /* SOFTWARE API DEFINITION FOR Debug Unit */ 180 /* ***************************************************************************** */ 181 /* *** Register offset in AT91S_DBGU structure *** */ 182 #define DBGU_CR ( 0 ) /* Control Register */ 183 #define DBGU_MR ( 4 ) /* Mode Register */ 184 #define DBGU_IER ( 8 ) /* Interrupt Enable Register */ 185 #define DBGU_IDR ( 12 ) /* Interrupt Disable Register */ 186 #define DBGU_IMR ( 16 ) /* Interrupt Mask Register */ 187 #define DBGU_CSR ( 20 ) /* Channel Status Register */ 188 #define DBGU_RHR ( 24 ) /* Receiver Holding Register */ 189 #define DBGU_THR ( 28 ) /* Transmitter Holding Register */ 190 #define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */ 191 #define DBGU_C1R ( 64 ) /* Chip ID1 Register */ 192 #define DBGU_C2R ( 68 ) /* Chip ID2 Register */ 193 #define DBGU_FNTR ( 72 ) /* Force NTRST Register */ 194 #define DBGU_RPR ( 256 ) /* Receive Pointer Register */ 195 #define DBGU_RCR ( 260 ) /* Receive Counter Register */ 196 #define DBGU_TPR ( 264 ) /* Transmit Pointer Register */ 197 #define DBGU_TCR ( 268 ) /* Transmit Counter Register */ 198 #define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */ 199 #define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */ 200 #define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */ 201 #define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */ 202 #define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */ 203 #define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */ 204 /* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ 205 #define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */ 206 #define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */ 207 #define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */ 208 #define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */ 209 #define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */ 210 #define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */ 211 /* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ 212 #define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */ 213 #define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */ 214 #define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */ 215 #define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ 216 #define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ 217 #define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */ 218 #define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */ 219 #define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */ 220 #define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ 221 #define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ 222 #define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ 223 #define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ 224 /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ 225 #define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ 226 #define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ 227 #define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ 228 #define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ 229 #define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ 230 #define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ 231 #define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ 232 #define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ 233 #define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ 234 #define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ 235 #define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ 236 #define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ 237 /* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ 238 /* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ 239 /* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ 240 /* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ 241 #define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ 242 243 /* ***************************************************************************** */ 244 /* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ 245 /* ***************************************************************************** */ 246 /* *** Register offset in AT91S_PDC structure *** */ 247 #define PDC_RPR ( 0 ) /* Receive Pointer Register */ 248 #define PDC_RCR ( 4 ) /* Receive Counter Register */ 249 #define PDC_TPR ( 8 ) /* Transmit Pointer Register */ 250 #define PDC_TCR ( 12 ) /* Transmit Counter Register */ 251 #define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */ 252 #define PDC_RNCR ( 20 ) /* Receive Next Counter Register */ 253 #define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */ 254 #define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */ 255 #define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */ 256 #define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */ 257 /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ 258 #define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ 259 #define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ 260 #define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ 261 #define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ 262 /* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ 263 264 /* ***************************************************************************** */ 265 /* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ 266 /* ***************************************************************************** */ 267 /* *** Register offset in AT91S_PIO structure *** */ 268 #define PIO_PER ( 0 ) /* PIO Enable Register */ 269 #define PIO_PDR ( 4 ) /* PIO Disable Register */ 270 #define PIO_PSR ( 8 ) /* PIO Status Register */ 271 #define PIO_OER ( 16 ) /* Output Enable Register */ 272 #define PIO_ODR ( 20 ) /* Output Disable Registerr */ 273 #define PIO_OSR ( 24 ) /* Output Status Register */ 274 #define PIO_IFER ( 32 ) /* Input Filter Enable Register */ 275 #define PIO_IFDR ( 36 ) /* Input Filter Disable Register */ 276 #define PIO_IFSR ( 40 ) /* Input Filter Status Register */ 277 #define PIO_SODR ( 48 ) /* Set Output Data Register */ 278 #define PIO_CODR ( 52 ) /* Clear Output Data Register */ 279 #define PIO_ODSR ( 56 ) /* Output Data Status Register */ 280 #define PIO_PDSR ( 60 ) /* Pin Data Status Register */ 281 #define PIO_IER ( 64 ) /* Interrupt Enable Register */ 282 #define PIO_IDR ( 68 ) /* Interrupt Disable Register */ 283 #define PIO_IMR ( 72 ) /* Interrupt Mask Register */ 284 #define PIO_ISR ( 76 ) /* Interrupt Status Register */ 285 #define PIO_MDER ( 80 ) /* Multi-driver Enable Register */ 286 #define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */ 287 #define PIO_MDSR ( 88 ) /* Multi-driver Status Register */ 288 #define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */ 289 #define PIO_PPUER ( 100 ) /* Pull-up Enable Register */ 290 #define PIO_PPUSR ( 104 ) /* Pad Pull-up Status Register */ 291 #define PIO_ASR ( 112 ) /* Select A Register */ 292 #define PIO_BSR ( 116 ) /* Select B Register */ 293 #define PIO_ABSR ( 120 ) /* AB Select Status Register */ 294 #define PIO_OWER ( 160 ) /* Output Write Enable Register */ 295 #define PIO_OWDR ( 164 ) /* Output Write Disable Register */ 296 #define PIO_OWSR ( 168 ) /* Output Write Status Register */ 297 298 /* ***************************************************************************** */ 299 /* SOFTWARE API DEFINITION FOR Clock Generator Controller */ 300 /* ***************************************************************************** */ 301 /* *** Register offset in AT91S_CKGR structure *** */ 302 #define CKGR_MOR ( 0 ) /* Main Oscillator Register */ 303 #define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */ 304 #define CKGR_PLLR ( 12 ) /* PLL Register */ 305 /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ 306 #define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ 307 #define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ 308 #define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ 309 /* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ 310 #define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ 311 #define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */ 312 /* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ 313 #define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */ 314 #define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */ 315 #define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */ 316 #define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */ 317 #define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ 318 #define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ 319 #define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ 320 #define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ 321 #define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ 322 #define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ 323 #define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ 324 #define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ 325 #define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ 326 #define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ 327 328 /* ***************************************************************************** */ 329 /* SOFTWARE API DEFINITION FOR Power Management Controller */ 330 /* ***************************************************************************** */ 331 /* *** Register offset in AT91S_PMC structure *** */ 332 #define PMC_SCER ( 0 ) /* System Clock Enable Register */ 333 #define PMC_SCDR ( 4 ) /* System Clock Disable Register */ 334 #define PMC_SCSR ( 8 ) /* System Clock Status Register */ 335 #define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */ 336 #define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */ 337 #define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */ 338 #define PMC_MOR ( 32 ) /* Main Oscillator Register */ 339 #define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */ 340 #define PMC_PLLR ( 44 ) /* PLL Register */ 341 #define PMC_MCKR ( 48 ) /* Master Clock Register */ 342 #define PMC_PCKR ( 64 ) /* Programmable Clock Register */ 343 #define PMC_IER ( 96 ) /* Interrupt Enable Register */ 344 #define PMC_IDR ( 100 ) /* Interrupt Disable Register */ 345 #define PMC_SR ( 104 ) /* Status Register */ 346 #define PMC_IMR ( 108 ) /* Interrupt Mask Register */ 347 /* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ 348 #define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */ 349 #define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */ 350 #define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */ 351 #define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */ 352 #define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */ 353 #define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */ 354 /* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ 355 /* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ 356 /* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ 357 /* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ 358 /* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ 359 /* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ 360 #define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ 361 #define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */ 362 #define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */ 363 #define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */ 364 #define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ 365 #define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */ 366 #define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ 367 #define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ 368 #define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ 369 #define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ 370 #define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ 371 #define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ 372 /* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ 373 /* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ 374 #define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ 375 #define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ 376 #define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ 377 #define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ 378 #define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ 379 #define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ 380 #define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ 381 /* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ 382 /* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ 383 /* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ 384 385 /* ***************************************************************************** */ 386 /* SOFTWARE API DEFINITION FOR Reset Controller Interface */ 387 /* ***************************************************************************** */ 388 /* *** Register offset in AT91S_RSTC structure *** */ 389 #define RSTC_RCR ( 0 ) /* Reset Control Register */ 390 #define RSTC_RSR ( 4 ) /* Reset Status Register */ 391 #define RSTC_RMR ( 8 ) /* Reset Mode Register */ 392 /* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ 393 #define AT91C_SYSC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */ 394 #define AT91C_SYSC_ICERST ( 0x1 << 1 ) /* (RSTC) ICE Interface Reset */ 395 #define AT91C_SYSC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */ 396 #define AT91C_SYSC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */ 397 #define AT91C_SYSC_KEY ( 0xFF << 24 ) /* (RSTC) Password */ 398 /* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ 399 #define AT91C_SYSC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */ 400 #define AT91C_SYSC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brown-out Detection Status */ 401 #define AT91C_SYSC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */ 402 #define AT91C_SYSC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ 403 #define AT91C_SYSC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ 404 #define AT91C_SYSC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ 405 #define AT91C_SYSC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ 406 #define AT91C_SYSC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brown-out Reset. */ 407 #define AT91C_SYSC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */ 408 #define AT91C_SYSC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ 409 /* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ 410 #define AT91C_SYSC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */ 411 #define AT91C_SYSC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ 412 #define AT91C_SYSC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */ 413 #define AT91C_SYSC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brown-out Detection Interrupt Enable */ 414 415 /* ***************************************************************************** */ 416 /* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ 417 /* ***************************************************************************** */ 418 /* *** Register offset in AT91S_RTTC structure *** */ 419 #define RTTC_RTMR ( 0 ) /* Real-time Mode Register */ 420 #define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */ 421 #define RTTC_RTVR ( 8 ) /* Real-time Value Register */ 422 #define RTTC_RTSR ( 12 ) /* Real-time Status Register */ 423 /* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ 424 #define AT91C_SYSC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ 425 #define AT91C_SYSC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ 426 #define AT91C_SYSC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ 427 #define AT91C_SYSC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ 428 /* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ 429 #define AT91C_SYSC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */ 430 /* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ 431 #define AT91C_SYSC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */ 432 /* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ 433 #define AT91C_SYSC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ 434 #define AT91C_SYSC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ 435 436 /* ***************************************************************************** */ 437 /* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ 438 /* ***************************************************************************** */ 439 /* *** Register offset in AT91S_PITC structure *** */ 440 #define PITC_PIMR ( 0 ) /* Period Interval Mode Register */ 441 #define PITC_PISR ( 4 ) /* Period Interval Status Register */ 442 #define PITC_PIVR ( 8 ) /* Period Interval Value Register */ 443 #define PITC_PIIR ( 12 ) /* Period Interval Image Register */ 444 /* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ 445 #define AT91C_SYSC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ 446 #define AT91C_SYSC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ 447 #define AT91C_SYSC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ 448 /* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ 449 #define AT91C_SYSC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ 450 /* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ 451 #define AT91C_SYSC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ 452 #define AT91C_SYSC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ 453 /* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ 454 455 /* ***************************************************************************** */ 456 /* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ 457 /* ***************************************************************************** */ 458 /* *** Register offset in AT91S_WDTC structure *** */ 459 #define WDTC_WDCR ( 0 ) /* Watchdog Control Register */ 460 #define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */ 461 #define WDTC_WDSR ( 8 ) /* Watchdog Status Register */ 462 /* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ 463 #define AT91C_SYSC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */ 464 /* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ 465 #define AT91C_SYSC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ 466 #define AT91C_SYSC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ 467 #define AT91C_SYSC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ 468 #define AT91C_SYSC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ 469 #define AT91C_SYSC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */ 470 #define AT91C_SYSC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ 471 #define AT91C_SYSC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ 472 #define AT91C_SYSC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ 473 /* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ 474 #define AT91C_SYSC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ 475 #define AT91C_SYSC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */ 476 477 /* ***************************************************************************** */ 478 /* SOFTWARE API DEFINITION FOR Memory Controller Interface */ 479 /* ***************************************************************************** */ 480 /* *** Register offset in AT91S_MC structure *** */ 481 #define MC_RCR ( 0 ) /* MC Remap Control Register */ 482 #define MC_ASR ( 4 ) /* MC Abort Status Register */ 483 #define MC_AASR ( 8 ) /* MC Abort Address Status Register */ 484 #define MC_FMR ( 96 ) /* MC Flash Mode Register */ 485 #define MC_FCR ( 100 ) /* MC Flash Command Register */ 486 #define MC_FSR ( 104 ) /* MC Flash Status Register */ 487 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ 488 #define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ 489 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ 490 #define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ 491 #define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ 492 #define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ 493 #define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ 494 #define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ 495 #define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */ 496 #define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */ 497 #define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */ 498 #define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */ 499 #define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */ 500 #define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */ 501 #define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */ 502 #define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ 503 #define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ 504 /* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ 505 #define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */ 506 #define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */ 507 #define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */ 508 #define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */ 509 #define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */ 510 #define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ 511 #define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ 512 #define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ 513 #define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ 514 #define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ 515 /* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ 516 #define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */ 517 #define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ 518 #define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ 519 #define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ 520 #define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ 521 #define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ 522 #define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */ 523 #define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */ 524 #define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */ 525 #define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */ 526 #define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */ 527 /* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ 528 #define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */ 529 #define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ 530 #define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ 531 #define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ 532 #define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ 533 #define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ 534 #define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ 535 #define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ 536 #define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ 537 #define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ 538 #define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ 539 #define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ 540 #define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ 541 #define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ 542 #define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ 543 #define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ 544 #define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ 545 #define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ 546 #define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ 547 #define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ 548 #define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ 549 #define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ 550 #define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ 551 #define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ 552 #define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ 553 554 /* ***************************************************************************** */ 555 /* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ 556 /* ***************************************************************************** */ 557 /* *** Register offset in AT91S_SPI structure *** */ 558 #define SPI_CR ( 0 ) /* Control Register */ 559 #define SPI_MR ( 4 ) /* Mode Register */ 560 #define SPI_RDR ( 8 ) /* Receive Data Register */ 561 #define SPI_TDR ( 12 ) /* Transmit Data Register */ 562 #define SPI_SR ( 16 ) /* Status Register */ 563 #define SPI_IER ( 20 ) /* Interrupt Enable Register */ 564 #define SPI_IDR ( 24 ) /* Interrupt Disable Register */ 565 #define SPI_IMR ( 28 ) /* Interrupt Mask Register */ 566 #define SPI_CSR ( 48 ) /* Chip Select Register */ 567 #define SPI_RPR ( 256 ) /* Receive Pointer Register */ 568 #define SPI_RCR ( 260 ) /* Receive Counter Register */ 569 #define SPI_TPR ( 264 ) /* Transmit Pointer Register */ 570 #define SPI_TCR ( 268 ) /* Transmit Counter Register */ 571 #define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */ 572 #define SPI_RNCR ( 276 ) /* Receive Next Counter Register */ 573 #define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */ 574 #define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */ 575 #define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */ 576 #define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */ 577 /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ 578 #define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */ 579 #define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */ 580 #define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */ 581 #define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */ 582 /* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ 583 #define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */ 584 #define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */ 585 #define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ 586 #define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ 587 #define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */ 588 #define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */ 589 #define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */ 590 #define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */ 591 #define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */ 592 #define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ 593 /* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ 594 #define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */ 595 #define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ 596 /* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ 597 #define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */ 598 #define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ 599 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ 600 #define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */ 601 #define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ 602 #define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */ 603 #define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */ 604 #define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ 605 #define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ 606 #define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ 607 #define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ 608 #define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */ 609 #define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ 610 #define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */ 611 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ 612 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ 613 /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ 614 /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ 615 #define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */ 616 #define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */ 617 #define AT91C_SPI_CSAAT ( 0x1 << 2 ) /* (SPI) Chip Select Active After Transfer */ 618 #define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */ 619 #define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ 620 #define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ 621 #define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ 622 #define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ 623 #define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ 624 #define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ 625 #define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ 626 #define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ 627 #define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ 628 #define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ 629 #define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */ 630 #define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ 631 632 /* ***************************************************************************** */ 633 /* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ 634 /* ***************************************************************************** */ 635 /* *** Register offset in AT91S_ADC structure *** */ 636 #define ADC_CR ( 0 ) /* ADC Control Register */ 637 #define ADC_MR ( 4 ) /* ADC Mode Register */ 638 #define ADC_CHER ( 16 ) /* ADC Channel Enable Register */ 639 #define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */ 640 #define ADC_CHSR ( 24 ) /* ADC Channel Status Register */ 641 #define ADC_SR ( 28 ) /* ADC Status Register */ 642 #define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */ 643 #define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */ 644 #define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */ 645 #define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */ 646 #define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */ 647 #define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */ 648 #define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */ 649 #define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */ 650 #define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */ 651 #define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */ 652 #define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */ 653 #define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */ 654 #define ADC_RPR ( 256 ) /* Receive Pointer Register */ 655 #define ADC_RCR ( 260 ) /* Receive Counter Register */ 656 #define ADC_TPR ( 264 ) /* Transmit Pointer Register */ 657 #define ADC_TCR ( 268 ) /* Transmit Counter Register */ 658 #define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */ 659 #define ADC_RNCR ( 276 ) /* Receive Next Counter Register */ 660 #define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */ 661 #define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */ 662 #define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */ 663 #define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */ 664 /* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ 665 #define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */ 666 #define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */ 667 /* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ 668 #define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */ 669 #define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ 670 #define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ 671 #define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */ 672 #define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ 673 #define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ 674 #define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ 675 #define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ 676 #define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ 677 #define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ 678 #define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ 679 #define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */ 680 #define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */ 681 #define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */ 682 #define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */ 683 #define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */ 684 #define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */ 685 #define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */ 686 #define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */ 687 #define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */ 688 /* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ 689 #define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */ 690 #define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */ 691 #define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */ 692 #define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */ 693 #define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */ 694 #define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */ 695 #define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */ 696 #define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */ 697 /* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ 698 /* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ 699 /* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ 700 #define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */ 701 #define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */ 702 #define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */ 703 #define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */ 704 #define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */ 705 #define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */ 706 #define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */ 707 #define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */ 708 #define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */ 709 #define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */ 710 #define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */ 711 #define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */ 712 #define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */ 713 #define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */ 714 #define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */ 715 #define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */ 716 #define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */ 717 #define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */ 718 #define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ 719 #define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ 720 /* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ 721 #define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */ 722 /* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ 723 /* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ 724 /* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ 725 /* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ 726 #define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */ 727 /* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ 728 /* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ 729 /* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ 730 /* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ 731 /* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ 732 /* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ 733 /* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ 734 735 /* ***************************************************************************** */ 736 /* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ 737 /* ***************************************************************************** */ 738 /* *** Register offset in AT91S_SSC structure *** */ 739 #define SSC_CR ( 0 ) /* Control Register */ 740 #define SSC_CMR ( 4 ) /* Clock Mode Register */ 741 #define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */ 742 #define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */ 743 #define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */ 744 #define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */ 745 #define SSC_RHR ( 32 ) /* Receive Holding Register */ 746 #define SSC_THR ( 36 ) /* Transmit Holding Register */ 747 #define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */ 748 #define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */ 749 #define SSC_RC0R ( 56 ) /* Receive Compare 0 Register */ 750 #define SSC_RC1R ( 60 ) /* Receive Compare 1 Register */ 751 #define SSC_SR ( 64 ) /* Status Register */ 752 #define SSC_IER ( 68 ) /* Interrupt Enable Register */ 753 #define SSC_IDR ( 72 ) /* Interrupt Disable Register */ 754 #define SSC_IMR ( 76 ) /* Interrupt Mask Register */ 755 #define SSC_RPR ( 256 ) /* Receive Pointer Register */ 756 #define SSC_RCR ( 260 ) /* Receive Counter Register */ 757 #define SSC_TPR ( 264 ) /* Transmit Pointer Register */ 758 #define SSC_TCR ( 268 ) /* Transmit Counter Register */ 759 #define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */ 760 #define SSC_RNCR ( 276 ) /* Receive Next Counter Register */ 761 #define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */ 762 #define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */ 763 #define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */ 764 #define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */ 765 /* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ 766 #define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */ 767 #define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */ 768 #define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */ 769 #define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */ 770 #define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */ 771 /* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ 772 #define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ 773 #define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */ 774 #define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */ 775 #define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */ 776 #define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ 777 #define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ 778 #define AT91C_SSC_CKO_CONTINUOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ 779 #define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ 780 #define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ 781 #define AT91C_SSC_CKG ( 0x3 << 6 ) /* (SSC) Receive/Transmit Clock Gating Selection */ 782 #define AT91C_SSC_CKG_NONE ( 0x0 << 6 ) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */ 783 #define AT91C_SSC_CKG_LOW ( 0x1 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF Low */ 784 #define AT91C_SSC_CKG_HIGH ( 0x2 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF High */ 785 #define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ 786 #define AT91C_SSC_START_CONTINUOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ 787 #define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */ 788 #define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ 789 #define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ 790 #define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ 791 #define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ 792 #define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ 793 #define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ 794 #define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */ 795 #define AT91C_SSC_STOP ( 0x1 << 12 ) /* (SSC) Receive Stop Selection */ 796 #define AT91C_SSC_STTOUT ( 0x1 << 15 ) /* (SSC) Receive/Transmit Start Output Selection */ 797 #define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ 798 #define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ 799 /* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ 800 #define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */ 801 #define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */ 802 #define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */ 803 #define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */ 804 #define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ 805 #define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ 806 #define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ 807 #define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ 808 #define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ 809 #define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ 810 #define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ 811 #define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ 812 #define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ 813 /* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ 814 /* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ 815 #define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */ 816 #define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ 817 /* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ 818 #define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */ 819 #define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */ 820 #define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */ 821 #define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ 822 #define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */ 823 #define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */ 824 #define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */ 825 #define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */ 826 #define AT91C_SSC_CP0 ( 0x1 << 8 ) /* (SSC) Compare 0 */ 827 #define AT91C_SSC_CP1 ( 0x1 << 9 ) /* (SSC) Compare 1 */ 828 #define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */ 829 #define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */ 830 #define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */ 831 #define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */ 832 /* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ 833 /* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ 834 /* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ 835 836 /* ***************************************************************************** */ 837 /* SOFTWARE API DEFINITION FOR Usart */ 838 /* ***************************************************************************** */ 839 /* *** Register offset in AT91S_USART structure *** */ 840 #define US_CR ( 0 ) /* Control Register */ 841 #define US_MR ( 4 ) /* Mode Register */ 842 #define US_IER ( 8 ) /* Interrupt Enable Register */ 843 #define US_IDR ( 12 ) /* Interrupt Disable Register */ 844 #define US_IMR ( 16 ) /* Interrupt Mask Register */ 845 #define US_CSR ( 20 ) /* Channel Status Register */ 846 #define US_RHR ( 24 ) /* Receiver Holding Register */ 847 #define US_THR ( 28 ) /* Transmitter Holding Register */ 848 #define US_BRGR ( 32 ) /* Baud Rate Generator Register */ 849 #define US_RTOR ( 36 ) /* Receiver Time-out Register */ 850 #define US_TTGR ( 40 ) /* Transmitter Time-guard Register */ 851 #define US_FIDI ( 64 ) /* FI_DI_Ratio Register */ 852 #define US_NER ( 68 ) /* Nb Errors Register */ 853 #define US_XXR ( 72 ) /* XON_XOFF Register */ 854 #define US_IF ( 76 ) /* IRDA_FILTER Register */ 855 #define US_RPR ( 256 ) /* Receive Pointer Register */ 856 #define US_RCR ( 260 ) /* Receive Counter Register */ 857 #define US_TPR ( 264 ) /* Transmit Pointer Register */ 858 #define US_TCR ( 268 ) /* Transmit Counter Register */ 859 #define US_RNPR ( 272 ) /* Receive Next Pointer Register */ 860 #define US_RNCR ( 276 ) /* Receive Next Counter Register */ 861 #define US_TNPR ( 280 ) /* Transmit Next Pointer Register */ 862 #define US_TNCR ( 284 ) /* Transmit Next Counter Register */ 863 #define US_PTCR ( 288 ) /* PDC Transfer Control Register */ 864 #define US_PTSR ( 292 ) /* PDC Transfer Status Register */ 865 /* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ 866 #define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (USART) Reset Status Bits */ 867 #define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */ 868 #define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */ 869 #define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */ 870 #define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */ 871 #define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */ 872 #define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ 873 #define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */ 874 #define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ 875 #define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ 876 #define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */ 877 #define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */ 878 /* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ 879 #define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */ 880 #define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */ 881 #define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */ 882 #define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */ 883 #define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */ 884 #define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ 885 #define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ 886 #define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */ 887 #define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */ 888 #define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ 889 #define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */ 890 #define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */ 891 #define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */ 892 #define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */ 893 #define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ 894 #define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */ 895 #define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */ 896 #define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */ 897 #define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */ 898 #define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */ 899 #define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */ 900 #define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */ 901 #define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ 902 #define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */ 903 #define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */ 904 #define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */ 905 #define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */ 906 #define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */ 907 #define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ 908 #define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */ 909 #define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */ 910 #define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */ 911 /* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ 912 #define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */ 913 #define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */ 914 #define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ 915 #define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */ 916 #define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ 917 #define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ 918 #define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */ 919 #define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ 920 /* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ 921 /* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ 922 /* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ 923 #define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */ 924 #define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */ 925 #define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */ 926 #define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */ 927 928 /* ***************************************************************************** */ 929 /* SOFTWARE API DEFINITION FOR Two-wire Interface */ 930 /* ***************************************************************************** */ 931 /* *** Register offset in AT91S_TWI structure *** */ 932 #define TWI_CR ( 0 ) /* Control Register */ 933 #define TWI_MMR ( 4 ) /* Master Mode Register */ 934 #define TWI_SMR ( 8 ) /* Slave Mode Register */ 935 #define TWI_IADR ( 12 ) /* Internal Address Register */ 936 #define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */ 937 #define TWI_SR ( 32 ) /* Status Register */ 938 #define TWI_IER ( 36 ) /* Interrupt Enable Register */ 939 #define TWI_IDR ( 40 ) /* Interrupt Disable Register */ 940 #define TWI_IMR ( 44 ) /* Interrupt Mask Register */ 941 #define TWI_RHR ( 48 ) /* Receive Holding Register */ 942 #define TWI_THR ( 52 ) /* Transmit Holding Register */ 943 /* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ 944 #define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */ 945 #define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */ 946 #define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ 947 #define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ 948 #define AT91C_TWI_SVEN ( 0x1 << 4 ) /* (TWI) TWI Slave Transfer Enabled */ 949 #define AT91C_TWI_SVDIS ( 0x1 << 5 ) /* (TWI) TWI Slave Transfer Disabled */ 950 #define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */ 951 /* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ 952 #define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */ 953 #define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */ 954 #define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */ 955 #define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */ 956 #define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */ 957 #define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */ 958 #define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */ 959 /* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ 960 #define AT91C_TWI_SADR ( 0x7F << 16 ) /* (TWI) Slave Device Address */ 961 /* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ 962 #define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */ 963 #define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */ 964 #define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */ 965 /* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ 966 #define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */ 967 #define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ 968 #define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ 969 #define AT91C_TWI_SVREAD ( 0x1 << 3 ) /* (TWI) Slave Read */ 970 #define AT91C_TWI_SVACC ( 0x1 << 4 ) /* (TWI) Slave Access */ 971 #define AT91C_TWI_GCACC ( 0x1 << 5 ) /* (TWI) General Call Access */ 972 #define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */ 973 #define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */ 974 #define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */ 975 #define AT91C_TWI_ARBLST ( 0x1 << 9 ) /* (TWI) Arbitration Lost */ 976 /* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ 977 /* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ 978 /* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ 979 980 /* ***************************************************************************** */ 981 /* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ 982 /* ***************************************************************************** */ 983 /* *** Register offset in AT91S_TC structure *** */ 984 #define TC_CCR ( 0 ) /* Channel Control Register */ 985 #define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */ 986 #define TC_CV ( 16 ) /* Counter Value */ 987 #define TC_RA ( 20 ) /* Register A */ 988 #define TC_RB ( 24 ) /* Register B */ 989 #define TC_RC ( 28 ) /* Register C */ 990 #define TC_SR ( 32 ) /* Status Register */ 991 #define TC_IER ( 36 ) /* Interrupt Enable Register */ 992 #define TC_IDR ( 40 ) /* Interrupt Disable Register */ 993 #define TC_IMR ( 44 ) /* Interrupt Mask Register */ 994 /* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ 995 #define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ 996 #define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ 997 #define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */ 998 /* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ 999 #define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */ 1000 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ 1001 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ 1002 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ 1003 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ 1004 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ 1005 #define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */ 1006 #define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */ 1007 #define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */ 1008 #define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */ 1009 #define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */ 1010 #define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ 1011 #define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ 1012 #define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ 1013 #define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ 1014 #define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ 1015 #define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ 1016 #define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ 1017 #define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ 1018 #define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ 1019 #define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ 1020 #define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ 1021 #define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ 1022 #define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ 1023 #define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */ 1024 #define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ 1025 #define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ 1026 #define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ 1027 #define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ 1028 #define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ 1029 #define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */ 1030 #define AT91C_TC_EEVT_NONE ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ 1031 #define AT91C_TC_EEVT_RISING ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ 1032 #define AT91C_TC_EEVT_FALLING ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ 1033 #define AT91C_TC_EEVT_BOTH ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ 1034 #define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */ 1035 #define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */ 1036 #define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ 1037 #define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ 1038 #define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ 1039 #define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ 1040 #define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ 1041 #define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */ 1042 #define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */ 1043 #define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */ 1044 #define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ 1045 #define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ 1046 #define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ 1047 #define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ 1048 #define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */ 1049 #define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */ 1050 #define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */ 1051 #define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */ 1052 #define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */ 1053 #define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */ 1054 #define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ 1055 #define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ 1056 #define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ 1057 #define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ 1058 #define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */ 1059 #define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */ 1060 #define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */ 1061 #define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */ 1062 #define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ 1063 #define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */ 1064 #define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */ 1065 #define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */ 1066 #define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */ 1067 #define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ 1068 #define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */ 1069 #define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */ 1070 #define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */ 1071 #define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */ 1072 #define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ 1073 #define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */ 1074 #define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */ 1075 #define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */ 1076 #define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */ 1077 #define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ 1078 #define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */ 1079 #define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */ 1080 #define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */ 1081 #define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */ 1082 #define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ 1083 #define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */ 1084 #define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */ 1085 #define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */ 1086 #define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */ 1087 #define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ 1088 #define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */ 1089 #define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */ 1090 #define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */ 1091 #define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */ 1092 /* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ 1093 #define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */ 1094 #define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */ 1095 #define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */ 1096 #define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */ 1097 #define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */ 1098 #define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */ 1099 #define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */ 1100 #define AT91C_TC_ETRCS ( 0x1 << 7 ) /* (TC) External Trigger */ 1101 #define AT91C_TC_ETRGS ( 0x1 << 16 ) /* (TC) Clock Enabling */ 1102 #define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */ 1103 #define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */ 1104 /* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ 1105 /* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ 1106 /* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ 1107 1108 /* ***************************************************************************** */ 1109 /* SOFTWARE API DEFINITION FOR Timer Counter Interface */ 1110 /* ***************************************************************************** */ 1111 /* *** Register offset in AT91S_TCB structure *** */ 1112 #define TCB_TC0 ( 0 ) /* TC Channel 0 */ 1113 #define TCB_TC1 ( 64 ) /* TC Channel 1 */ 1114 #define TCB_TC2 ( 128 ) /* TC Channel 2 */ 1115 #define TCB_BCR ( 192 ) /* TC Block Control Register */ 1116 #define TCB_BMR ( 196 ) /* TC Block Mode Register */ 1117 /* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ 1118 #define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */ 1119 /* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ 1120 #define AT91C_TCB_TC0XC0S ( 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */ 1121 #define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */ 1122 #define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */ 1123 #define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */ 1124 #define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */ 1125 #define AT91C_TCB_TC1XC1S ( 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */ 1126 #define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ 1127 #define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ 1128 #define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ 1129 #define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ 1130 #define AT91C_TCB_TC2XC2S ( 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */ 1131 #define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ 1132 #define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ 1133 #define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ 1134 #define AT91C_TCB_TC2XC2S_TIOA2 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ 1135 1136 /* ***************************************************************************** */ 1137 /* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ 1138 /* ***************************************************************************** */ 1139 /* *** Register offset in AT91S_PWMC_CH structure *** */ 1140 #define PWMC_CMR ( 0 ) /* Channel Mode Register */ 1141 #define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */ 1142 #define PWMC_CPRDR ( 8 ) /* Channel Period Register */ 1143 #define PWMC_CCNTR ( 12 ) /* Channel Counter Register */ 1144 #define PWMC_CUPDR ( 16 ) /* Channel Update Register */ 1145 #define PWMC_Reserved ( 20 ) /* Reserved */ 1146 /* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ 1147 #define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ 1148 #define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */ 1149 #define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */ 1150 #define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */ 1151 #define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ 1152 #define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ 1153 #define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ 1154 /* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ 1155 #define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ 1156 /* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ 1157 #define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */ 1158 /* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ 1159 #define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ 1160 /* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ 1161 #define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */ 1162 1163 /* ***************************************************************************** */ 1164 /* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ 1165 /* ***************************************************************************** */ 1166 /* *** Register offset in AT91S_PWMC structure *** */ 1167 #define PWMC_MR ( 0 ) /* PWMC Mode Register */ 1168 #define PWMC_ENA ( 4 ) /* PWMC Enable Register */ 1169 #define PWMC_DIS ( 8 ) /* PWMC Disable Register */ 1170 #define PWMC_SR ( 12 ) /* PWMC Status Register */ 1171 #define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */ 1172 #define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */ 1173 #define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */ 1174 #define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */ 1175 #define PWMC_VR ( 252 ) /* PWMC Version Register */ 1176 #define PWMC_CH ( 512 ) /* PWMC Channel 0 */ 1177 /* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ 1178 #define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ 1179 #define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ 1180 #define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */ 1181 #define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ 1182 #define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ 1183 #define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */ 1184 /* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ 1185 #define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */ 1186 #define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */ 1187 #define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */ 1188 #define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */ 1189 #define AT91C_PWMC_CHID4 ( 0x1 << 4 ) /* (PWMC) Channel ID 4 */ 1190 #define AT91C_PWMC_CHID5 ( 0x1 << 5 ) /* (PWMC) Channel ID 5 */ 1191 #define AT91C_PWMC_CHID6 ( 0x1 << 6 ) /* (PWMC) Channel ID 6 */ 1192 #define AT91C_PWMC_CHID7 ( 0x1 << 7 ) /* (PWMC) Channel ID 7 */ 1193 /* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ 1194 /* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ 1195 /* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ 1196 /* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ 1197 /* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ 1198 /* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ 1199 1200 /* ***************************************************************************** */ 1201 /* SOFTWARE API DEFINITION FOR USB Device Interface */ 1202 /* ***************************************************************************** */ 1203 /* *** Register offset in AT91S_UDP structure *** */ 1204 #define UDP_NUM ( 0 ) /* Frame Number Register */ 1205 #define UDP_GLBSTATE ( 4 ) /* Global State Register */ 1206 #define UDP_FADDR ( 8 ) /* Function Address Register */ 1207 #define UDP_IER ( 16 ) /* Interrupt Enable Register */ 1208 #define UDP_IDR ( 20 ) /* Interrupt Disable Register */ 1209 #define UDP_IMR ( 24 ) /* Interrupt Mask Register */ 1210 #define UDP_ISR ( 28 ) /* Interrupt Status Register */ 1211 #define UDP_ICR ( 32 ) /* Interrupt Clear Register */ 1212 #define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */ 1213 #define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */ 1214 #define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */ 1215 /* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ 1216 #define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ 1217 #define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */ 1218 #define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */ 1219 /* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ 1220 #define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */ 1221 #define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */ 1222 #define AT91C_UDP_RMWUPE ( 0x1 << 2 ) /* (UDP) Remote Wake Up Enable */ 1223 #define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ 1224 /* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ 1225 #define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */ 1226 #define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */ 1227 /* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ 1228 #define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ 1229 #define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ 1230 #define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ 1231 #define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ 1232 #define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ 1233 #define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ 1234 #define AT91C_UDP_EPINT6 ( 0x1 << 6 ) /* (UDP) Endpoint 6 Interrupt */ 1235 #define AT91C_UDP_EPINT7 ( 0x1 << 7 ) /* (UDP) Endpoint 7 Interrupt */ 1236 #define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ 1237 #define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ 1238 #define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ 1239 #define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ 1240 #define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ 1241 /* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ 1242 /* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ 1243 /* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ 1244 #define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ 1245 /* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ 1246 /* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ 1247 #define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ 1248 #define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ 1249 #define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ 1250 #define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ 1251 #define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ 1252 #define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ 1253 #define AT91C_UDP_EP6 ( 0x1 << 6 ) /* (UDP) Reset Endpoint 6 */ 1254 #define AT91C_UDP_EP7 ( 0x1 << 7 ) /* (UDP) Reset Endpoint 7 */ 1255 /* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ 1256 #define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ 1257 #define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ 1258 #define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ 1259 #define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ 1260 #define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ 1261 #define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ 1262 #define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ 1263 #define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */ 1264 #define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */ 1265 #define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */ 1266 #define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */ 1267 #define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */ 1268 #define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */ 1269 #define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */ 1270 #define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */ 1271 #define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */ 1272 #define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */ 1273 #define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ 1274 #define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ 1275 1276 /* ***************************************************************************** */ 1277 /* REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */ 1278 /* ***************************************************************************** */ 1279 /* ========== Register definition for SYSC peripheral ========== */ 1280 #define AT91C_SYSC_SYSC_VRPM ( 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */ 1281 /* ========== Register definition for AIC peripheral ========== */ 1282 #define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ 1283 #define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ 1284 #define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */ 1285 #define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ 1286 #define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ 1287 #define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ 1288 #define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ 1289 #define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */ 1290 #define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ 1291 #define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ 1292 #define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ 1293 #define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ 1294 #define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ 1295 #define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ 1296 #define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ 1297 #define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ 1298 #define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ 1299 #define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ 1300 /* ========== Register definition for DBGU peripheral ========== */ 1301 #define AT91C_DBGU_C2R ( 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */ 1302 #define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ 1303 #define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */ 1304 #define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ 1305 #define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */ 1306 #define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ 1307 #define AT91C_DBGU_C1R ( 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */ 1308 #define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ 1309 #define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ 1310 #define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ 1311 #define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ 1312 #define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */ 1313 /* ========== Register definition for PDC_DBGU peripheral ========== */ 1314 #define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ 1315 #define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ 1316 #define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ 1317 #define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ 1318 #define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ 1319 #define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ 1320 #define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ 1321 #define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ 1322 #define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ 1323 #define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ 1324 /* ========== Register definition for PIOA peripheral ========== */ 1325 #define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ 1326 #define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ 1327 #define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ 1328 #define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ 1329 #define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ 1330 #define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ 1331 #define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ 1332 #define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ 1333 #define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */ 1334 #define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */ 1335 #define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */ 1336 #define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ 1337 #define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ 1338 #define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ 1339 #define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ 1340 #define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ 1341 #define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ 1342 #define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */ 1343 #define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */ 1344 #define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ 1345 #define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ 1346 #define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ 1347 #define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ 1348 #define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */ 1349 #define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ 1350 #define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ 1351 #define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ 1352 #define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ 1353 #define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ 1354 /* ========== Register definition for CKGR peripheral ========== */ 1355 #define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */ 1356 #define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ 1357 #define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ 1358 /* ========== Register definition for PMC peripheral ========== */ 1359 #define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ 1360 #define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ 1361 #define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ 1362 #define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ 1363 #define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ 1364 #define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ 1365 #define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */ 1366 #define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ 1367 #define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */ 1368 #define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ 1369 #define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ 1370 #define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ 1371 #define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */ 1372 #define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ 1373 #define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ 1374 /* ========== Register definition for RSTC peripheral ========== */ 1375 #define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ 1376 #define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ 1377 #define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ 1378 /* ========== Register definition for RTTC peripheral ========== */ 1379 #define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ 1380 #define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ 1381 #define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ 1382 #define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ 1383 /* ========== Register definition for PITC peripheral ========== */ 1384 #define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ 1385 #define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ 1386 #define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ 1387 #define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ 1388 /* ========== Register definition for WDTC peripheral ========== */ 1389 #define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ 1390 #define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ 1391 #define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ 1392 /* ========== Register definition for MC peripheral ========== */ 1393 #define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ 1394 #define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ 1395 #define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ 1396 #define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ 1397 #define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ 1398 #define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ 1399 /* ========== Register definition for PDC_SPI peripheral ========== */ 1400 #define AT91C_SPI_PTCR ( 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */ 1401 #define AT91C_SPI_TNPR ( 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */ 1402 #define AT91C_SPI_RNPR ( 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */ 1403 #define AT91C_SPI_TPR ( 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */ 1404 #define AT91C_SPI_RPR ( 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */ 1405 #define AT91C_SPI_PTSR ( 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */ 1406 #define AT91C_SPI_TNCR ( 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */ 1407 #define AT91C_SPI_RNCR ( 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */ 1408 #define AT91C_SPI_TCR ( 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */ 1409 #define AT91C_SPI_RCR ( 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */ 1410 /* ========== Register definition for SPI peripheral ========== */ 1411 #define AT91C_SPI_CSR ( 0xFFFE0030 ) /* (SPI) Chip Select Register */ 1412 #define AT91C_SPI_IDR ( 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */ 1413 #define AT91C_SPI_SR ( 0xFFFE0010 ) /* (SPI) Status Register */ 1414 #define AT91C_SPI_RDR ( 0xFFFE0008 ) /* (SPI) Receive Data Register */ 1415 #define AT91C_SPI_CR ( 0xFFFE0000 ) /* (SPI) Control Register */ 1416 #define AT91C_SPI_IMR ( 0xFFFE001C ) /* (SPI) Interrupt Mask Register */ 1417 #define AT91C_SPI_IER ( 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */ 1418 #define AT91C_SPI_TDR ( 0xFFFE000C ) /* (SPI) Transmit Data Register */ 1419 #define AT91C_SPI_MR ( 0xFFFE0004 ) /* (SPI) Mode Register */ 1420 /* ========== Register definition for PDC_ADC peripheral ========== */ 1421 #define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ 1422 #define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ 1423 #define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ 1424 #define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ 1425 #define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ 1426 #define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ 1427 #define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ 1428 #define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ 1429 #define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ 1430 #define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ 1431 /* ========== Register definition for ADC peripheral ========== */ 1432 #define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ 1433 #define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ 1434 #define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ 1435 #define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ 1436 #define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ 1437 #define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ 1438 #define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ 1439 #define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ 1440 #define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */ 1441 #define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ 1442 #define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */ 1443 #define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ 1444 #define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ 1445 #define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ 1446 #define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */ 1447 #define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ 1448 #define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ 1449 #define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ 1450 /* ========== Register definition for PDC_SSC peripheral ========== */ 1451 #define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ 1452 #define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ 1453 #define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ 1454 #define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ 1455 #define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ 1456 #define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ 1457 #define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ 1458 #define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ 1459 #define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ 1460 #define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ 1461 /* ========== Register definition for SSC peripheral ========== */ 1462 #define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ 1463 #define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */ 1464 #define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ 1465 #define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */ 1466 #define AT91C_SSC_RC0R ( 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */ 1467 #define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ 1468 #define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */ 1469 #define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ 1470 #define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ 1471 #define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */ 1472 #define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ 1473 #define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ 1474 #define AT91C_SSC_RC1R ( 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */ 1475 #define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ 1476 #define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ 1477 #define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ 1478 /* ========== Register definition for PDC_US1 peripheral ========== */ 1479 #define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ 1480 #define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ 1481 #define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ 1482 #define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ 1483 #define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ 1484 #define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ 1485 #define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ 1486 #define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ 1487 #define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ 1488 #define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ 1489 /* ========== Register definition for US1 peripheral ========== */ 1490 #define AT91C_US1_XXR ( 0xFFFC4048 ) /* (US1) XON_XOFF Register */ 1491 #define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */ 1492 #define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ 1493 #define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ 1494 #define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */ 1495 #define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ 1496 #define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */ 1497 #define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */ 1498 #define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */ 1499 #define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ 1500 #define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ 1501 #define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ 1502 #define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ 1503 #define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */ 1504 #define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */ 1505 /* ========== Register definition for PDC_US0 peripheral ========== */ 1506 #define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ 1507 #define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ 1508 #define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ 1509 #define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ 1510 #define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ 1511 #define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ 1512 #define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ 1513 #define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ 1514 #define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ 1515 #define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ 1516 /* ========== Register definition for US0 peripheral ========== */ 1517 #define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ 1518 #define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ 1519 #define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */ 1520 #define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ 1521 #define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */ 1522 #define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ 1523 #define AT91C_US0_XXR ( 0xFFFC0048 ) /* (US0) XON_XOFF Register */ 1524 #define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ 1525 #define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */ 1526 #define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ 1527 #define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ 1528 #define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */ 1529 #define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */ 1530 #define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */ 1531 #define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */ 1532 /* ========== Register definition for TWI peripheral ========== */ 1533 #define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */ 1534 #define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ 1535 #define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */ 1536 #define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ 1537 #define AT91C_TWI_SMR ( 0xFFFB8008 ) /* (TWI) Slave Mode Register */ 1538 #define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */ 1539 #define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ 1540 #define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ 1541 #define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ 1542 #define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */ 1543 #define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */ 1544 /* ========== Register definition for TC2 peripheral ========== */ 1545 #define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ 1546 #define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ 1547 #define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */ 1548 #define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */ 1549 #define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ 1550 #define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ 1551 #define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */ 1552 #define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */ 1553 #define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */ 1554 #define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */ 1555 /* ========== Register definition for TC1 peripheral ========== */ 1556 #define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ 1557 #define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ 1558 #define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */ 1559 #define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */ 1560 #define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ 1561 #define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ 1562 #define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */ 1563 #define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */ 1564 #define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */ 1565 #define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */ 1566 /* ========== Register definition for TC0 peripheral ========== */ 1567 #define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ 1568 #define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ 1569 #define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */ 1570 #define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */ 1571 #define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ 1572 #define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ 1573 #define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */ 1574 #define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */ 1575 #define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */ 1576 #define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */ 1577 /* ========== Register definition for TCB peripheral ========== */ 1578 #define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ 1579 #define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ 1580 /* ========== Register definition for PWMC_CH3 peripheral ========== */ 1581 #define AT91C_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ 1582 #define AT91C_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ 1583 #define AT91C_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ 1584 #define AT91C_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ 1585 #define AT91C_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ 1586 #define AT91C_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ 1587 /* ========== Register definition for PWMC_CH2 peripheral ========== */ 1588 #define AT91C_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ 1589 #define AT91C_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ 1590 #define AT91C_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ 1591 #define AT91C_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ 1592 #define AT91C_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ 1593 #define AT91C_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ 1594 /* ========== Register definition for PWMC_CH1 peripheral ========== */ 1595 #define AT91C_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ 1596 #define AT91C_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ 1597 #define AT91C_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ 1598 #define AT91C_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ 1599 #define AT91C_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ 1600 #define AT91C_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ 1601 /* ========== Register definition for PWMC_CH0 peripheral ========== */ 1602 #define AT91C_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ 1603 #define AT91C_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ 1604 #define AT91C_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ 1605 #define AT91C_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ 1606 #define AT91C_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ 1607 #define AT91C_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ 1608 /* ========== Register definition for PWMC peripheral ========== */ 1609 #define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ 1610 #define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ 1611 #define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ 1612 #define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ 1613 #define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ 1614 #define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ 1615 #define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ 1616 #define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ 1617 #define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ 1618 /* ========== Register definition for UDP peripheral ========== */ 1619 #define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */ 1620 #define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ 1621 #define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */ 1622 #define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ 1623 #define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ 1624 #define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ 1625 #define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ 1626 #define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ 1627 #define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ 1628 #define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */ 1629 #define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */ 1630 1631 /* ***************************************************************************** */ 1632 /* PIO DEFINITIONS FOR AT91SAM7S64 */ 1633 /* ***************************************************************************** */ 1634 #define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */ 1635 #define AT91C_PA0_PWM0 ( AT91C_PIO_PA0 ) /* PWM Channel 0 */ 1636 #define AT91C_PA0_TIOA0 ( AT91C_PIO_PA0 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ 1637 #define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */ 1638 #define AT91C_PA1_PWM1 ( AT91C_PIO_PA1 ) /* PWM Channel 1 */ 1639 #define AT91C_PA1_TIOB0 ( AT91C_PIO_PA1 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ 1640 #define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */ 1641 #define AT91C_PA10_DTXD ( AT91C_PIO_PA10 ) /* DBGU Debug Transmit Data */ 1642 #define AT91C_PA10_NPCS2 ( AT91C_PIO_PA10 ) /* SPI Peripheral Chip Select 2 */ 1643 #define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */ 1644 #define AT91C_PA11_NPCS0 ( AT91C_PIO_PA11 ) /* SPI Peripheral Chip Select 0 */ 1645 #define AT91C_PA11_PWM0 ( AT91C_PIO_PA11 ) /* PWM Channel 0 */ 1646 #define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */ 1647 #define AT91C_PA12_MISO ( AT91C_PIO_PA12 ) /* SPI Master In Slave */ 1648 #define AT91C_PA12_PWM1 ( AT91C_PIO_PA12 ) /* PWM Channel 1 */ 1649 #define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */ 1650 #define AT91C_PA13_MOSI ( AT91C_PIO_PA13 ) /* SPI Master Out Slave */ 1651 #define AT91C_PA13_PWM2 ( AT91C_PIO_PA13 ) /* PWM Channel 2 */ 1652 #define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */ 1653 #define AT91C_PA14_SPCK ( AT91C_PIO_PA14 ) /* SPI Serial Clock */ 1654 #define AT91C_PA14_PWM3 ( AT91C_PIO_PA14 ) /* PWM Channel 3 */ 1655 #define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */ 1656 #define AT91C_PA15_TF ( AT91C_PIO_PA15 ) /* SSC Transmit Frame Sync */ 1657 #define AT91C_PA15_TIOA1 ( AT91C_PIO_PA15 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ 1658 #define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */ 1659 #define AT91C_PA16_TK ( AT91C_PIO_PA16 ) /* SSC Transmit Clock */ 1660 #define AT91C_PA16_TIOB1 ( AT91C_PIO_PA16 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ 1661 #define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */ 1662 #define AT91C_PA17_TD ( AT91C_PIO_PA17 ) /* SSC Transmit data */ 1663 #define AT91C_PA17_PCK1 ( AT91C_PIO_PA17 ) /* PMC Programmable Clock Output 1 */ 1664 #define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */ 1665 #define AT91C_PA18_RD ( AT91C_PIO_PA18 ) /* SSC Receive Data */ 1666 #define AT91C_PA18_PCK2 ( AT91C_PIO_PA18 ) /* PMC Programmable Clock Output 2 */ 1667 #define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */ 1668 #define AT91C_PA19_RK ( AT91C_PIO_PA19 ) /* SSC Receive Clock */ 1669 #define AT91C_PA19_FIQ ( AT91C_PIO_PA19 ) /* AIC Fast Interrupt Input */ 1670 #define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */ 1671 #define AT91C_PA2_PWM2 ( AT91C_PIO_PA2 ) /* PWM Channel 2 */ 1672 #define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ 1673 #define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */ 1674 #define AT91C_PA20_RF ( AT91C_PIO_PA20 ) /* SSC Receive Frame Sync */ 1675 #define AT91C_PA20_IRQ0 ( AT91C_PIO_PA20 ) /* External Interrupt 0 */ 1676 #define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */ 1677 #define AT91C_PA21_RXD1 ( AT91C_PIO_PA21 ) /* USART 1 Receive Data */ 1678 #define AT91C_PA21_PCK1 ( AT91C_PIO_PA21 ) /* PMC Programmable Clock Output 1 */ 1679 #define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */ 1680 #define AT91C_PA22_TXD1 ( AT91C_PIO_PA22 ) /* USART 1 Transmit Data */ 1681 #define AT91C_PA22_NPCS3 ( AT91C_PIO_PA22 ) /* SPI Peripheral Chip Select 3 */ 1682 #define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */ 1683 #define AT91C_PA23_SCK1 ( AT91C_PIO_PA23 ) /* USART 1 Serial Clock */ 1684 #define AT91C_PA23_PWM0 ( AT91C_PIO_PA23 ) /* PWM Channel 0 */ 1685 #define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */ 1686 #define AT91C_PA24_RTS1 ( AT91C_PIO_PA24 ) /* USART 1 Ready To Send */ 1687 #define AT91C_PA24_PWM1 ( AT91C_PIO_PA24 ) /* PWM Channel 1 */ 1688 #define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */ 1689 #define AT91C_PA25_CTS1 ( AT91C_PIO_PA25 ) /* USART 1 Clear To Send */ 1690 #define AT91C_PA25_PWM2 ( AT91C_PIO_PA25 ) /* PWM Channel 2 */ 1691 #define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */ 1692 #define AT91C_PA26_DCD1 ( AT91C_PIO_PA26 ) /* USART 1 Data Carrier Detect */ 1693 #define AT91C_PA26_TIOA2 ( AT91C_PIO_PA26 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ 1694 #define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */ 1695 #define AT91C_PA27_DTR1 ( AT91C_PIO_PA27 ) /* USART 1 Data Terminal ready */ 1696 #define AT91C_PA27_TIOB2 ( AT91C_PIO_PA27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ 1697 #define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */ 1698 #define AT91C_PA28_DSR1 ( AT91C_PIO_PA28 ) /* USART 1 Data Set ready */ 1699 #define AT91C_PA28_TCLK1 ( AT91C_PIO_PA28 ) /* Timer Counter 1 external clock input */ 1700 #define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */ 1701 #define AT91C_PA29_RI1 ( AT91C_PIO_PA29 ) /* USART 1 Ring Indicator */ 1702 #define AT91C_PA29_TCLK2 ( AT91C_PIO_PA29 ) /* Timer Counter 2 external clock input */ 1703 #define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */ 1704 #define AT91C_PA3_TWD ( AT91C_PIO_PA3 ) /* TWI Two-wire Serial Data */ 1705 #define AT91C_PA3_NPCS3 ( AT91C_PIO_PA3 ) /* SPI Peripheral Chip Select 3 */ 1706 #define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */ 1707 #define AT91C_PA30_IRQ1 ( AT91C_PIO_PA30 ) /* External Interrupt 1 */ 1708 #define AT91C_PA30_NPCS2 ( AT91C_PIO_PA30 ) /* SPI Peripheral Chip Select 2 */ 1709 #define AT91C_PIO_PA31 ( 1 << 31 ) /* Pin Controlled by PA31 */ 1710 #define AT91C_PA31_NPCS1 ( AT91C_PIO_PA31 ) /* SPI Peripheral Chip Select 1 */ 1711 #define AT91C_PA31_PCK2 ( AT91C_PIO_PA31 ) /* PMC Programmable Clock Output 2 */ 1712 #define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */ 1713 #define AT91C_PA4_TWCK ( AT91C_PIO_PA4 ) /* TWI Two-wire Serial Clock */ 1714 #define AT91C_PA4_TCLK0 ( AT91C_PIO_PA4 ) /* Timer Counter 0 external clock input */ 1715 #define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */ 1716 #define AT91C_PA5_RXD0 ( AT91C_PIO_PA5 ) /* USART 0 Receive Data */ 1717 #define AT91C_PA5_NPCS3 ( AT91C_PIO_PA5 ) /* SPI Peripheral Chip Select 3 */ 1718 #define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */ 1719 #define AT91C_PA6_TXD0 ( AT91C_PIO_PA6 ) /* USART 0 Transmit Data */ 1720 #define AT91C_PA6_PCK0 ( AT91C_PIO_PA6 ) /* PMC Programmable Clock Output 0 */ 1721 #define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */ 1722 #define AT91C_PA7_RTS0 ( AT91C_PIO_PA7 ) /* USART 0 Ready To Send */ 1723 #define AT91C_PA7_PWM3 ( AT91C_PIO_PA7 ) /* PWM Channel 3 */ 1724 #define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */ 1725 #define AT91C_PA8_CTS0 ( AT91C_PIO_PA8 ) /* USART 0 Clear To Send */ 1726 #define AT91C_PA8_ADTRG ( AT91C_PIO_PA8 ) /* ADC External Trigger */ 1727 #define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */ 1728 #define AT91C_PA9_DRXD ( AT91C_PIO_PA9 ) /* DBGU Debug Receive Data */ 1729 #define AT91C_PA9_NPCS1 ( AT91C_PIO_PA9 ) /* SPI Peripheral Chip Select 1 */ 1730 1731 /* ***************************************************************************** */ 1732 /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ 1733 /* ***************************************************************************** */ 1734 #define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */ 1735 #define AT91C_ID_SYS ( 1 ) /* System Peripheral */ 1736 #define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller */ 1737 #define AT91C_ID_3_Reserved ( 3 ) /* Reserved */ 1738 #define AT91C_ID_ADC ( 4 ) /* Analog-to-Digital Converter */ 1739 #define AT91C_ID_SPI ( 5 ) /* Serial Peripheral Interface */ 1740 #define AT91C_ID_US0 ( 6 ) /* USART 0 */ 1741 #define AT91C_ID_US1 ( 7 ) /* USART 1 */ 1742 #define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */ 1743 #define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */ 1744 #define AT91C_ID_PWMC ( 10 ) /* PWM Controller */ 1745 #define AT91C_ID_UDP ( 11 ) /* USB Device Port */ 1746 #define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */ 1747 #define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */ 1748 #define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */ 1749 #define AT91C_ID_15_Reserved ( 15 ) /* Reserved */ 1750 #define AT91C_ID_16_Reserved ( 16 ) /* Reserved */ 1751 #define AT91C_ID_17_Reserved ( 17 ) /* Reserved */ 1752 #define AT91C_ID_18_Reserved ( 18 ) /* Reserved */ 1753 #define AT91C_ID_19_Reserved ( 19 ) /* Reserved */ 1754 #define AT91C_ID_20_Reserved ( 20 ) /* Reserved */ 1755 #define AT91C_ID_21_Reserved ( 21 ) /* Reserved */ 1756 #define AT91C_ID_22_Reserved ( 22 ) /* Reserved */ 1757 #define AT91C_ID_23_Reserved ( 23 ) /* Reserved */ 1758 #define AT91C_ID_24_Reserved ( 24 ) /* Reserved */ 1759 #define AT91C_ID_25_Reserved ( 25 ) /* Reserved */ 1760 #define AT91C_ID_26_Reserved ( 26 ) /* Reserved */ 1761 #define AT91C_ID_27_Reserved ( 27 ) /* Reserved */ 1762 #define AT91C_ID_28_Reserved ( 28 ) /* Reserved */ 1763 #define AT91C_ID_29_Reserved ( 29 ) /* Reserved */ 1764 #define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */ 1765 #define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */ 1766 1767 /* ***************************************************************************** */ 1768 /* BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */ 1769 /* ***************************************************************************** */ 1770 #define AT91C_BASE_SYSC ( 0xFFFFF000 ) /* (SYSC) Base Address */ 1771 #define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */ 1772 #define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */ 1773 #define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ 1774 #define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */ 1775 #define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */ 1776 #define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */ 1777 #define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */ 1778 #define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */ 1779 #define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */ 1780 #define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */ 1781 #define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */ 1782 #define AT91C_BASE_PDC_SPI ( 0xFFFE0100 ) /* (PDC_SPI) Base Address */ 1783 #define AT91C_BASE_SPI ( 0xFFFE0000 ) /* (SPI) Base Address */ 1784 #define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */ 1785 #define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */ 1786 #define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */ 1787 #define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */ 1788 #define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */ 1789 #define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */ 1790 #define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */ 1791 #define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */ 1792 #define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */ 1793 #define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */ 1794 #define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */ 1795 #define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */ 1796 #define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */ 1797 #define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ 1798 #define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ 1799 #define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ 1800 #define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ 1801 #define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */ 1802 #define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */ 1803 1804 /* ***************************************************************************** */ 1805 /* MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */ 1806 /* ***************************************************************************** */ 1807 #define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */ 1808 #define AT91C_ISRAM_SIZE ( 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */ 1809 #define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */ 1810 #define AT91C_IFLASH_SIZE ( 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */ 1811
