1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31
32 /* Scheduler includes. */
33 #include "FreeRTOS.h"
34 #include "task.h"
35
36 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
37 #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
38 #endif
39
40 #ifndef configSETUP_TICK_INTERRUPT
41 #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
42 #endif /* configSETUP_TICK_INTERRUPT */
43
44 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
45 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
46 #endif
47
48 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
49 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
50 #endif
51
52 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
53 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
54 #endif
55
56 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
57 /* Check the configuration. */
58 #if ( configMAX_PRIORITIES > 32 )
59 #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
60 #endif
61 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
62
63 /* In case security extensions are implemented. */
64 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
65 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
66 #endif
67
68 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
69 * portmacro.h. */
70 #ifndef configCLEAR_TICK_INTERRUPT
71 #define configCLEAR_TICK_INTERRUPT()
72 #endif
73
74 /* A critical section is exited when the critical section nesting count reaches
75 * this value. */
76 #define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
77
78 /* In all GICs 255 can be written to the priority mask register to unmask all
79 * (but the lowest) interrupt priority. */
80 #define portUNMASK_VALUE ( 0xFFUL )
81
82 /* Tasks are not created with a floating point context, but can be given a
83 * floating point context after they have been created. A variable is stored as
84 * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
85 * does not have an FPU context, or any other value if the task does have an FPU
86 * context. */
87 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
88
89 /* Constants required to setup the initial task context. */
90 #define portSP_ELx ( ( StackType_t ) 0x01 )
91 #define portSP_EL0 ( ( StackType_t ) 0x00 )
92
93 #if defined( GUEST )
94 #define portEL1 ( ( StackType_t ) 0x04 )
95 #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
96 #else
97 #define portEL3 ( ( StackType_t ) 0x0c )
98 /* At the time of writing, the BSP only supports EL3. */
99 #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
100 #endif
101
102 /* Masks all bits in the APSR other than the mode bits. */
103 #define portAPSR_MODE_BITS_MASK ( 0x0C )
104
105 /* The I bit in the DAIF bits. */
106 #define portDAIF_I ( 0x80 )
107
108 /* Macro to unmask all interrupt priorities. */
109 /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
110 #define portCLEAR_INTERRUPT_MASK() \
111 { \
112 __asm volatile ( "MSR DAIFSET, #2 \n" \
113 "DSB SY \n" \
114 "ISB SY \n" \
115 "MSR s3_0_c4_c6_0, %0 \n" \
116 "DSB SY \n" \
117 "ISB SY \n" \
118 "MSR DAIFCLR, #2 \n" \
119 "DSB SY \n" \
120 "ISB SY \n" \
121 ::"r" ( portUNMASK_VALUE ) ); \
122 }
123
124 /*-----------------------------------------------------------*/
125
126 /*
127 * Starts the first task executing. This function is necessarily written in
128 * assembly code so is implemented in portASM.s.
129 */
130 extern void vPortRestoreTaskContext( void );
131
132 /*-----------------------------------------------------------*/
133
134 /* A variable is used to keep track of the critical section nesting. This
135 * variable has to be stored as part of the task context and must be initialised to
136 * a non zero value to ensure interrupts don't inadvertently become unmasked before
137 * the scheduler starts. As it is stored as part of the task context it will
138 * automatically be set to 0 when the first task is started. */
139 volatile uint64_t ullCriticalNesting = 9999ULL;
140
141 /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
142 * then floating point context must be saved and restored for the task. */
143 uint64_t ullPortTaskHasFPUContext = pdFALSE;
144
145 /* Set to 1 to pend a context switch from an ISR. */
146 uint64_t ullPortYieldRequired = pdFALSE;
147
148 /* Counts the interrupt nesting depth. A context switch is only performed if
149 * if the nesting depth is 0. */
150 uint64_t ullPortInterruptNesting = 0;
151
152 /* Used in the ASM code. */
153 __attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
154
155 /*-----------------------------------------------------------*/
156
157 /*
158 * See header file for description.
159 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)160 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
161 TaskFunction_t pxCode,
162 void * pvParameters )
163 {
164 /* Setup the initial stack of the task. The stack is set exactly as
165 * expected by the portRESTORE_CONTEXT() macro. */
166
167 /* First all the general purpose registers. */
168 pxTopOfStack--;
169 *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
170 pxTopOfStack--;
171 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
172 pxTopOfStack--;
173 *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
174 pxTopOfStack--;
175 *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
176 pxTopOfStack--;
177 *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
178 pxTopOfStack--;
179 *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
180 pxTopOfStack--;
181 *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
182 pxTopOfStack--;
183 *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
184 pxTopOfStack--;
185 *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
186 pxTopOfStack--;
187 *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
188 pxTopOfStack--;
189 *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
190 pxTopOfStack--;
191 *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
192 pxTopOfStack--;
193 *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
194 pxTopOfStack--;
195 *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
196 pxTopOfStack--;
197 *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
198 pxTopOfStack--;
199 *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
200 pxTopOfStack--;
201 *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
202 pxTopOfStack--;
203 *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
204 pxTopOfStack--;
205 *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
206 pxTopOfStack--;
207 *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
208 pxTopOfStack--;
209 *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
210 pxTopOfStack--;
211 *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
212 pxTopOfStack--;
213 *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
214 pxTopOfStack--;
215 *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
216 pxTopOfStack--;
217 *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
218 pxTopOfStack--;
219 *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
220 pxTopOfStack--;
221 *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
222 pxTopOfStack--;
223 *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
224 pxTopOfStack--;
225 *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
226 pxTopOfStack--;
227 *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
228 pxTopOfStack--;
229 *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
230 pxTopOfStack--;
231 *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
232 pxTopOfStack--;
233
234 *pxTopOfStack = portINITIAL_PSTATE;
235 pxTopOfStack--;
236
237 *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
238 pxTopOfStack--;
239
240 /* The task will start with a critical nesting count of 0 as interrupts are
241 * enabled. */
242 *pxTopOfStack = portNO_CRITICAL_NESTING;
243 pxTopOfStack--;
244
245 /* The task will start without a floating point context. A task that uses
246 * the floating point hardware must call vPortTaskUsesFPU() before executing
247 * any floating point instructions. */
248 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
249
250 return pxTopOfStack;
251 }
252 /*-----------------------------------------------------------*/
253
xPortStartScheduler(void)254 BaseType_t xPortStartScheduler( void )
255 {
256 uint32_t ulAPSR;
257
258 __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
259
260 ulAPSR &= portAPSR_MODE_BITS_MASK;
261
262 #if defined( GUEST )
263 configASSERT( ulAPSR == portEL1 );
264
265 if( ulAPSR == portEL1 )
266 #else
267 configASSERT( ulAPSR == portEL3 );
268
269 if( ulAPSR == portEL3 )
270 #endif
271 {
272 /* Interrupts are turned off in the CPU itself to ensure a tick does
273 * not execute while the scheduler is being started. Interrupts are
274 * automatically turned back on in the CPU when the first task starts
275 * executing. */
276 portDISABLE_INTERRUPTS();
277
278 /* Start the timer that generates the tick ISR. */
279 configSETUP_TICK_INTERRUPT();
280
281 /* Start the first task executing. */
282 vPortRestoreTaskContext();
283 }
284
285 return 0;
286 }
287 /*-----------------------------------------------------------*/
288
vPortEndScheduler(void)289 void vPortEndScheduler( void )
290 {
291 /* Not implemented in ports where there is nothing to return to.
292 * Artificially force an assert. */
293 configASSERT( ullCriticalNesting == 1000ULL );
294 }
295 /*-----------------------------------------------------------*/
296
vPortEnterCritical(void)297 void vPortEnterCritical( void )
298 {
299 /* Mask interrupts up to the max syscall interrupt priority. */
300 uxPortSetInterruptMask();
301
302 /* Now interrupts are disabled ullCriticalNesting can be accessed
303 * directly. Increment ullCriticalNesting to keep a count of how many times
304 * portENTER_CRITICAL() has been called. */
305 ullCriticalNesting++;
306
307 /* This is not the interrupt safe version of the enter critical function so
308 * assert() if it is being called from an interrupt context. Only API
309 * functions that end in "FromISR" can be used in an interrupt. Only assert if
310 * the critical nesting count is 1 to protect against recursive calls if the
311 * assert function also uses a critical section. */
312 if( ullCriticalNesting == 1ULL )
313 {
314 configASSERT( ullPortInterruptNesting == 0 );
315 }
316 }
317 /*-----------------------------------------------------------*/
318
vPortExitCritical(void)319 void vPortExitCritical( void )
320 {
321 if( ullCriticalNesting > portNO_CRITICAL_NESTING )
322 {
323 /* Decrement the nesting count as the critical section is being
324 * exited. */
325 ullCriticalNesting--;
326
327 /* If the nesting level has reached zero then all interrupt
328 * priorities must be re-enabled. */
329 if( ullCriticalNesting == portNO_CRITICAL_NESTING )
330 {
331 /* Critical nesting has reached zero so all interrupt priorities
332 * should be unmasked. */
333 portCLEAR_INTERRUPT_MASK();
334 }
335 }
336 }
337 /*-----------------------------------------------------------*/
338
FreeRTOS_Tick_Handler(void)339 void FreeRTOS_Tick_Handler( void )
340 {
341 /* Must be the lowest possible priority. */
342 #if !defined( QEMU )
343 {
344 uint64_t ullRunningInterruptPriority;
345 /* s3_0_c12_c11_3 is ICC_RPR_EL1. */
346 __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
347 configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
348 }
349 #endif
350
351 /* Interrupts should not be enabled before this point. */
352 #if ( configASSERT_DEFINED == 1 )
353 {
354 uint32_t ulMaskBits;
355
356 __asm volatile ( "MRS %0, DAIF" : "=r" ( ulMaskBits )::"memory" );
357 configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
358 }
359 #endif /* configASSERT_DEFINED */
360
361 /* Set interrupt mask before altering scheduler structures. The tick
362 * handler runs at the lowest priority, so interrupts cannot already be masked,
363 * so there is no need to save and restore the current mask value. It is
364 * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
365 * updated. */
366 /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
367 __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
368 "DSB SY \n"
369 "ISB SY \n"
370 ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
371
372 /* Ok to enable interrupts after the interrupt source has been cleared. */
373 configCLEAR_TICK_INTERRUPT();
374 portENABLE_INTERRUPTS();
375
376 /* Increment the RTOS tick. */
377 if( xTaskIncrementTick() != pdFALSE )
378 {
379 ullPortYieldRequired = pdTRUE;
380 }
381
382 /* Ensure all interrupt priorities are active again. */
383 portCLEAR_INTERRUPT_MASK();
384 }
385 /*-----------------------------------------------------------*/
386
vPortTaskUsesFPU(void)387 void vPortTaskUsesFPU( void )
388 {
389 /* A task is registering the fact that it needs an FPU context. Set the
390 * FPU flag (which is saved as part of the task context). */
391 ullPortTaskHasFPUContext = pdTRUE;
392
393 /* Consider initialising the FPSR here - but probably not necessary in
394 * AArch64. */
395 }
396 /*-----------------------------------------------------------*/
397
vPortClearInterruptMask(UBaseType_t uxNewMaskValue)398 void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
399 {
400 if( uxNewMaskValue == pdFALSE )
401 {
402 portCLEAR_INTERRUPT_MASK();
403 }
404 }
405 /*-----------------------------------------------------------*/
406
uxPortSetInterruptMask(void)407 UBaseType_t uxPortSetInterruptMask( void )
408 {
409 uint32_t ulReturn;
410 uint64_t ullPMRValue;
411
412 /* Interrupt in the CPU must be turned off while the ICCPMR is being
413 * updated. */
414 portDISABLE_INTERRUPTS();
415 /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
416 __asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) );
417
418 if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
419 {
420 /* Interrupts were already masked. */
421 ulReturn = pdTRUE;
422 }
423 else
424 {
425 ulReturn = pdFALSE;
426 /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
427 __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
428 "DSB SY \n"
429 "ISB SY \n"
430 ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
431 }
432
433 portENABLE_INTERRUPTS();
434
435 return ulReturn;
436 }
437 /*-----------------------------------------------------------*/
438
439 #if ( configASSERT_DEFINED == 1 )
440
vPortValidateInterruptPriority(void)441 void vPortValidateInterruptPriority( void )
442 {
443 /* The following assertion will fail if a service routine (ISR) for
444 * an interrupt that has been assigned a priority above
445 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
446 * function. ISR safe FreeRTOS API functions must *only* be called
447 * from interrupts that have been assigned a priority at or below
448 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
449 *
450 * Numerically low interrupt priority numbers represent logically high
451 * interrupt priorities, therefore the priority of the interrupt must
452 * be set to a value equal to or numerically *higher* than
453 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
454 *
455 * FreeRTOS maintains separate thread and ISR API functions to ensure
456 * interrupt entry is as fast and simple as possible. */
457 uint64_t ullRunningInterruptPriority;
458 /* s3_0_c12_c11_3 is ICC_RPR_EL1. */
459 __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
460
461 configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
462 }
463
464 #endif /* configASSERT_DEFINED */
465 /*-----------------------------------------------------------*/
466
