1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4 MPU port.
31 *----------------------------------------------------------*/
32
33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
34 * all the API functions to use the MPU wrappers. That should only be done when
35 * task.h is included from an application file. */
36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
37
38 /* Scheduler includes. */
39 #include "FreeRTOS.h"
40 #include "task.h"
41 #include "mpu_syscall_numbers.h"
42
43 #ifndef __TARGET_FPU_VFP
44 #error This port can only be used when the project options are configured to enable hardware floating point support.
45 #endif
46
47 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
48
49 #ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
50 #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
51 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
52 #endif
53
54 /* Prototype of all Interrupt Service Routines (ISRs). */
55 typedef void ( * portISR_t )( void );
56
57 /* Constants required to access and manipulate the NVIC. */
58 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
59 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
60 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
61 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
62 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
63 #define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
64 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
65
66 /* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
67 * that a work around is active for errata 837070. */
68 #define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
69 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
70 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
71
72 /* Constants required to access and manipulate the MPU. */
73 #define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
74 #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
75 #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
76 #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
77 #define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
78 #define portMPU_ENABLE ( 0x01UL )
79 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
80 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
81 #define portMPU_REGION_VALID ( 0x10UL )
82 #define portMPU_REGION_ENABLE ( 0x01UL )
83 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
84 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
85
86 /* Constants required to access and manipulate the SysTick. */
87 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
88 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
89 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
90 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
91 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
92 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
93
94 /* Constants required to manipulate the VFP. */
95 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
96 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
97
98 /* Constants required to set up the initial stack. */
99 #define portINITIAL_XPSR ( 0x01000000UL )
100 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
101 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
102 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
103
104 /* Constants used to check the installation of the FreeRTOS interrupt handlers. */
105 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
106 #define portVECTOR_INDEX_SVC ( 11 )
107 #define portVECTOR_INDEX_PENDSV ( 14 )
108
109 /* Constants required to check the validity of an interrupt priority. */
110 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
111 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
112 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
113 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
114 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
115 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
116 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
117 #define portPRIGROUP_SHIFT ( 8UL )
118
119 /* Constants used during system call enter and exit. */
120 #define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
121 #define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
122
123 /* Offsets in the stack to the parameters when inside the SVC handler. */
124 #define portOFFSET_TO_LR ( 5 )
125 #define portOFFSET_TO_PC ( 6 )
126 #define portOFFSET_TO_PSR ( 7 )
127
128 /* For strict compliance with the Cortex-M spec the task start address should
129 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
130 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
131
132 /* Does addr lie within [start, end] address range? */
133 #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
134 ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
135
136 /* Is the access request satisfied by the available permissions? */
137 #define portIS_AUTHORIZED( accessRequest, permissions ) \
138 ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
139
140 /* Max value that fits in a uint32_t type. */
141 #define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
142
143 /* Check if adding a and b will result in overflow. */
144 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
145 /*-----------------------------------------------------------*/
146
147 /* Each task maintains its own interrupt status in the critical nesting
148 * variable. Note this is not saved as part of the task context as context
149 * switches can only occur when uxCriticalNesting is zero. */
150 PRIVILEGED_DATA static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
151
152 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
153
154 /*
155 * This variable is set to pdTRUE when the scheduler is started.
156 */
157 PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
158
159 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
160
161 /*
162 * Setup the timer to generate the tick interrupts.
163 */
164 void vSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
165
166 /*
167 * Configure a number of standard MPU regions that are used by all tasks.
168 */
169 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
170
171 /*
172 * Start first task is a separate function so it can be tested in isolation.
173 */
174 static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
175
176 /*
177 * Return the smallest MPU region size that a given number of bytes will fit
178 * into. The region size is returned as the value that should be programmed
179 * into the region attribute register for that region.
180 */
181 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
182
183 /*
184 * Standard FreeRTOS exception handlers.
185 */
186 void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
187 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
188 void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
189
190 /*
191 * Starts the scheduler by restoring the context of the first task to run.
192 */
193 static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
194
195 /*
196 * C portion of the SVC handler. The SVC handler is split between an asm entry
197 * and a C wrapper for simplicity of coding and maintenance.
198 */
199 void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( used ) ) PRIVILEGED_FUNCTION;
200
201 /*
202 * Function to enable the VFP.
203 */
204 static void vPortEnableVFP( void );
205
206 /*
207 * Utility function.
208 */
209 static uint32_t prvPortGetIPSR( void );
210
211 /*
212 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
213 * FreeRTOS API functions are not called from interrupts that have been assigned
214 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
215 */
216 #if ( configASSERT_DEFINED == 1 )
217 static uint8_t ucMaxSysCallPriority = 0;
218 static uint32_t ulMaxPRIGROUPValue = 0;
219 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
220 #endif /* configASSERT_DEFINED */
221
222 /**
223 * @brief Checks whether or not the processor is privileged.
224 *
225 * @return 1 if the processor is already privileged, 0 otherwise.
226 */
227 BaseType_t xIsPrivileged( void );
228
229 /**
230 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
231 * register.
232 *
233 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
234 * Bit[0] = 0 --> The processor is running privileged
235 * Bit[0] = 1 --> The processor is running unprivileged.
236 */
237 void vResetPrivilege( void );
238
239 /**
240 * @brief Make a task unprivileged.
241 */
242 void vPortSwitchToUserMode( void );
243
244 /**
245 * @brief Enter critical section.
246 */
247 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
248 void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
249 #else
250 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
251 #endif
252
253 /**
254 * @brief Exit from critical section.
255 */
256 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
257 void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
258 #else
259 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
260 #endif
261
262 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
263
264 /**
265 * @brief Triggers lazy stacking of FPU registers.
266 */
267 static void prvTriggerLazyStacking( void ) PRIVILEGED_FUNCTION;
268
269 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
270
271 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
272
273 /**
274 * @brief Sets up the system call stack so that upon returning from
275 * SVC, the system call stack is used.
276 *
277 * @param pulTaskStack The current SP when the SVC was raised.
278 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
279 * @param ucSystemCallNumber The system call number of the system call.
280 */
281 void vSystemCallEnter( uint32_t * pulTaskStack,
282 uint32_t ulLR,
283 uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
284
285 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
286
287 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
288
289 /**
290 * @brief Raise SVC for exiting from a system call.
291 */
292 void vRequestSystemCallExit( void ) PRIVILEGED_FUNCTION;
293
294 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
295
296 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
297
298 /**
299 * @brief Sets up the task stack so that upon returning from
300 * SVC, the task stack is used again.
301 *
302 * @param pulSystemCallStack The current SP when the SVC was raised.
303 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
304 */
305 void vSystemCallExit( uint32_t * pulSystemCallStack,
306 uint32_t ulLR ) PRIVILEGED_FUNCTION;
307
308 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
309
310 /**
311 * @brief Checks whether or not the calling task is privileged.
312 *
313 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
314 */
315 BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
316 /*-----------------------------------------------------------*/
317
318 /*
319 * See header file for description.
320 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters,BaseType_t xRunPrivileged,xMPU_SETTINGS * xMPUSettings)321 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
322 TaskFunction_t pxCode,
323 void * pvParameters,
324 BaseType_t xRunPrivileged,
325 xMPU_SETTINGS * xMPUSettings )
326 {
327 if( xRunPrivileged == pdTRUE )
328 {
329 xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
330 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED;
331 }
332 else
333 {
334 xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
335 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
336 }
337
338 xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
339 xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
340 xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
341 xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
342 xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
343 xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
344 xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
345 xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
346 xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
347
348 xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
349 xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
350 xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
351 xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
352 xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
353 xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
354 xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
355 xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
356 xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
357
358 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
359 {
360 /* Ensure that the system call stack is double word aligned. */
361 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
362 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
363 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
364
365 /* This is not NULL only for the duration of a system call. */
366 xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
367 }
368 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
369
370 return &( xMPUSettings->ulContext[ 19 ] );
371 }
372 /*-----------------------------------------------------------*/
373
vSVCHandler_C(uint32_t * pulParam)374 void vSVCHandler_C( uint32_t * pulParam )
375 {
376 uint8_t ucSVCNumber;
377 uint32_t ulPC;
378
379 #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
380 uint32_t ulReg;
381 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
382
383 #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
384 extern uint32_t __syscalls_flash_start__;
385 extern uint32_t __syscalls_flash_end__;
386 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
387
388 /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
389 * argument (r0) is pulParam[ 0 ]. */
390 ulPC = pulParam[ portOFFSET_TO_PC ];
391 ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
392
393 switch( ucSVCNumber )
394 {
395 case portSVC_START_SCHEDULER:
396 prvRestoreContextOfFirstTask();
397 break;
398
399 case portSVC_YIELD:
400 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
401
402 /* Barriers are normally not required
403 * but do ensure the code is completely
404 * within the specified behaviour for the
405 * architecture. */
406 __asm volatile ( "dsb" );
407 __asm volatile ( "isb" );
408
409 break;
410
411 #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
412 #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
413 case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
414 * svc was raised from any of the
415 * system calls. */
416
417 if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
418 ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
419 {
420 __asm
421 {
422 /* *INDENT-OFF* */
423 mrs ulReg, control /* Obtain current control value. */
424 bic ulReg, # 1 /* Set privilege bit. */
425 msr control, ulReg /* Write back new control value. */
426 /* *INDENT-ON* */
427 }
428 }
429
430 break;
431 #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
432 case portSVC_RAISE_PRIVILEGE:
433 __asm
434 {
435 /* *INDENT-OFF* */
436 mrs ulReg, control /* Obtain current control value. */
437 bic ulReg, # 1 /* Set privilege bit. */
438 msr control, ulReg /* Write back new control value. */
439 /* *INDENT-ON* */
440 }
441 break;
442 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
443 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
444
445 default: /* Unknown SVC call. */
446 break;
447 }
448 }
449 /*-----------------------------------------------------------*/
450
451 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
452
prvTriggerLazyStacking(void)453 __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
454 {
455 /* *INDENT-OFF* */
456 PRESERVE8
457
458 vpush {s0} /* Trigger lazy stacking. */
459 vpop {s0} /* Nullify the affect of the above instruction. */
460
461 /* *INDENT-ON* */
462 }
463
464 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
465 /*-----------------------------------------------------------*/
466
467 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
468
vSystemCallEnter(uint32_t * pulTaskStack,uint32_t ulLR,uint8_t ucSystemCallNumber)469 void vSystemCallEnter( uint32_t * pulTaskStack,
470 uint32_t ulLR,
471 uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
472 {
473 extern TaskHandle_t pxCurrentTCB;
474 extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
475 xMPU_SETTINGS * pxMpuSettings;
476 uint32_t * pulSystemCallStack;
477 uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
478 extern uint32_t __syscalls_flash_start__;
479 extern uint32_t __syscalls_flash_end__;
480
481 ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
482 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
483
484 /* Checks:
485 * 1. SVC is raised from the system call section (i.e. application is
486 * not raising SVC directly).
487 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
488 * it is non-NULL only during the execution of a system call (i.e.
489 * between system call enter and exit).
490 * 3. System call is not for a kernel API disabled by the configuration
491 * in FreeRTOSConfig.h.
492 * 4. We do not need to check that ucSystemCallNumber is within range
493 * because the assembly SVC handler checks that before calling
494 * this function.
495 */
496 if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
497 ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
498 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
499 ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
500 {
501 pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
502
503 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
504 {
505 /* Extended frame i.e. FPU in use. */
506 ulStackFrameSize = 26;
507 prvTriggerLazyStacking();
508 }
509 else
510 {
511 /* Standard frame i.e. FPU not in use. */
512 ulStackFrameSize = 8;
513 }
514
515 /* Make space on the system call stack for the stack frame. */
516 pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
517
518 /* Copy the stack frame. */
519 for( i = 0; i < ulStackFrameSize; i++ )
520 {
521 pulSystemCallStack[ i ] = pulTaskStack[ i ];
522 }
523
524 /* Use the pulSystemCallStack in thread mode. */
525 __asm
526 {
527 msr psp, pulSystemCallStack
528 };
529
530 /* Raise the privilege for the duration of the system call. */
531 __asm
532 {
533 mrs r1, control /* Obtain current control value. */
534 bic r1, # 1 /* Clear nPRIV bit. */
535 msr control, r1 /* Write back new control value. */
536 };
537
538 /* Remember the location where we should copy the stack frame when we exit from
539 * the system call. */
540 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
541
542 /* Store the value of the Link Register before the SVC was raised.
543 * It contains the address of the caller of the System Call entry
544 * point (i.e. the caller of the MPU_<API>). We need to restore it
545 * when we exit from the system call. */
546 pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
547
548 /* Start executing the system call upon returning from this handler. */
549 pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
550 /* Raise a request to exit from the system call upon finishing the
551 * system call. */
552 pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
553
554 /* Record if the hardware used padding to force the stack pointer
555 * to be double word aligned. */
556 if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
557 {
558 pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
559 }
560 else
561 {
562 pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
563 }
564
565 /* We ensure in pxPortInitialiseStack that the system call stack is
566 * double word aligned and therefore, there is no need of padding.
567 * Clear the bit[9] of stacked xPSR. */
568 pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
569 }
570 }
571
572 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
573 /*-----------------------------------------------------------*/
574
575 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
576
vRequestSystemCallExit(void)577 __asm void vRequestSystemCallExit( void ) /* PRIVILEGED_FUNCTION */
578 {
579 PRESERVE8
580
581 svc #portSVC_SYSTEM_CALL_EXIT
582 }
583
584 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
585 /*-----------------------------------------------------------*/
586
587 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
588
vSystemCallExit(uint32_t * pulSystemCallStack,uint32_t ulLR)589 void vSystemCallExit( uint32_t * pulSystemCallStack,
590 uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
591 {
592 extern TaskHandle_t pxCurrentTCB;
593 xMPU_SETTINGS * pxMpuSettings;
594 uint32_t * pulTaskStack;
595 uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
596 extern uint32_t __privileged_functions_start__;
597 extern uint32_t __privileged_functions_end__;
598
599 ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
600 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
601
602 /* Checks:
603 * 1. SVC is raised from the privileged code (i.e. application is not
604 * raising SVC directly). This SVC is only raised from
605 * vRequestSystemCallExit which is in the privileged code section.
606 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
607 * this means that we previously entered a system call and the
608 * application is not attempting to exit without entering a system
609 * call.
610 */
611 if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
612 ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
613 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
614 {
615 pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
616
617 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
618 {
619 /* Extended frame i.e. FPU in use. */
620 ulStackFrameSize = 26;
621 prvTriggerLazyStacking();
622 }
623 else
624 {
625 /* Standard frame i.e. FPU not in use. */
626 ulStackFrameSize = 8;
627 }
628
629 /* Make space on the task stack for the stack frame. */
630 pulTaskStack = pulTaskStack - ulStackFrameSize;
631
632 /* Copy the stack frame. */
633 for( i = 0; i < ulStackFrameSize; i++ )
634 {
635 pulTaskStack[ i ] = pulSystemCallStack[ i ];
636 }
637
638 /* Use the pulTaskStack in thread mode. */
639 __asm
640 {
641 msr psp, pulTaskStack
642 };
643
644 /* Drop the privilege before returning to the thread mode. */
645 __asm
646 {
647 mrs r1, control /* Obtain current control value. */
648 orr r1, # 1 /* Set nPRIV bit. */
649 msr control, r1 /* Write back new control value. */
650 };
651
652 /* Return to the caller of the System Call entry point (i.e. the
653 * caller of the MPU_<API>). */
654 pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
655 /* Ensure that LR has a valid value.*/
656 pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
657
658 /* If the hardware used padding to force the stack pointer
659 * to be double word aligned, set the stacked xPSR bit[9],
660 * otherwise clear it. */
661 if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
662 {
663 pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
664 }
665 else
666 {
667 pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
668 }
669
670 /* This is not NULL only for the duration of the system call. */
671 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
672 }
673 }
674
675 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
676 /*-----------------------------------------------------------*/
677
xPortIsTaskPrivileged(void)678 BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
679 {
680 BaseType_t xTaskIsPrivileged = pdFALSE;
681 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
682
683 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
684 {
685 xTaskIsPrivileged = pdTRUE;
686 }
687
688 return xTaskIsPrivileged;
689 }
690 /*-----------------------------------------------------------*/
691
692 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
693
vPortSVCHandler(void)694 __asm void vPortSVCHandler( void )
695 {
696 extern vSVCHandler_C
697 extern vSystemCallEnter
698 extern vSystemCallExit
699
700 /* *INDENT-OFF* */
701 PRESERVE8
702
703 tst lr, #4
704 ite eq
705 mrseq r0, msp
706 mrsne r0, psp
707
708 ldr r1, [r0, #24]
709 ldrb r2, [r1, #-2]
710 cmp r2, #NUM_SYSTEM_CALLS
711 blt syscall_enter
712 cmp r2, #portSVC_SYSTEM_CALL_EXIT
713 beq syscall_exit
714 b vSVCHandler_C
715
716 syscall_enter
717 mov r1, lr
718 b vSystemCallEnter
719
720 syscall_exit
721 mov r1, lr
722 b vSystemCallExit
723 /* *INDENT-ON* */
724 }
725
726 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
727
vPortSVCHandler(void)728 __asm void vPortSVCHandler( void )
729 {
730 extern vSVCHandler_C
731
732 /* *INDENT-OFF* */
733 PRESERVE8
734
735 /* Assumes psp was in use. */
736 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
737 tst lr, # 4
738 ite eq
739 mrseq r0, msp
740 mrsne r0, psp
741 #else
742 mrs r0, psp
743 #endif
744
745 b vSVCHandler_C
746 /* *INDENT-ON* */
747 }
748
749 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
750 /*-----------------------------------------------------------*/
751
prvRestoreContextOfFirstTask(void)752 __asm void prvRestoreContextOfFirstTask( void )
753 {
754 /* *INDENT-OFF* */
755 PRESERVE8
756
757 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
758 ldr r0, [r0]
759 ldr r0, [r0]
760 msr msp, r0 /* Set the msp back to the start of the stack. */
761
762 /*------------ Program MPU. ------------ */
763 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
764 ldr r2, [r3] /* r2 = pxCurrentTCB. */
765 add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
766
767 dmb /* Complete outstanding transfers before disabling MPU. */
768 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
769 ldr r3, [r0] /* Read the value of MPU_CTRL. */
770 bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
771 str r3, [r0] /* Disable MPU. */
772
773 ldr r0, =0xe000ed9c /* Region Base Address register. */
774 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
775 stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
776
777 #if ( configTOTAL_MPU_REGIONS == 16 )
778 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
779 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
780 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
781 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
782 #endif /* configTOTAL_MPU_REGIONS == 16. */
783
784 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
785 ldr r3, [r0] /* Read the value of MPU_CTRL. */
786 orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
787 str r3, [r0] /* Enable MPU. */
788 dsb /* Force memory writes before continuing. */
789
790 /*---------- Restore Context. ---------- */
791 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
792 ldr r2, [r3] /* r2 = pxCurrentTCB. */
793 ldr r1, [r2] /* r1 = Location of saved context in TCB. */
794
795 ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
796 msr psp, r0
797 stmia r0, {r4-r11} /* Copy the hardware saved context on the task stack. */
798 ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
799 msr control, r3
800 str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
801
802 mov r0, #0
803 msr basepri, r0
804 bx lr
805 /* *INDENT-ON* */
806 }
807 /*-----------------------------------------------------------*/
808
809 /*
810 * See header file for description.
811 */
xPortStartScheduler(void)812 BaseType_t xPortStartScheduler( void )
813 {
814 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
815 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
816 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
817
818 /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
819 * and r0p1 cores. */
820 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
821 configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
822 #else
823
824 /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
825 * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
826 * FreeRTOSConfig.h. */
827 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
828 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
829 #endif
830
831 /* An application can install FreeRTOS interrupt handlers in one of the
832 * following ways:
833 * 1. Direct Routing - Install the functions vPortSVCHandler and
834 * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
835 * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
836 * interrupts and route program control from those handlers to
837 * vPortSVCHandler and xPortPendSVHandler functions.
838 *
839 * Applications that use Indirect Routing must set
840 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
841 * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
842 * is 1, should be preferred when possible. */
843 #if ( configCHECK_HANDLER_INSTALLATION == 1 )
844 {
845 const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
846
847 /* Validate that the application has correctly installed the FreeRTOS
848 * handlers for SVCall and PendSV interrupts. We do not check the
849 * installation of the SysTick handler because the application may
850 * choose to drive the RTOS tick using a timer other than the SysTick
851 * timer by overriding the weak function vPortSetupTimerInterrupt().
852 *
853 * Assertion failures here indicate incorrect installation of the
854 * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
855 * https://www.FreeRTOS.org/FAQHelp.html.
856 *
857 * Systems with a configurable address for the interrupt vector table
858 * can also encounter assertion failures or even system faults here if
859 * VTOR is not set correctly to point to the application's vector table. */
860 configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
861 configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
862 }
863 #endif /* configCHECK_HANDLER_INSTALLATION */
864
865 #if ( configASSERT_DEFINED == 1 )
866 {
867 volatile uint8_t ucOriginalPriority;
868 volatile uint32_t ulImplementedPrioBits = 0;
869 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
870 volatile uint8_t ucMaxPriorityValue;
871
872 /* Determine the maximum priority from which ISR safe FreeRTOS API
873 * functions can be called. ISR safe functions are those that end in
874 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
875 * ensure interrupt entry is as fast and simple as possible.
876 *
877 * Save the interrupt priority value that is about to be clobbered. */
878 ucOriginalPriority = *pucFirstUserPriorityRegister;
879
880 /* Determine the number of priority bits available. First write to all
881 * possible bits. */
882 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
883
884 /* Read the value back to see how many bits stuck. */
885 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
886
887 /* Use the same mask on the maximum system call priority. */
888 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
889
890 /* Check that the maximum system call priority is nonzero after
891 * accounting for the number of priority bits supported by the
892 * hardware. A priority of 0 is invalid because setting the BASEPRI
893 * register to 0 unmasks all interrupts, and interrupts with priority 0
894 * cannot be masked using BASEPRI.
895 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
896 configASSERT( ucMaxSysCallPriority );
897
898 /* Check that the bits not implemented in hardware are zero in
899 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
900 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
901
902 /* Calculate the maximum acceptable priority group value for the number
903 * of bits read back. */
904
905 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
906 {
907 ulImplementedPrioBits++;
908 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
909 }
910
911 if( ulImplementedPrioBits == 8 )
912 {
913 /* When the hardware implements 8 priority bits, there is no way for
914 * the software to configure PRIGROUP to not have sub-priorities. As
915 * a result, the least significant bit is always used for sub-priority
916 * and there are 128 preemption priorities and 2 sub-priorities.
917 *
918 * This may cause some confusion in some cases - for example, if
919 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
920 * priority interrupts will be masked in Critical Sections as those
921 * are at the same preemption priority. This may appear confusing as
922 * 4 is higher (numerically lower) priority than
923 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
924 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
925 * to 4, this confusion does not happen and the behaviour remains the same.
926 *
927 * The following assert ensures that the sub-priority bit in the
928 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
929 * confusion. */
930 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
931 ulMaxPRIGROUPValue = 0;
932 }
933 else
934 {
935 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
936 }
937
938 /* Shift the priority group value back to its position within the AIRCR
939 * register. */
940 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
941 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
942
943 /* Restore the clobbered interrupt priority register to its original
944 * value. */
945 *pucFirstUserPriorityRegister = ucOriginalPriority;
946 }
947 #endif /* configASSERT_DEFINED */
948
949 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
950 * handler highest priority so it can be used to exit a critical section
951 * (where lower priorities are masked). */
952 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
953 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
954 portNVIC_SHPR2_REG = 0;
955
956 /* Configure the regions in the MPU that are common to all tasks. */
957 prvSetupMPU();
958
959 /* Start the timer that generates the tick ISR. Interrupts are disabled
960 * here already. */
961 vSetupTimerInterrupt();
962
963 /* Initialise the critical nesting count ready for the first task. */
964 uxCriticalNesting = 0;
965
966 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
967 {
968 xSchedulerRunning = pdTRUE;
969 }
970 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
971
972 /* Ensure the VFP is enabled - it should be anyway. */
973 vPortEnableVFP();
974
975 /* Lazy save always. */
976 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
977
978 /* Start the first task. */
979 prvStartFirstTask();
980
981 /* Should not get here! */
982 return 0;
983 }
984 /*-----------------------------------------------------------*/
985
prvStartFirstTask(void)986 __asm void prvStartFirstTask( void )
987 {
988 /* *INDENT-OFF* */
989 PRESERVE8
990
991 /* Use the NVIC offset register to locate the stack. */
992 ldr r0, =0xE000ED08
993 ldr r0, [ r0 ]
994 ldr r0, [ r0 ]
995 /* Set the msp back to the start of the stack. */
996 msr msp, r0
997
998 /* Clear the bit that indicates the FPU is in use in case the FPU was used
999 * before the scheduler was started - which would otherwise result in the
1000 * unnecessary leaving of space in the SVC stack for lazy saving of FPU
1001 * registers. */
1002 mov r0, #0
1003 msr control, r0
1004 /* Globally enable interrupts. */
1005 cpsie i
1006 cpsie f
1007 dsb
1008 isb
1009 svc portSVC_START_SCHEDULER /* System call to start first task. */
1010 nop
1011 nop
1012 /* *INDENT-ON* */
1013 }
1014
vPortEndScheduler(void)1015 void vPortEndScheduler( void )
1016 {
1017 /* Not implemented in ports where there is nothing to return to.
1018 * Artificially force an assert. */
1019 configASSERT( uxCriticalNesting == 1000UL );
1020 }
1021 /*-----------------------------------------------------------*/
1022
vPortEnterCritical(void)1023 void vPortEnterCritical( void )
1024 {
1025 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
1026 if( portIS_PRIVILEGED() == pdFALSE )
1027 {
1028 portRAISE_PRIVILEGE();
1029 portMEMORY_BARRIER();
1030
1031 portDISABLE_INTERRUPTS();
1032 uxCriticalNesting++;
1033 portMEMORY_BARRIER();
1034
1035 portRESET_PRIVILEGE();
1036 portMEMORY_BARRIER();
1037 }
1038 else
1039 {
1040 portDISABLE_INTERRUPTS();
1041 uxCriticalNesting++;
1042 }
1043 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1044 portDISABLE_INTERRUPTS();
1045 uxCriticalNesting++;
1046 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1047 }
1048 /*-----------------------------------------------------------*/
1049
vPortExitCritical(void)1050 void vPortExitCritical( void )
1051 {
1052 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
1053 if( portIS_PRIVILEGED() == pdFALSE )
1054 {
1055 portRAISE_PRIVILEGE();
1056 portMEMORY_BARRIER();
1057
1058 configASSERT( uxCriticalNesting );
1059 uxCriticalNesting--;
1060
1061 if( uxCriticalNesting == 0 )
1062 {
1063 portENABLE_INTERRUPTS();
1064 }
1065
1066 portMEMORY_BARRIER();
1067
1068 portRESET_PRIVILEGE();
1069 portMEMORY_BARRIER();
1070 }
1071 else
1072 {
1073 configASSERT( uxCriticalNesting );
1074 uxCriticalNesting--;
1075
1076 if( uxCriticalNesting == 0 )
1077 {
1078 portENABLE_INTERRUPTS();
1079 }
1080 }
1081 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1082 configASSERT( uxCriticalNesting );
1083 uxCriticalNesting--;
1084
1085 if( uxCriticalNesting == 0 )
1086 {
1087 portENABLE_INTERRUPTS();
1088 }
1089 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1090 }
1091 /*-----------------------------------------------------------*/
1092
xPortPendSVHandler(void)1093 __asm void xPortPendSVHandler( void )
1094 {
1095 extern uxCriticalNesting;
1096 extern pxCurrentTCB;
1097 extern vTaskSwitchContext;
1098
1099 /* *INDENT-OFF* */
1100 PRESERVE8
1101
1102 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
1103 ldr r2, [r3] /* r2 = pxCurrentTCB. */
1104 ldr r1, [r2] /* r1 = Location where the context should be saved. */
1105
1106 /*------------ Save Context. ----------- */
1107 mrs r3, control
1108 mrs r0, psp
1109 isb
1110
1111 add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */
1112 tst lr, #0x10
1113 ittt eq
1114 vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
1115 vldmiaeq r0, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
1116 vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
1117 sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */
1118
1119 stmia r1!, {r3-r11, lr} /* Store CONTROL register, r4-r11 and LR. */
1120 ldmia r0, {r4-r11} /* Copy hardware saved context into r4-r11. */
1121 stmia r1!, {r0, r4-r11} /* Store original PSP (after hardware has saved context) and the hardware saved context. */
1122 str r1, [r2] /* Save the location from where the context should be restored as the first member of TCB. */
1123
1124 /*---------- Select next task. --------- */
1125 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
1126 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1127 cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1128 #endif
1129 msr basepri, r0
1130 dsb
1131 isb
1132 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1133 cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1134 #endif
1135 bl vTaskSwitchContext
1136 mov r0, #0
1137 msr basepri, r0
1138
1139 /*------------ Program MPU. ------------ */
1140 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
1141 ldr r2, [r3] /* r2 = pxCurrentTCB. */
1142 add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
1143
1144 dmb /* Complete outstanding transfers before disabling MPU. */
1145 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
1146 ldr r3, [r0] /* Read the value of MPU_CTRL. */
1147 bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
1148 str r3, [r0] /* Disable MPU. */
1149
1150 ldr r0, =0xe000ed9c /* Region Base Address register. */
1151 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
1152 stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
1153
1154 #if ( configTOTAL_MPU_REGIONS == 16 )
1155 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
1156 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
1157 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
1158 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
1159 #endif /* configTOTAL_MPU_REGIONS == 16. */
1160
1161 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
1162 ldr r3, [r0] /* Read the value of MPU_CTRL. */
1163 orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
1164 str r3, [r0] /* Enable MPU. */
1165 dsb /* Force memory writes before continuing. */
1166
1167 /*---------- Restore Context. ---------- */
1168 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
1169 ldr r2, [r3] /* r2 = pxCurrentTCB. */
1170 ldr r1, [r2] /* r1 = Location of saved context in TCB. */
1171
1172 ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
1173 msr psp, r0
1174 stmia r0!, {r4-r11} /* Copy the hardware saved context on the task stack. */
1175 ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
1176 msr control, r3
1177
1178 tst lr, #0x10
1179 ittt eq
1180 vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
1181 vstmiaeq r0!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
1182 vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
1183
1184 str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
1185 bx lr
1186 /* *INDENT-ON* */
1187 }
1188 /*-----------------------------------------------------------*/
1189
xPortSysTickHandler(void)1190 void xPortSysTickHandler( void )
1191 {
1192 uint32_t ulDummy;
1193
1194 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
1195 traceISR_ENTER();
1196 {
1197 /* Increment the RTOS tick. */
1198 if( xTaskIncrementTick() != pdFALSE )
1199 {
1200 traceISR_EXIT_TO_SCHEDULER();
1201 /* Pend a context switch. */
1202 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
1203 }
1204 else
1205 {
1206 traceISR_EXIT();
1207 }
1208 }
1209 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
1210 }
1211 /*-----------------------------------------------------------*/
1212
1213 /*
1214 * Setup the systick timer to generate the tick interrupts at the required
1215 * frequency.
1216 */
vSetupTimerInterrupt(void)1217 __weak void vSetupTimerInterrupt( void )
1218 {
1219 /* Reset the SysTick. */
1220 portNVIC_SYSTICK_CTRL_REG = 0UL;
1221 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
1222
1223 /* Configure SysTick to interrupt at the requested rate. */
1224 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
1225 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
1226 }
1227 /*-----------------------------------------------------------*/
1228
vPortEnableVFP(void)1229 __asm void vPortEnableVFP( void )
1230 {
1231 /* *INDENT-OFF* */
1232 PRESERVE8
1233
1234 ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
1235 ldr r1, [ r0 ]
1236
1237 orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
1238 str r1, [ r0 ]
1239 bx r14
1240 nop
1241 /* *INDENT-ON* */
1242 }
1243 /*-----------------------------------------------------------*/
1244
prvSetupMPU(void)1245 static void prvSetupMPU( void )
1246 {
1247 extern uint32_t __privileged_functions_start__;
1248 extern uint32_t __privileged_functions_end__;
1249 extern uint32_t __FLASH_segment_start__;
1250 extern uint32_t __FLASH_segment_end__;
1251 extern uint32_t __privileged_data_start__;
1252 extern uint32_t __privileged_data_end__;
1253
1254 /* The only permitted number of regions are 8 or 16. */
1255 configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
1256
1257 /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
1258 configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
1259
1260 /* Check the expected MPU is present. */
1261 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
1262 {
1263 /* First setup the unprivileged flash for unprivileged read only access. */
1264 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
1265 ( portMPU_REGION_VALID ) |
1266 ( portUNPRIVILEGED_FLASH_REGION );
1267
1268 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
1269 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1270 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
1271 ( portMPU_REGION_ENABLE );
1272
1273 /* Setup the privileged flash for privileged only access. This is where
1274 * the kernel code is placed. */
1275 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
1276 ( portMPU_REGION_VALID ) |
1277 ( portPRIVILEGED_FLASH_REGION );
1278
1279 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
1280 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1281 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
1282 ( portMPU_REGION_ENABLE );
1283
1284 /* Setup the privileged data RAM region. This is where the kernel data
1285 * is placed. */
1286 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
1287 ( portMPU_REGION_VALID ) |
1288 ( portPRIVILEGED_RAM_REGION );
1289
1290 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
1291 ( portMPU_REGION_EXECUTE_NEVER ) |
1292 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1293 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
1294 ( portMPU_REGION_ENABLE );
1295
1296 /* By default allow everything to access the general peripherals. The
1297 * system peripherals and registers are protected. */
1298 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
1299 ( portMPU_REGION_VALID ) |
1300 ( portGENERAL_PERIPHERALS_REGION );
1301
1302 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
1303 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
1304 ( portMPU_REGION_ENABLE );
1305
1306 /* Enable the memory fault exception. */
1307 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
1308
1309 /* Enable the MPU with the background region configured. */
1310 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
1311 }
1312 }
1313 /*-----------------------------------------------------------*/
1314
prvGetMPURegionSizeSetting(uint32_t ulActualSizeInBytes)1315 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
1316 {
1317 uint32_t ulRegionSize, ulReturnValue = 4;
1318
1319 /* 32 is the smallest region size, 31 is the largest valid value for
1320 * ulReturnValue. */
1321 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
1322 {
1323 if( ulActualSizeInBytes <= ulRegionSize )
1324 {
1325 break;
1326 }
1327 else
1328 {
1329 ulReturnValue++;
1330 }
1331 }
1332
1333 /* Shift the code by one before returning so it can be written directly
1334 * into the the correct bit position of the attribute register. */
1335 return( ulReturnValue << 1UL );
1336 }
1337 /*-----------------------------------------------------------*/
1338
xIsPrivileged(void)1339 __asm BaseType_t xIsPrivileged( void )
1340 {
1341 /* *INDENT-OFF* */
1342 PRESERVE8
1343
1344 mrs r0, control /* r0 = CONTROL. */
1345 tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
1346 ite ne
1347 movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
1348 moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
1349 bx lr /* Return. */
1350 /* *INDENT-ON* */
1351 }
1352 /*-----------------------------------------------------------*/
1353
vResetPrivilege(void)1354 __asm void vResetPrivilege( void )
1355 {
1356 /* *INDENT-OFF* */
1357 PRESERVE8
1358
1359 mrs r0, control /* r0 = CONTROL. */
1360 orrs r0, #1 /* r0 = r0 | 1. */
1361 msr control, r0 /* CONTROL = r0. */
1362 bx lr /* Return. */
1363 /* *INDENT-ON* */
1364 }
1365 /*-----------------------------------------------------------*/
1366
vPortSwitchToUserMode(void)1367 void vPortSwitchToUserMode( void )
1368 {
1369 /* Load the current task's MPU settings from its TCB. */
1370 xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
1371
1372 /* Mark the task as unprivileged. */
1373 xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
1374
1375 /* Lower the processor's privilege level. */
1376 vResetPrivilege();
1377 }
1378 /*-----------------------------------------------------------*/
1379
vPortStoreTaskMPUSettings(xMPU_SETTINGS * xMPUSettings,const struct xMEMORY_REGION * const xRegions,StackType_t * pxBottomOfStack,configSTACK_DEPTH_TYPE uxStackDepth)1380 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
1381 const struct xMEMORY_REGION * const xRegions,
1382 StackType_t * pxBottomOfStack,
1383 configSTACK_DEPTH_TYPE uxStackDepth )
1384 {
1385 extern uint32_t __SRAM_segment_start__;
1386 extern uint32_t __SRAM_segment_end__;
1387 extern uint32_t __privileged_data_start__;
1388 extern uint32_t __privileged_data_end__;
1389
1390
1391 int32_t lIndex;
1392 uint32_t ul;
1393
1394 if( xRegions == NULL )
1395 {
1396 /* No MPU regions are specified so allow access to all RAM. */
1397 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1398 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
1399 ( portMPU_REGION_VALID ) |
1400 ( portSTACK_REGION ); /* Region number. */
1401
1402 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1403 ( portMPU_REGION_READ_WRITE ) |
1404 ( portMPU_REGION_EXECUTE_NEVER ) |
1405 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1406 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
1407 ( portMPU_REGION_ENABLE );
1408
1409 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
1410 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
1411 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1412 tskMPU_WRITE_PERMISSION );
1413
1414 /* Invalidate user configurable regions. */
1415 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1416 {
1417 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1418 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1419 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1420 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1421 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1422 }
1423 }
1424 else
1425 {
1426 /* This function is called automatically when the task is created - in
1427 * which case the stack region parameters will be valid. At all other
1428 * times the stack parameters will not be valid and it is assumed that the
1429 * stack region has already been configured. */
1430 if( uxStackDepth > 0 )
1431 {
1432 /* Define the region that allows access to the stack. */
1433 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1434 ( ( uint32_t ) pxBottomOfStack ) |
1435 ( portMPU_REGION_VALID ) |
1436 ( portSTACK_REGION ); /* Region number. */
1437
1438 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1439 ( portMPU_REGION_READ_WRITE ) |
1440 ( portMPU_REGION_EXECUTE_NEVER ) |
1441 ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
1442 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1443 ( portMPU_REGION_ENABLE );
1444
1445 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
1446 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
1447 ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
1448 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1449 tskMPU_WRITE_PERMISSION );
1450 }
1451
1452 lIndex = 0;
1453
1454 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1455 {
1456 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
1457 {
1458 /* Translate the generic region definition contained in
1459 * xRegions into the CM4 specific MPU settings that are then
1460 * stored in xMPUSettings. */
1461 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
1462 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
1463 ( portMPU_REGION_VALID ) |
1464 ( ul - 1UL ); /* Region number. */
1465
1466 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
1467 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
1468 ( xRegions[ lIndex ].ulParameters ) |
1469 ( portMPU_REGION_ENABLE );
1470
1471 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
1472 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
1473 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1474
1475 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
1476 ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
1477 {
1478 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
1479 }
1480
1481 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
1482 {
1483 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
1484 }
1485 }
1486 else
1487 {
1488 /* Invalidate the region. */
1489 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1490 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1491 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1492 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1493 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1494 }
1495
1496 lIndex++;
1497 }
1498 }
1499 }
1500 /*-----------------------------------------------------------*/
1501
1502 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1503
xPortIsAuthorizedToAccessBuffer(const void * pvBuffer,uint32_t ulBufferLength,uint32_t ulAccessRequested)1504 BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
1505 uint32_t ulBufferLength,
1506 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
1507
1508 {
1509 uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
1510 BaseType_t xAccessGranted = pdFALSE;
1511 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1512
1513
1514 if( xSchedulerRunning == pdFALSE )
1515 {
1516 /* Grant access to all the kernel objects before the scheduler
1517 * is started. It is necessary because there is no task running
1518 * yet and therefore, we cannot use the permissions of any
1519 * task. */
1520 xAccessGranted = pdTRUE;
1521 }
1522 else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1523 {
1524 xAccessGranted = pdTRUE;
1525 }
1526 else
1527 {
1528 if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
1529 {
1530 ulBufferStartAddress = ( uint32_t ) pvBuffer;
1531 ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
1532
1533 for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
1534 {
1535 if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
1536 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1537 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1538 portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
1539 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1540 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1541 portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
1542 {
1543 xAccessGranted = pdTRUE;
1544 break;
1545 }
1546 }
1547 }
1548 }
1549
1550 return xAccessGranted;
1551 }
1552
1553 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
1554 /*-----------------------------------------------------------*/
1555
prvPortGetIPSR(void)1556 __asm uint32_t prvPortGetIPSR( void )
1557 {
1558 /* *INDENT-OFF* */
1559 PRESERVE8
1560
1561 mrs r0, ipsr
1562 bx r14
1563 /* *INDENT-ON* */
1564 }
1565 /*-----------------------------------------------------------*/
1566
1567 #if ( configASSERT_DEFINED == 1 )
1568
vPortValidateInterruptPriority(void)1569 void vPortValidateInterruptPriority( void )
1570 {
1571 uint32_t ulCurrentInterrupt;
1572 uint8_t ucCurrentPriority;
1573
1574 /* Obtain the number of the currently executing interrupt. */
1575 ulCurrentInterrupt = prvPortGetIPSR();
1576
1577 /* Is the interrupt number a user defined interrupt? */
1578 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
1579 {
1580 /* Look up the interrupt's priority. */
1581 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
1582
1583 /* The following assertion will fail if a service routine (ISR) for
1584 * an interrupt that has been assigned a priority above
1585 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
1586 * function. ISR safe FreeRTOS API functions must *only* be called
1587 * from interrupts that have been assigned a priority at or below
1588 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1589 *
1590 * Numerically low interrupt priority numbers represent logically high
1591 * interrupt priorities, therefore the priority of the interrupt must
1592 * be set to a value equal to or numerically *higher* than
1593 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1594 *
1595 * Interrupts that use the FreeRTOS API must not be left at their
1596 * default priority of zero as that is the highest possible priority,
1597 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
1598 * and therefore also guaranteed to be invalid.
1599 *
1600 * FreeRTOS maintains separate thread and ISR API functions to ensure
1601 * interrupt entry is as fast and simple as possible.
1602 *
1603 * The following links provide detailed information:
1604 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
1605 * https://www.FreeRTOS.org/FAQHelp.html */
1606 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
1607 }
1608
1609 /* Priority grouping: The interrupt controller (NVIC) allows the bits
1610 * that define each interrupt's priority to be split between bits that
1611 * define the interrupt's pre-emption priority bits and bits that define
1612 * the interrupt's sub-priority. For simplicity all bits must be defined
1613 * to be pre-emption priority bits. The following assertion will fail if
1614 * this is not the case (if some bits represent a sub-priority).
1615 *
1616 * If the application only uses CMSIS libraries for interrupt
1617 * configuration then the correct setting can be achieved on all Cortex-M
1618 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
1619 * scheduler. Note however that some vendor specific peripheral libraries
1620 * assume a non-zero priority group setting, in which cases using a value
1621 * of zero will result in unpredictable behaviour. */
1622 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
1623 }
1624
1625 #endif /* configASSERT_DEFINED */
1626 /*-----------------------------------------------------------*/
1627
1628 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1629
vPortGrantAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1630 void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1631 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1632 {
1633 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1634 xMPU_SETTINGS * xTaskMpuSettings;
1635
1636 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1637 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1638
1639 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1640
1641 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
1642 }
1643
1644 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1645 /*-----------------------------------------------------------*/
1646
1647 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1648
vPortRevokeAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1649 void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1650 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1651 {
1652 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1653 xMPU_SETTINGS * xTaskMpuSettings;
1654
1655 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1656 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1657
1658 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1659
1660 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
1661 }
1662
1663 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1664 /*-----------------------------------------------------------*/
1665
1666 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1667
1668 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
1669
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1670 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1671 {
1672 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1673 BaseType_t xAccessGranted = pdFALSE;
1674 const xMPU_SETTINGS * xTaskMpuSettings;
1675
1676 if( xSchedulerRunning == pdFALSE )
1677 {
1678 /* Grant access to all the kernel objects before the scheduler
1679 * is started. It is necessary because there is no task running
1680 * yet and therefore, we cannot use the permissions of any
1681 * task. */
1682 xAccessGranted = pdTRUE;
1683 }
1684 else
1685 {
1686 xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1687
1688 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1689 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1690
1691 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1692 {
1693 xAccessGranted = pdTRUE;
1694 }
1695 else
1696 {
1697 if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
1698 {
1699 xAccessGranted = pdTRUE;
1700 }
1701 }
1702 }
1703
1704 return xAccessGranted;
1705 }
1706
1707 #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1708
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1709 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1710 {
1711 ( void ) lInternalIndexOfKernelObject;
1712
1713 /* If Access Control List feature is not used, all the tasks have
1714 * access to all the kernel objects. */
1715 return pdTRUE;
1716 }
1717
1718 #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1719
1720 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
1721 /*-----------------------------------------------------------*/
1722
