Searched refs:driven (Results 1 – 25 of 191) sorted by relevance
12345678
| /Zephyr-latest/doc/hardware/peripherals/ |
| D | uart.rst | 22 With the Interrupt-driven API, possibly slow communication can happen in the
33 Interrupt-driven API and the Asynchronous API should NOT be used at
45 the interrupt-driven API or the asynchronous API can be used. Only enable the
75 Interrupt-driven API
|
| /Zephyr-latest/drivers/i2c/ |
| D | Kconfig.sam0 | 17 This enables DMA driven transactions for the I2C peripheral.
18 DMA driven mode requires fewer interrupts to handle the
|
| D | Kconfig.gpio | 10 Enable software driven (bit banging) I2C support using GPIO pins
|
| /Zephyr-latest/drivers/display/ |
| D | Kconfig.nrf_led_matrix | 5 bool "LED matrix driven by GPIOs"
11 Enable driver for a LED matrix with rows and columns driven by
|
| /Zephyr-latest/drivers/mdio/ |
| D | Kconfig.gpio | 9 Enable software driven (bit banging) MDIO support using GPIO pins
|
| /Zephyr-latest/subsys/console/ |
| D | Kconfig | 36 interrupt-driven operation and use busy-polling.
45 interrupt-driven operation and use busy-polling.
|
| /Zephyr-latest/drivers/spi/ |
| D | Kconfig.smartbond | 17 Enables using the DMA engine instead of interrupt-driven
|
| D | Kconfig.gd32 | 19 Enable the interrupt driven mode for SPI instances
|
| /Zephyr-latest/samples/drivers/auxdisplay/boards/ |
| D | esp_wrover_kit.overlay | 2 * Character HD44780 module driven by the PCF8574 gpio.
|
| /Zephyr-latest/boards/makerbase/mks_canable_v20/doc/ |
| D | index.rst | 58 The MKS CANable V2.0 system clock is driven by internal high speed oscillator.
59 By default system clock is driven by PLL clock at 160 MHz,
60 the PLL is driven by the 16 MHz high speed internal oscillator.
62 The FDCAN1 peripheral is driven by PLLQ, which has 80 MHz frequency.
|
| /Zephyr-latest/boards/st/steval_fcu001v1/doc/ |
| D | index.rst | 56 The steval_fcu001v1 system clock can be driven by an internal or external oscillator,
57 as well as by the main PLL clock. By default, the system clock is driven by the PLL clock at 84MHz,
58 driven by a 16MHz high-speed external clock.
|
| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.altera_jtag | 18 Enabling this will disable poll_in and interrupt driven api.
|
| /Zephyr-latest/drivers/sdhc/ |
| D | Kconfig.rcar | 38 bool "Internal DMA IRQ driven support for Renesas Rcar MMC driver"
|
| /Zephyr-latest/boards/st/stm32l4r9i_disco/doc/ |
| D | index.rst | 38 The STM32L4R9AI System Clock can be driven by an internal or external oscillator,
39 as well as by the main PLL clock. By default, the System clock is driven by
40 the PLL clock at 120MHz. PLL clock is driven by a 4MHz medium speed internal clock.
|
| /Zephyr-latest/boards/fanke/fk750m1_vbt6/doc/ |
| D | index.rst | 71 The FK750M1-VBT6 System Clock could be driven by an internal or external oscillator,
72 as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 480MHz,
73 driven by an 25MHz external crystal oscillator.
|
| /Zephyr-latest/boards/st/nucleo_f412zg/doc/ |
| D | index.rst | 106 Nucleo F412ZG System Clock could be driven by internal or external oscillator,
107 as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz,
108 driven by 8MHz high speed external clock.
|
| /Zephyr-latest/boards/weact/usb2canfdv1/doc/ |
| D | index.rst | 23 The STM32G0B1CBT6 PLL is driven by an external crystal oscillator (HSE) running at 16 MHz and
|
| /Zephyr-latest/boards/st/nucleo_f207zg/doc/ |
| D | index.rst | 112 Nucleo F207ZG System Clock could be driven by internal or external oscillator,
113 as well as main PLL clock. By default System clock is driven by PLL clock at 120MHz,
114 driven by 8MHz high speed external clock.
|
| /Zephyr-latest/boards/st/nucleo_f401re/doc/ |
| D | index.rst | 92 Nucleo F401RE System Clock could be driven by internal or external oscillator,
93 as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz,
94 driven by 8MHz high speed external clock.
|
| /Zephyr-latest/boards/st/nucleo_f410rb/doc/ |
| D | index.rst | 102 Nucleo F410RB System Clock could be driven by an internal or external oscillator,
103 as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz,
104 driven by an 8MHz high-speed external clock.
|
| /Zephyr-latest/boards/others/black_f407zg_pro/doc/ |
| D | index.rst | 121 BLACK_F407ZG_PRO System Clock could be driven by internal or external oscillator,
122 as well as main PLL clock. By default System clock is driven by PLL clock
123 at 168MHz, driven by 8MHz high speed external clock.
|
| /Zephyr-latest/boards/st/stm32f072_eval/doc/ |
| D | index.rst | 99 STM32F072-EVAL System Clock could be driven by an internal or external oscillator,
100 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 48MHz,
101 driven by an 8MHz high speed internal clock.
|
| /Zephyr-latest/boards/st/nucleo_f413zh/doc/ |
| D | index.rst | 106 Nucleo F413ZH System Clock could be driven by internal or external oscillator,
107 as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz,
108 driven by 8MHz high speed external clock.
|
| /Zephyr-latest/boards/st/nucleo_g431kb/doc/ |
| D | index.rst | 58 The Nucleo G431KB System Clock could be driven by internal or external oscillator,
60 High Speed oscillator is supported. By default System clock is driven by PLL clock at 170 MHz,
61 the PLL is driven by the 16 MHz high speed internal oscillator.
|
| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.cavs | 26 The DSP wall clock timer is a timer driven directly by
|
12345678
