1.. zephyr:board:: nucleo_f207zg 2 3Overview 4******** 5 6The Nucleo F207ZG board features an ARM Cortex-M3 based STM32F207ZG MCU 7with a wide range of connectivity support and configurations. Here are 8some highlights of the Nucleo F207ZG board: 9 10- STM32 microcontroller in LQFP144 package 11- Ethernet compliant with IEEE-802.3-2002 12- Two types of extension resources: 13 14 - ST Zio connector including: support for Arduino* Uno V3 connectivity 15 (A0 to A5, D0 to D15) and additional signals exposing a wide range of 16 peripherals 17 - ST morpho extension pin headers for full access to all STM32 I/Os 18 19- On-board ST-LINK/V2-1 debugger/programmer with SWD connector 20- Flexible board power supply: 21 22 - 5 V from ST-LINK/V2-1 USB VBUS 23 - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho 24 connectors, 5 V on ST morpho connector 25 26- Three user LEDs 27- Two push-buttons: USER and RESET 28 29More information about the board can be found at the `Nucleo F207ZG website`_. 30 31Hardware 32******** 33 34Nucleo F207ZG provides the following hardware components: 35 36- STM32F207ZGT6 in LQFP144 package 37- ARM |reg| 32-bit Cortex |reg| -M3 CPU 38- 120 MHz max CPU frequency 39- VDD from 1.7 V to 3.6 V 40- 1 MB Flash 41- 128 KB SRAM 42- GPIO with external interrupt capability 43- 12-bit ADC with 24 channels 44- RTC 45- 17 General purpose timers 46- 2 watchdog timers (independent and window) 47- SysTick timer 48- USART/UART (6) 49- I2C (3) 50- SPI (3) 51- SDIO 52- USB 2.0 OTG FS 53- DMA Controller 54- 10/100 Ethernet MAC with dedicated DMA 55- CRC calculation unit 56- True random number generator 57 58More information about STM32F207ZG can be found here: 59 60- `STM32F207ZG on www.st.com`_ 61- `STM32F207 reference manual`_ 62 63Supported Features 64================== 65 66The Zephyr nucleo_207zg board configuration supports the following hardware features: 67 68+-------------+------------+-------------------------------------+ 69| Interface | Controller | Driver/Component | 70+=============+============+=====================================+ 71| NVIC | on-chip | nested vector interrupt controller | 72+-------------+------------+-------------------------------------+ 73| UART | on-chip | serial port-polling; | 74| | | serial port-interrupt | 75+-------------+------------+-------------------------------------+ 76| PINMUX | on-chip | pinmux | 77+-------------+------------+-------------------------------------+ 78| GPIO | on-chip | gpio | 79+-------------+------------+-------------------------------------+ 80| ETHERNET | on-chip | Ethernet | 81+-------------+------------+-------------------------------------+ 82| I2C | on-chip | i2c | 83+-------------+------------+-------------------------------------+ 84| USB | on-chip | USB device | 85+-------------+------------+-------------------------------------+ 86| SPI | on-chip | spi | 87+-------------+------------+-------------------------------------+ 88| WATCHDOG | on-chip | independent watchdog | 89+-------------+------------+-------------------------------------+ 90| ADC | on-chip | ADC Controller | 91+-------------+------------+-------------------------------------+ 92| DAC | on-chip | DAC Controller | 93+-------------+------------+-------------------------------------+ 94| Backup SRAM | on-chip | Backup SRAM | 95+-------------+------------+-------------------------------------+ 96| PWM | on-chip | PWM | 97+-------------+------------+-------------------------------------+ 98| RNG | on-chip | Random Number Generator | 99+-------------+------------+-------------------------------------+ 100| DMA | on-chip | Direct Memory Access | 101+-------------+------------+-------------------------------------+ 102| die-temp | on-chip | die temperature sensor | 103+-------------+------------+-------------------------------------+ 104| RTC | on-chip | rtc | 105+-------------+------------+-------------------------------------+ 106 107Other hardware features are not yet supported on this Zephyr port. 108 109The default configuration can be found in the defconfig file: 110:zephyr_file:`boards/st/nucleo_f207zg/nucleo_f207zg_defconfig` 111 112 113Connections and IOs 114=================== 115 116Nucleo F207ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, 117input/output, pull-up, etc. 118 119Available pins: 120--------------- 121.. image:: img/nucleo_f207zg_zio_left.jpg 122 :align: center 123 :alt: Nucleo F207ZG ZIO connectors (left) 124.. image:: img/nucleo_f207zg_zio_right.jpg 125 :align: center 126 :alt: Nucleo F207ZG ZIO connectors (right) 127.. image:: img/nucleo_f207zg_morpho_left.jpg 128 :align: center 129 :alt: Nucleo F207ZG Morpho connectors (left) 130.. image:: img/nucleo_f207zg_morpho_right.jpg 131 :align: center 132 :alt: Nucleo F207ZG Morpho connectors (right) 133 134For more details please refer to `STM32 Nucleo-144 board User Manual`_. 135 136Default Zephyr Peripheral Mapping: 137---------------------------------- 138 139- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) 140- UART_6 TX/RX : PG14/PG9 (Arduino Serial) 141- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) 142- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) 143- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 144- USB_DM : PA11 145- USB_DP : PA12 146- USER_PB : PC13 147- LD1 : PB0 148- LD2 : PB7 149- LD3 : PB14 150- DAC: PA4 151- ADC: PA0 152- PWM_1_CH1 : PE9 153 154System Clock 155------------ 156 157Nucleo F207ZG System Clock could be driven by internal or external oscillator, 158as well as main PLL clock. By default System clock is driven by PLL clock at 120MHz, 159driven by 8MHz high speed external clock. 160 161Serial Port 162----------- 163 164Nucleo F207ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. 165Default settings are 115200 8N1. 166 167Network interface 168----------------- 169 170Ethernet configured as the default network interface 171 172USB 173--- 174Nucleo F207ZG board has a USB OTG dual-role device (DRD) controller that 175supports both device and host functions through its micro USB connector 176(USB USER). Only USB device function is supported in Zephyr at the moment. 177 178Backup SRAM 179----------- 180 181In order to test backup SRAM you may want to disconnect VBAT from VDD. You can 182do it by removing ``SB156`` jumper on the back side of the board. 183 184Programming and Debugging 185************************* 186 187Nucleo F207ZG board includes an ST-LINK/V2-1 embedded debug tool interface. 188 189Flashing 190======== 191 192The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, 193so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required. 194 195Alternatively, OpenOCD or JLink can also be used to flash the board using 196the ``--runner`` (or ``-r``) option: 197 198.. code-block:: console 199 200 $ west flash --runner openocd 201 $ west flash --runner jlink 202 203 204.. _Nucleo F207ZG website: 205 https://www.st.com/en/evaluation-tools/nucleo-f207zg.html 206 207.. _STM32 Nucleo-144 board User Manual: 208 https://www.st.com/resource/en/user_manual/dm00244518.pdf 209 210.. _STM32F207ZG on www.st.com: 211 https://www.st.com/en/microcontrollers/stm32f207zg.html 212 213.. _STM32F207 reference manual: 214 https://www.st.com/resource/en/reference_manual/cd00225773.pdf 215 216.. _STM32CubeProgrammer: 217 https://www.st.com/en/development-tools/stm32cubeprog.html 218