| /trusted-firmware-a-3.7.0/plat/intel/soc/n5x/soc/ |
| D | n5x_clock_manager.c | 26 uint64_t clock = 0; in clk_get_pll_output_hz() local
34 clock = mmio_read_32(scr_reg); in clk_get_pll_output_hz()
38 clock = CLKMGR_INTOSC_HZ; in clk_get_pll_output_hz()
43 clock = mmio_read_32(scr_reg); in clk_get_pll_output_hz()
59 return ((clock * 2 * (divf + 1)) / ((divr + 1) * power)); in clk_get_pll_output_hz()
64 uint32_t clock = 0; in get_l4_clk() local
80 clock = clk_get_pll_output_hz(); in get_l4_clk()
81 clock /= 1 + mainpll_c1cnt; in get_l4_clk()
85 clock = clk_get_pll_output_hz(); in get_l4_clk()
86 clock /= 1 + perpll_c1cnt; in get_l4_clk()
[all …]
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| /trusted-firmware-a-3.7.0/fdts/ |
| D | rtsm_ve-motherboard.dtsi | 14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24000000>;
17 clock-output-names = "v2m:clk24mhz";
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <1000000>;
24 clock-output-names = "v2m:refclk1mhz";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
[all …]
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| D | fvp-foundation-motherboard.dtsi | 21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "v2m:clk24mhz";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <1000000>;
31 clock-output-names = "v2m:refclk1mhz";
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
[all …]
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| D | corstone700.dtsi | 51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <100000000>;
54 clock-output-names = "apb_pclk";
58 /* Reference 24MHz clock x 2 */
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <48000000>;
62 clock-output-names = "smclk";
66 /* UART clock - 32MHz */
[all …]
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| D | morello.dtsi | 62 clock-names = "apb_pclk";
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <50000000>;
88 clock-output-names = "apb_pclk";
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <85000000>;
95 clock-output-names = "iofpga:aclk";
99 compatible = "fixed-clock";
[all …]
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| D | a5ds.dts | 68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <7500000>;
71 clock-output-names = "apb_pclk";
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <24000000>;
78 clock-output-names = "apb_pclk";
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
[all …]
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| D | fvp-ve-Cortex-A5x1.dts | 56 clock-names = "pxlclk";
81 /* CPU and internal AXI reference clock */
85 #clock-cells = <0>;
86 clock-output-names = "oscclk0";
90 /* Multiplexed AXI master clock */
94 #clock-cells = <0>;
95 clock-output-names = "oscclk1";
103 #clock-cells = <0>;
104 clock-output-names = "oscclk2";
112 #clock-cells = <0>;
[all …]
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| D | n1sdp-single-chip.dts | 34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <60000000>;
37 clock-output-names = "iofpga_clk";
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <23750000>;
44 clock-output-names = "hdlcdclk";
52 clock-names = "pxlclk";
66 clock-frequency = <400000>;
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| D | tc.dts | 245 clock-names = "apb_pclk";
257 clock-names = "apb_pclk";
280 #clock-cells = <1>;
285 #clock-cells = <1>;
310 compatible = "fixed-clock";
311 #clock-cells = <0>;
312 clock-frequency = <100000000>;
313 clock-output-names = "apb_pclk";
317 compatible = "fixed-clock";
318 #clock-cells = <0>;
[all …]
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| D | stm32mp251.dtsi | 7 #include <dt-bindings/clock/stm32mp25-clks.h>
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <48000000>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <64000000>;
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <32768>;
[all …]
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| D | morello-coresight.dtsi | 20 clock-names = "apb_pclk";
28 clock-names = "apb_pclk";
43 clock-names = "apb_pclk";
51 clock-names = "apb_pclk";
66 clock-names = "apb_pclk";
74 clock-names = "apb_pclk";
89 clock-names = "apb_pclk";
97 clock-names = "apb_pclk";
165 clock-names = "apb_pclk";
179 clock-names = "apb_pclk";
[all …]
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| D | arm_fpga.dts | 68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <100000000>;
71 clock-output-names = "apb_pclk";
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <10000000>;
78 clock-output-names = "uartclk";
86 clock-names = "uartclk", "apb_pclk";
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| D | stm32mp131.dtsi | 6 #include <dt-bindings/clock/stm32mp13-clks.h>
23 clock-names = "cpu";
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-frequency = <4000000>;
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <24000000>;
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
[all …]
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| D | morello-soc.dts | 231 clock-names = "aclk";
238 clock-names = "pxclk";
258 clock-frequency = <100000>;
278 /* 77.1 MHz derived from 24 MHz reference clock */
279 compatible = "fixed-clock";
280 #clock-cells = <0>;
281 clock-frequency = <350000000>;
282 clock-output-names = "aclk";
297 clock-names = "clk_mali";
302 compatible = "fixed-clock";
[all …]
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| D | stm32mp151.dtsi | 7 #include <dt-bindings/clock/stm32mp1-clks.h>
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <24000000>;
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <64000000>;
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
[all …]
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| D | fvp-ve-Cortex-A7x1.dts | 63 /* Reference 24MHz clock x 2 */
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <48000000>;
67 clock-output-names = "smclk";
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| D | n1sdp.dtsi | 71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <100000000>;
74 clock-output-names = "apb_pclk";
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <50000000>;
81 clock-output-names = "uartclk";
206 clock-names = "uartclk", "apb_pclk";
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| D | morello-fvp.dts | 158 clock-names = "KMIREFCLK", "apb_pclk";
166 clock-names = "KMIREFCLK", "apb_pclk";
180 #clock-cells = <1>;
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "bp:clock24mhz";
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| /trusted-firmware-a-3.7.0/plat/st/stm32mp1/ |
| D | stm32mp1_scmi.c | 131 struct stm32_scmi_clk *clock; member
139 .clock = stm32_scmi0_clock,
145 .clock = stm32_scmi1_clock,
230 return &resource->clock[n]; in find_clock()
252 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); in plat_scmi_clock_get_name() local
254 if ((clock == NULL) || in plat_scmi_clock_get_name()
255 !stm32mp_nsec_can_access_clock(clock->clock_id)) { in plat_scmi_clock_get_name()
259 return clock->name; in plat_scmi_clock_get_name()
266 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); in plat_scmi_clock_rates_array() local
268 if (clock == NULL) { in plat_scmi_clock_rates_array()
[all …]
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| /trusted-firmware-a-3.7.0/drivers/st/crypto/ |
| D | stm32_hash.c | 86 unsigned int clock; member
223 clk_enable(stm32_hash.clock); in stm32_hash_update()
265 clk_disable(stm32_hash.clock); in stm32_hash_update()
274 clk_enable(stm32_hash.clock); in stm32_hash_final()
279 clk_disable(stm32_hash.clock); in stm32_hash_final()
294 clk_disable(stm32_hash.clock); in stm32_hash_final()
314 clk_enable(stm32_hash.clock); in stm32_hash_init()
318 clk_disable(stm32_hash.clock); in stm32_hash_init()
340 if (hash_info.clock < 0) { in stm32_hash_register()
345 stm32_hash.clock = hash_info.clock; in stm32_hash_register()
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| D | stm32_rng.c | 58 unsigned long clock; member
91 clock_rate = clk_get_rate(stm32_rng.clock); in stm32_rng_clock_freq_restrain()
102 VERBOSE("RNG clk rate : %lu\n", clk_get_rate(stm32_rng.clock) >> clock_div); in stm32_rng_clock_freq_restrain()
247 if (dt_rng.clock < 0) { in stm32_rng_init()
251 stm32_rng.clock = (unsigned long)dt_rng.clock; in stm32_rng_init()
252 clk_enable(stm32_rng.clock); in stm32_rng_init()
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| /trusted-firmware-a-3.7.0/drivers/st/iwdg/ |
| D | stm32_iwdg.c | 34 unsigned long clock; member
65 clk_enable(iwdg->clock); in stm32_iwdg_refresh()
70 clk_disable(iwdg->clock); in stm32_iwdg_refresh()
98 iwdg->clock = (unsigned long)dt_info.clock; in stm32_iwdg_init()
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| /trusted-firmware-a-3.7.0/drivers/st/clk/ |
| D | stm32mp1_clk.c | 852 unsigned long clock = 0; in get_clock_rate() local
861 clock = stm32mp1_clk_get_fixed(_HSI); in get_clock_rate()
864 clock = stm32mp1_clk_get_fixed(_HSE); in get_clock_rate()
867 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
870 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
874 clock >>= stm32mp1_mpu_div[clkdiv]; in get_clock_rate()
889 clock = stm32mp1_clk_get_fixed(_HSI); in get_clock_rate()
892 clock = stm32mp1_clk_get_fixed(_HSE); in get_clock_rate()
895 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); in get_clock_rate()
903 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; in get_clock_rate()
[all …]
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| /trusted-firmware-a-3.7.0/plat/xilinx/common/ |
| D | plat_console.c | 224 static void setup_runtime_console(uint32_t clock, dt_uart_info_t *info) in setup_runtime_console() argument
231 clock, in setup_runtime_console()
236 clock, in setup_runtime_console()
260 uint32_t clock) in runtime_console_init() argument
274 setup_runtime_console(clock, uart_info); in runtime_console_init()
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| /trusted-firmware-a-3.7.0/drivers/st/gpio/ |
| D | stm32_gpio.c | 230 unsigned long clock = stm32_get_gpio_bank_clock(bank); in set_gpio() local
234 clk_enable(clock); in set_gpio()
283 clk_disable(clock); in set_gpio()
302 unsigned long clock = stm32_get_gpio_bank_clock(bank); in set_gpio_secure_cfg() local
306 clk_enable(clock); in set_gpio_secure_cfg()
314 clk_disable(clock); in set_gpio_secure_cfg()
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