1/*
2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
9#include "morello-coresight.dtsi"
10
11/ {
12	model = "Arm Morello System Development Platform";
13
14	chosen {
15		stdout-path = "serial0:115200n8";
16	};
17
18	reserved-memory {
19		#address-cells = <2>;
20		#size-cells = <2>;
21		ranges;
22
23		secure-firmware@ff000000 {
24			reg = <0 0xff000000 0 0x01000000>;
25			no-map;
26		};
27	};
28
29	/*
30	 * The timings below are just to demonstrate working cpuidle.
31	 * These values may be inaccurate.
32	 */
33	idle-states {
34		entry-method = "psci";
35
36		cluster_sleep: cluster-sleep {
37			compatible = "arm,idle-state";
38			arm,psci-suspend-param = <0x40000022>;
39			local-timer-stop;
40			entry-latency-us = <500>;
41			exit-latency-us = <1000>;
42			min-residency-us = <2500>;
43		};
44
45		cpu_sleep: cpu-sleep {
46			compatible = "arm,idle-state";
47			arm,psci-suspend-param = <0x40000002>;
48			local-timer-stop;
49			entry-latency-us = <150>;
50			exit-latency-us = <300>;
51			min-residency-us = <200>;
52		};
53	};
54
55	cpus {
56		#address-cells = <2>;
57		#size-cells = <0>;
58		cpu0: cpu0@0 {
59			compatible = "arm,armv8";
60			reg = <0x0 0x0>;
61			device_type = "cpu";
62			enable-method = "psci";
63			clocks = <&scmi_dvfs 0>;
64			operating-points = <
65				/* kHz		uV */
66				2600000		925000
67				2400000		875000
68				2200000		825000
69				2000000		775000
70				1800000		750000
71			>;
72			#cooling-cells = <2>;
73			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
74		};
75		cpu1: cpu1@100 {
76			compatible = "arm,armv8";
77			reg = <0x0 0x100>;
78			device_type = "cpu";
79			enable-method = "psci";
80			clocks = <&scmi_dvfs 0>;
81			operating-points = <
82				/* kHz		uV */
83				2600000		925000
84				2400000		875000
85				2200000		825000
86				2000000		775000
87				1800000		750000
88			>;
89			#cooling-cells = <2>;
90			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
91		};
92		cpu2: cpu2@10000 {
93			compatible = "arm,armv8";
94			reg = <0x0 0x10000>;
95			device_type = "cpu";
96			enable-method = "psci";
97			clocks = <&scmi_dvfs 1>;
98			operating-points = <
99				/* kHz		uV */
100				2600000		925000
101				2400000		875000
102				2200000		825000
103				2000000		775000
104				1800000		750000
105			>;
106			#cooling-cells = <2>;
107			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
108		};
109		cpu3: cpu3@10100 {
110			compatible = "arm,armv8";
111			reg = <0x0 0x10100>;
112			device_type = "cpu";
113			enable-method = "psci";
114			clocks = <&scmi_dvfs 1>;
115			operating-points = <
116				/* kHz		uV */
117				2600000		925000
118				2400000		875000
119				2200000		825000
120				2000000		775000
121				1800000		750000
122			>;
123			#cooling-cells = <2>;
124			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
125		};
126	};
127
128	/* The first bank of memory, memory map is actually provided by UEFI. */
129	memory@80000000 {
130		device_type = "memory";
131		/* [0x80000000-0xffffffff] */
132		reg = <0x00000000 0x80000000 0x0 0x7F000000>;
133	};
134
135	memory@8080000000 {
136		device_type = "memory";
137		/* [0x8080000000-0x83f7ffffff] */
138		reg = <0x00000080 0x80000000 0x3 0x78000000>;
139	};
140
141	smmu_pcie: iommu@4f400000 {
142		compatible = "arm,smmu-v3";
143		reg = <0 0x4f400000 0 0x40000>;
144		interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
145				<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
146				<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
147				<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
148		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
149		msi-parent = <&its2 0>;
150		#iommu-cells = <1>;
151		dma-coherent;
152	};
153
154	pcie_ctlr: pcie@28c0000000 {
155		compatible = "pci-host-ecam-generic";
156		device_type = "pci";
157		reg = <0x28 0xC0000000 0 0x10000000>;
158		bus-range = <0 255>;
159		linux,pci-domain = <0>;
160		#address-cells = <3>;
161		#size-cells = <2>;
162		dma-coherent;
163		ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>,
164		     <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>,
165			 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>;
166		#interrupt-cells = <1>;
167		interrupt-map-mask = <0 0 0 7>;
168		interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
169			<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
170			<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
171			<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
172		msi-map = <0 &its_pcie 0 0x10000>;
173		iommu-map = <0 &smmu_pcie 0 0x10000>;
174		status = "okay";
175	};
176
177	smmu_ccix: iommu@4f000000 {
178		compatible = "arm,smmu-v3";
179		reg = <0 0x4f000000 0 0x40000>;
180		interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
181				<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
182				<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
183				<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
184		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
185		msi-parent = <&its1 0>;
186		#iommu-cells = <1>;
187		dma-coherent;
188	};
189
190	ccix_pcie_ctlr: pcie@4fc0000000 {
191		compatible = "pci-host-ecam-generic";
192		device_type = "pci";
193		reg = <0x4F 0xC0000000 0 0x10000000>;
194		bus-range = <0 255>;
195		linux,pci-domain = <1>;
196		#address-cells = <3>;
197		#size-cells = <2>;
198		dma-coherent;
199		ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>,
200		     <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>,
201			 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>;
202		#interrupt-cells = <1>;
203		interrupt-map-mask = <0 0 0 7>;
204		interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
205			<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
206			<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
207			<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
208		msi-map = <0 &its_ccix 0 0x10000>;
209		iommu-map = <0 &smmu_ccix 0 0x10000>;
210		status = "okay";
211	};
212
213	smmu_dp: iommu@2ce00000 {
214		compatible = "arm,smmu-v3";
215		reg = <0 0x2ce00000 0 0x40000>;
216		interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
217				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
218				<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
219		interrupt-names = "eventq", "gerror", "cmdq-sync";
220		#iommu-cells = <1>;
221	};
222
223	dp0: display@2cc00000 {
224		#address-cells = <1>;
225		#size-cells = <0>;
226		compatible = "arm,mali-d32", "arm,mali-d71";
227		reg = <0 0x2cc00000 0 0x20000>;
228		interrupts = <0 69 4>;
229		interrupt-names = "DPU";
230		clocks = <&dpu_aclk>;
231		clock-names = "aclk";
232		iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
233			<&smmu_dp 8>;
234
235		pl0: pipeline@0 {
236			reg = <0>;
237			clocks = <&scmi_clk 1>;
238			clock-names = "pxclk";
239			pl_id = <0>;
240			ports {
241				#address-cells = <1>;
242				#size-cells = <0>;
243				port@0 {
244					reg = <0>;
245					dp_pl0_out0: endpoint {
246						remote-endpoint = <&tda998x_0_input>;
247					};
248				};
249			};
250		};
251	};
252
253	i2c@1c0f0000 {
254		compatible = "cdns,i2c-r1p14";
255		reg = <0x0 0x1c0f0000 0x0 0x1000>;
256		#address-cells = <1>;
257		#size-cells = <0>;
258		clock-frequency = <100000>;
259		i2c-sda-hold-time-ns = <500>;
260		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
261		clocks = <&dpu_aclk>;
262
263		hdmi_tx: hdmi-transmitter@70 {
264			compatible = "nxp,tda998x";
265			reg = <0x70>;
266			video-ports = <0x234501>;
267			#sound-dai-cells = <0>;
268			audio-ports = <2 0x03>;
269			port {
270				tda998x_0_input: endpoint {
271					remote-endpoint = <&dp_pl0_out0>;
272				};
273			};
274		};
275	};
276
277	dpu_aclk: dpu_aclk {
278		/* 77.1 MHz derived from 24 MHz reference clock */
279		compatible = "fixed-clock";
280		#clock-cells = <0>;
281		clock-frequency = <350000000>;
282		clock-output-names = "aclk";
283	};
284
285	gpu@2d000000 {
286		compatible = "arm,mali-bifrost";
287		reg = <0x0 0x2d000000 0x0 0x4000>;
288		interrupts =
289			<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
290			<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
291			<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
292		interrupt-names =
293			"gpu",
294			"job",
295			"mmu";
296		clocks = <&clk_gpu>;
297		clock-names = "clk_mali";
298		status = "okay";
299	};
300
301	clk_gpu: clk_gpu {
302		compatible = "fixed-clock";
303		#clock-cells = <0>;
304		clock-frequency = <650000000>;
305		clock-output-names = "clk_mali";
306	};
307
308	firmware {
309		scmi {
310			compatible = "arm,scmi";
311			mbox-names = "tx", "rx";
312			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
313			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
314			#address-cells = <1>;
315			#size-cells = <0>;
316			scmi_dvfs: protocol@13 {
317				reg = <0x13>;
318				#clock-cells = <1>;
319			};
320			scmi_clk: protocol@14 {
321				reg = <0x14>;
322				#clock-cells = <1>;
323			};
324			scmi_sensor: protocol@15 {
325				reg = <0x15>;
326				#thermal-sensor-cells = <1>;
327			};
328		};
329	};
330
331	thermal-zones {
332		clus0-thermal {
333			polling-delay-passive = <200>; /* ms */
334			polling-delay = <1000>; /* ms */
335
336			thermal-sensors = <&scmi_sensor 0>;
337
338			trips {
339				clus0_alarm: clus0-alarm {
340					temperature = <85000>; /* millicelsius */
341					hysteresis = <1000>; /* millicelsius */
342					type = "passive";
343				};
344				clus0_shutdown: clus0-shutdown {
345					temperature = <90000>; /* millicelsius */
346					hysteresis = <0>; /* millicelsius */
347					type = "critical";
348				};
349			};
350
351			cooling-maps {
352				map0 {
353					trip = <&clus0_alarm>;
354					cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
355				};
356			};
357		};
358		clus1-thermal {
359			polling-delay-passive = <200>; /* ms */
360			polling-delay = <1000>; /* ms */
361
362			thermal-sensors = <&scmi_sensor 1>;
363			trips {
364				clus1_alarm: clus1-alarm {
365					temperature = <85000>; /* millicelsius */
366					hysteresis = <1000>; /* millicelsius */
367					type = "passive";
368				};
369				clus1_shutdown: clus1-shutdown {
370					temperature = <90000>; /* millicelsius */
371					hysteresis = <0>; /* millicelsius */
372					type = "critical";
373				};
374			};
375
376			cooling-maps {
377				map0 {
378					trip = <&clus1_alarm>;
379					cooling-device = <&cpu2 4 4>, <&cpu3 4 4>;
380				};
381			};
382		};
383		sys-thermal {
384			polling-delay-passive = <200>; /* ms */
385			polling-delay = <1000>; /* ms */
386
387			thermal-sensors = <&scmi_sensor 2>;
388			trips {
389				sys_alarm: sys-alarm {
390					temperature = <85000>; /* millicelsius */
391					hysteresis = <1000>; /* millicelsius */
392					type = "passive";
393				};
394				sys_shutdown: sys-shutdown {
395					temperature = <90000>; /* millicelsius */
396					hysteresis = <0>; /* millicelsius */
397					type = "critical";
398				};
399			};
400
401			cooling-maps {
402				map0 {
403					trip = <&sys_alarm>;
404					cooling-device = <&cpu0 4 4>,
405						<&cpu1 4 4>,
406						<&cpu2 4 4>,
407						<&cpu3 4 4>;
408				};
409			};
410		};
411	};
412
413	iofpga_i2s: xlnx-i2s@1c150000 {
414		#sound-dai-cells = <0>;
415		compatible = "xlnx,i2s-transmitter-1.0";
416		#address-cells = <1>;
417		#size-cells = <0>;
418		reg = <0x0 0x1c150000 0x0 0x10000>;
419		xlnx,dwidth = <0x18>;
420		xlnx,num-channels = <1>;
421	};
422
423	audio_formatter: audio-formatter@1c100000 {
424		compatible = "xlnx,audio-formatter-1.0";
425		reg = <0x0 0x1c000000 0x0 0x10000>;
426		#sound-dai-cells = <0>;
427		interrupt-names = "irq_mm2s";
428		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
429		clock-names = "s_axi_lite_aclk", "aud_mclk", "m_axis_mm2s_aclk";
430		clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>;
431	};
432
433	sound {
434		compatible = "simple-audio-card";
435		simple-audio-card,format = "i2s";
436		simple-audio-card,bitclock-master = <&audio_master>;
437		simple-audio-card,frame-master = <&audio_master>;
438		audio_master: simple-audio-card,cpu {
439			sound-dai = <&iofpga_i2s>;
440			clocks = <&i2s_audclk>;
441		};
442
443		simple-audio-card,codec {
444			sound-dai = <&hdmi_tx>;
445		};
446
447		simple-audio-card,plat {
448			sound-dai = <&audio_formatter>;
449		};
450	};
451
452	i2s_audclk: i2s_audclk {
453		compatible = "fixed-clock";
454		#clock-cells = <0>;
455		clock-frequency = <12288000>;
456		clock-output-names = "iofpga:i2s_audclk";
457	};
458};
459
460&gic {
461	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
462	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
463	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
464
465	its1: msi-controller@30040000 {
466		compatible = "arm,gic-v3-its";
467		msi-controller;
468		#msi-cells = <1>;
469		reg = <0x0 0x30040000 0x0 0x20000>;
470	};
471
472	its2: msi-controller@30060000 {
473		compatible = "arm,gic-v3-its";
474		msi-controller;
475		#msi-cells = <1>;
476		reg = <0x0 0x30060000 0x0 0x20000>;
477	};
478
479	its_ccix: msi-controller@30080000 {
480		compatible = "arm,gic-v3-its";
481		msi-controller;
482		#msi-cells = <1>;
483		reg = <0x0 0x30080000 0x0 0x20000>;
484	};
485
486	its_pcie: msi-controller@300a0000 {
487		compatible = "arm,gic-v3-its";
488		msi-controller;
489		#msi-cells = <1>;
490		reg = <0x0 0x300a0000 0x0 0x20000>;
491	};
492};
493