1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/clock/stm32mp13-clks.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22			clocks = <&rcc CK_MPU>;
23			clock-names = "cpu";
24			nvmem-cells = <&part_number_otp>;
25			nvmem-cell-names = "part_number";
26		};
27	};
28
29	clocks {
30		clk_csi: clk-csi {
31			#clock-cells = <0>;
32			compatible = "fixed-clock";
33			clock-frequency = <4000000>;
34		};
35
36		clk_hse: clk-hse {
37			#clock-cells = <0>;
38			compatible = "fixed-clock";
39			clock-frequency = <24000000>;
40		};
41
42		clk_hsi: clk-hsi {
43			#clock-cells = <0>;
44			compatible = "fixed-clock";
45			clock-frequency = <64000000>;
46		};
47
48		clk_lse: clk-lse {
49			#clock-cells = <0>;
50			compatible = "fixed-clock";
51			clock-frequency = <32768>;
52		};
53
54		clk_lsi: clk-lsi {
55			#clock-cells = <0>;
56			compatible = "fixed-clock";
57			clock-frequency = <32000>;
58		};
59	};
60
61	intc: interrupt-controller@a0021000 {
62		compatible = "arm,cortex-a7-gic";
63		#interrupt-cells = <3>;
64		interrupt-controller;
65		reg = <0xa0021000 0x1000>,
66		      <0xa0022000 0x2000>;
67	};
68
69	psci {
70		compatible = "arm,psci-1.0";
71		method = "smc";
72	};
73
74	soc {
75		compatible = "simple-bus";
76		#address-cells = <1>;
77		#size-cells = <1>;
78		interrupt-parent = <&intc>;
79		ranges;
80
81		usart3: serial@4000f000 {
82			compatible = "st,stm32h7-uart";
83			reg = <0x4000f000 0x400>;
84			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
85			clocks = <&rcc USART3_K>;
86			resets = <&rcc USART3_R>;
87			status = "disabled";
88		};
89
90		uart4: serial@40010000 {
91			compatible = "st,stm32h7-uart";
92			reg = <0x40010000 0x400>;
93			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
94			clocks = <&rcc UART4_K>;
95			resets = <&rcc UART4_R>;
96			status = "disabled";
97		};
98
99		uart5: serial@40011000 {
100			compatible = "st,stm32h7-uart";
101			reg = <0x40011000 0x400>;
102			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
103			clocks = <&rcc UART5_K>;
104			resets = <&rcc UART5_R>;
105			status = "disabled";
106		};
107
108		uart7: serial@40018000 {
109			compatible = "st,stm32h7-uart";
110			reg = <0x40018000 0x400>;
111			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112			clocks = <&rcc UART7_K>;
113			resets = <&rcc UART7_R>;
114			status = "disabled";
115		};
116
117		uart8: serial@40019000 {
118			compatible = "st,stm32h7-uart";
119			reg = <0x40019000 0x400>;
120			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
121			clocks = <&rcc UART8_K>;
122			resets = <&rcc UART8_R>;
123			status = "disabled";
124		};
125
126		usart6: serial@44003000 {
127			compatible = "st,stm32h7-uart";
128			reg = <0x44003000 0x400>;
129			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
130			clocks = <&rcc USART6_K>;
131			resets = <&rcc USART6_R>;
132			status = "disabled";
133		};
134
135		usbotg_hs: usb-otg@49000000 {
136			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
137			reg = <0x49000000 0x40000>;
138			clocks = <&rcc USBO_K>;
139			clock-names = "otg";
140			resets = <&rcc USBO_R>;
141			reset-names = "dwc2";
142			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
143			g-rx-fifo-size = <512>;
144			g-np-tx-fifo-size = <32>;
145			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
146			dr_mode = "otg";
147			usb33d-supply = <&usb33>;
148			status = "disabled";
149		};
150
151		usart1: serial@4c000000 {
152			compatible = "st,stm32h7-uart";
153			reg = <0x4c000000 0x400>;
154			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
155			clocks = <&rcc USART1_K>;
156			resets = <&rcc USART1_R>;
157			status = "disabled";
158		};
159
160		usart2: serial@4c001000 {
161			compatible = "st,stm32h7-uart";
162			reg = <0x4c001000 0x400>;
163			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
164			clocks = <&rcc USART2_K>;
165			resets = <&rcc USART2_R>;
166			status = "disabled";
167		};
168
169		i2c3: i2c@4c004000 {
170			compatible = "st,stm32mp13-i2c";
171			reg = <0x4c004000 0x400>;
172			interrupt-names = "event", "error";
173			interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
174					      <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
175			clocks = <&rcc I2C3_K>;
176			resets = <&rcc I2C3_R>;
177			#address-cells = <1>;
178			#size-cells = <0>;
179			st,syscfg-fmp = <&syscfg 0x4 0x4>;
180			i2c-analog-filter;
181			status = "disabled";
182		};
183
184		i2c4: i2c@4c005000 {
185			compatible = "st,stm32mp13-i2c";
186			reg = <0x4c005000 0x400>;
187			interrupt-names = "event", "error";
188			interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
189					      <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
190			clocks = <&rcc I2C4_K>;
191			resets = <&rcc I2C4_R>;
192			#address-cells = <1>;
193			#size-cells = <0>;
194			st,syscfg-fmp = <&syscfg 0x4 0x8>;
195			i2c-analog-filter;
196			status = "disabled";
197		};
198
199		i2c5: i2c@4c006000 {
200			compatible = "st,stm32mp13-i2c";
201			reg = <0x4c006000 0x400>;
202			interrupt-names = "event", "error";
203			interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
204					      <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
205			clocks = <&rcc I2C5_K>;
206			resets = <&rcc I2C5_R>;
207			#address-cells = <1>;
208			#size-cells = <0>;
209			st,syscfg-fmp = <&syscfg 0x4 0x10>;
210			i2c-analog-filter;
211			status = "disabled";
212		};
213
214		rcc: rcc@50000000 {
215			compatible = "st,stm32mp13-rcc", "syscon";
216			reg = <0x50000000 0x1000>;
217			#address-cells = <1>;
218			#size-cells = <0>;
219			#clock-cells = <1>;
220			#reset-cells = <1>;
221			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
222			secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
223			secure-interrupt-names = "wakeup";
224		};
225
226		pwr_regulators: pwr@50001000 {
227			compatible = "st,stm32mp1,pwr-reg";
228			reg = <0x50001000 0x10>;
229
230			reg11: reg11 {
231				regulator-name = "reg11";
232				regulator-min-microvolt = <1100000>;
233				regulator-max-microvolt = <1100000>;
234			};
235
236			reg18: reg18 {
237				regulator-name = "reg18";
238				regulator-min-microvolt = <1800000>;
239				regulator-max-microvolt = <1800000>;
240			};
241
242			usb33: usb33 {
243				regulator-name = "usb33";
244				regulator-min-microvolt = <3300000>;
245				regulator-max-microvolt = <3300000>;
246			};
247		};
248
249		exti: interrupt-controller@5000d000 {
250			compatible = "st,stm32mp13-exti", "syscon";
251			interrupt-controller;
252			#interrupt-cells = <2>;
253			reg = <0x5000d000 0x400>;
254		};
255
256		syscfg: syscon@50020000 {
257			compatible = "st,stm32mp157-syscfg", "syscon";
258			reg = <0x50020000 0x400>;
259			clocks = <&rcc SYSCFG>;
260		};
261
262		hash: hash@54003000 {
263			compatible = "st,stm32mp13-hash";
264			reg = <0x54003000 0x400>;
265			clocks = <&rcc HASH1>;
266			resets = <&rcc HASH1_R>;
267			status = "disabled";
268		};
269
270		rng: rng@54004000 {
271			compatible = "st,stm32mp13-rng";
272			reg = <0x54004000 0x400>;
273			clocks = <&rcc RNG1_K>;
274			resets = <&rcc RNG1_R>;
275			status = "disabled";
276		};
277
278		fmc: memory-controller@58002000 {
279			compatible = "st,stm32mp1-fmc2-ebi";
280			reg = <0x58002000 0x1000>;
281			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
282				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
283				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
284				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
285				 <4 0 0x80000000 0x10000000>; /* NAND */
286			#address-cells = <2>;
287			#size-cells = <1>;
288			clocks = <&rcc FMC_K>;
289			resets = <&rcc FMC_R>;
290			status = "disabled";
291
292			nand-controller@4,0 {
293				compatible = "st,stm32mp1-fmc2-nfc";
294				reg = <4 0x00000000 0x1000>,
295				      <4 0x08010000 0x1000>,
296				      <4 0x08020000 0x1000>,
297				      <4 0x01000000 0x1000>,
298				      <4 0x09010000 0x1000>,
299				      <4 0x09020000 0x1000>;
300				#address-cells = <1>;
301				#size-cells = <0>;
302				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
303				status = "disabled";
304			};
305		};
306
307		qspi: spi@58003000 {
308			compatible = "st,stm32f469-qspi";
309			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
310			reg-names = "qspi", "qspi_mm";
311			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
312			clocks = <&rcc QSPI_K>;
313			resets = <&rcc QSPI_R>;
314			status = "disabled";
315		};
316
317		sdmmc1: mmc@58005000 {
318			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
319			arm,primecell-periphid = <0x20253180>;
320			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
321			clocks = <&rcc SDMMC1_K>;
322			clock-names = "apb_pclk";
323			resets = <&rcc SDMMC1_R>;
324			cap-sd-highspeed;
325			cap-mmc-highspeed;
326			max-frequency = <130000000>;
327			status = "disabled";
328		};
329
330		sdmmc2: mmc@58007000 {
331			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
332			arm,primecell-periphid = <0x20253180>;
333			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
334			clocks = <&rcc SDMMC2_K>;
335			clock-names = "apb_pclk";
336			resets = <&rcc SDMMC2_R>;
337			cap-sd-highspeed;
338			cap-mmc-highspeed;
339			max-frequency = <130000000>;
340			status = "disabled";
341		};
342
343		usbh_ohci: usb@5800c000 {
344			compatible = "generic-ohci";
345			reg = <0x5800c000 0x1000>;
346			clocks = <&rcc USBH>;
347			resets = <&rcc USBH_R>;
348			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
349			status = "disabled";
350		};
351
352		usbh_ehci: usb@5800d000 {
353			compatible = "generic-ehci";
354			reg = <0x5800d000 0x1000>;
355			clocks = <&rcc USBH>;
356			resets = <&rcc USBH_R>;
357			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
358			companion = <&usbh_ohci>;
359			status = "disabled";
360		};
361
362		iwdg2: watchdog@5a002000 {
363			compatible = "st,stm32mp1-iwdg";
364			reg = <0x5a002000 0x400>;
365			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
366			clock-names = "pclk", "lsi";
367			status = "disabled";
368		};
369
370		ddr: ddr@5a003000 {
371			compatible = "st,stm32mp13-ddr";
372			reg = <0x5a003000 0x550>, <0x5a004000 0x234>;
373			clocks = <&rcc AXIDCG>,
374				 <&rcc DDRC1>,
375				 <&rcc DDRPHYC>,
376				 <&rcc DDRCAPB>,
377				 <&rcc DDRPHYCAPB>;
378			clock-names = "axidcg",
379				      "ddrc1",
380				      "ddrphyc",
381				      "ddrcapb",
382				      "ddrphycapb";
383		};
384
385		usbphyc: usbphyc@5a006000 {
386			#address-cells = <1>;
387			#size-cells = <0>;
388			#clock-cells = <0>;
389			compatible = "st,stm32mp1-usbphyc";
390			reg = <0x5a006000 0x1000>;
391			clocks = <&rcc USBPHY_K>;
392			resets = <&rcc USBPHY_R>;
393			vdda1v1-supply = <&reg11>;
394			vdda1v8-supply = <&reg18>;
395			status = "disabled";
396
397			usbphyc_port0: usb-phy@0 {
398				#phy-cells = <0>;
399				reg = <0>;
400			};
401
402			usbphyc_port1: usb-phy@1 {
403				#phy-cells = <1>;
404				reg = <1>;
405			};
406		};
407
408		iwdg1: watchdog@5c003000 {
409			compatible = "st,stm32mp1-iwdg";
410			reg = <0x5c003000 0x400>;
411			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
412			clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
413			clock-names = "pclk", "lsi";
414			status = "disabled";
415		};
416
417		bsec: efuse@5c005000 {
418			compatible = "st,stm32mp13-bsec";
419			reg = <0x5c005000 0x400>;
420			#address-cells = <1>;
421			#size-cells = <1>;
422
423			cfg0_otp: cfg0_otp@0 {
424				reg = <0x0 0x2>;
425			};
426			part_number_otp: part-number-otp@4 {
427				reg = <0x4 0x2>;
428			};
429			monotonic_otp: monotonic_otp@10 {
430				reg = <0x10 0x4>;
431			};
432			nand_otp: cfg9_otp@24 {
433				reg = <0x24 0x4>;
434			};
435			nand2_otp: cfg10_otp@28 {
436				reg = <0x28 0x4>;
437			};
438			uid_otp: uid_otp@34 {
439				reg = <0x34 0xc>;
440			};
441			hw2_otp: hw2_otp@48 {
442				reg = <0x48 0x4>;
443			};
444			ts_cal1: calib@5c {
445				reg = <0x5c 0x2>;
446			};
447			ts_cal2: calib@5e {
448				reg = <0x5e 0x2>;
449			};
450			pkh_otp: pkh_otp@60 {
451				reg = <0x60 0x20>;
452			};
453			mac_addr: mac_addr@e4 {
454				reg = <0xe4 0xc>;
455				st,non-secure-otp;
456			};
457			enckey_otp: enckey_otp@170 {
458				reg = <0x170 0x10>;
459			};
460		};
461		/*
462		 * Break node order to solve dependency probe issue between
463		 * pinctrl and exti.
464		 */
465		pinctrl: pinctrl@50002000 {
466			#address-cells = <1>;
467			#size-cells = <1>;
468			compatible = "st,stm32mp135-pinctrl";
469			ranges = <0 0x50002000 0x8400>;
470			interrupt-parent = <&exti>;
471			st,syscfg = <&exti 0x60 0xff>;
472
473			gpioa: gpio@50002000 {
474				gpio-controller;
475				#gpio-cells = <2>;
476				interrupt-controller;
477				#interrupt-cells = <2>;
478				reg = <0x0 0x400>;
479				clocks = <&rcc GPIOA>;
480				st,bank-name = "GPIOA";
481				ngpios = <16>;
482				gpio-ranges = <&pinctrl 0 0 16>;
483			};
484
485			gpiob: gpio@50003000 {
486				gpio-controller;
487				#gpio-cells = <2>;
488				interrupt-controller;
489				#interrupt-cells = <2>;
490				reg = <0x1000 0x400>;
491				clocks = <&rcc GPIOB>;
492				st,bank-name = "GPIOB";
493				ngpios = <16>;
494				gpio-ranges = <&pinctrl 0 16 16>;
495			};
496
497			gpioc: gpio@50004000 {
498				gpio-controller;
499				#gpio-cells = <2>;
500				interrupt-controller;
501				#interrupt-cells = <2>;
502				reg = <0x2000 0x400>;
503				clocks = <&rcc GPIOC>;
504				st,bank-name = "GPIOC";
505				ngpios = <16>;
506				gpio-ranges = <&pinctrl 0 32 16>;
507			};
508
509			gpiod: gpio@50005000 {
510				gpio-controller;
511				#gpio-cells = <2>;
512				interrupt-controller;
513				#interrupt-cells = <2>;
514				reg = <0x3000 0x400>;
515				clocks = <&rcc GPIOD>;
516				st,bank-name = "GPIOD";
517				ngpios = <16>;
518				gpio-ranges = <&pinctrl 0 48 16>;
519			};
520
521			gpioe: gpio@50006000 {
522				gpio-controller;
523				#gpio-cells = <2>;
524				interrupt-controller;
525				#interrupt-cells = <2>;
526				reg = <0x4000 0x400>;
527				clocks = <&rcc GPIOE>;
528				st,bank-name = "GPIOE";
529				ngpios = <16>;
530				gpio-ranges = <&pinctrl 0 64 16>;
531			};
532
533			gpiof: gpio@50007000 {
534				gpio-controller;
535				#gpio-cells = <2>;
536				interrupt-controller;
537				#interrupt-cells = <2>;
538				reg = <0x5000 0x400>;
539				clocks = <&rcc GPIOF>;
540				st,bank-name = "GPIOF";
541				ngpios = <16>;
542				gpio-ranges = <&pinctrl 0 80 16>;
543			};
544
545			gpiog: gpio@50008000 {
546				gpio-controller;
547				#gpio-cells = <2>;
548				interrupt-controller;
549				#interrupt-cells = <2>;
550				reg = <0x6000 0x400>;
551				clocks = <&rcc GPIOG>;
552				st,bank-name = "GPIOG";
553				ngpios = <16>;
554				gpio-ranges = <&pinctrl 0 96 16>;
555			};
556
557			gpioh: gpio@50009000 {
558				gpio-controller;
559				#gpio-cells = <2>;
560				interrupt-controller;
561				#interrupt-cells = <2>;
562				reg = <0x7000 0x400>;
563				clocks = <&rcc GPIOH>;
564				st,bank-name = "GPIOH";
565				ngpios = <15>;
566				gpio-ranges = <&pinctrl 0 112 15>;
567			};
568
569			gpioi: gpio@5000a000 {
570				gpio-controller;
571				#gpio-cells = <2>;
572				interrupt-controller;
573				#interrupt-cells = <2>;
574				reg = <0x8000 0x400>;
575				clocks = <&rcc GPIOI>;
576				st,bank-name = "GPIOI";
577				ngpios = <8>;
578				gpio-ranges = <&pinctrl 0 128 8>;
579			};
580		};
581	};
582};
583