1/*
2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
9
10/ {
11	model = "Arm Morello Fixed Virtual Platform";
12
13	chosen {
14		stdout-path = "serial0:115200n8";
15	};
16
17	reserved-memory {
18		#address-cells = <2>;
19		#size-cells = <2>;
20		ranges;
21
22		secure-firmware@ff000000 {
23			reg = <0 0xff000000 0 0x01000000>;
24			no-map;
25		};
26	};
27
28	/*
29	 * The timings below are just to demonstrate working cpuidle.
30	 * These values may be inaccurate.
31	 */
32	idle-states {
33		entry-method = "psci";
34
35		cluster_sleep: cluster-sleep {
36			compatible = "arm,idle-state";
37			arm,psci-suspend-param = <0x40000022>;
38			local-timer-stop;
39			entry-latency-us = <500>;
40			exit-latency-us = <1000>;
41			min-residency-us = <2500>;
42		};
43
44		cpu_sleep: cpu-sleep {
45			compatible = "arm,idle-state";
46			arm,psci-suspend-param = <0x40000002>;
47			local-timer-stop;
48			entry-latency-us = <150>;
49			exit-latency-us = <300>;
50			min-residency-us = <200>;
51		};
52	};
53
54	cpus {
55		#address-cells = <2>;
56		#size-cells = <0>;
57
58		cpu-map {
59			cluster0 {
60				core0 {
61					cpu = <&CPU0>;
62				};
63				core1 {
64					cpu = <&CPU1>;
65				};
66			};
67			cluster1 {
68				core0 {
69					cpu = <&CPU2>;
70				};
71				core1 {
72					cpu = <&CPU3>;
73				};
74			};
75		};
76		CPU0: cpu0@0 {
77			compatible = "arm,armv8";
78			reg = <0x0 0x0>;
79			device_type = "cpu";
80			enable-method = "psci";
81			clocks = <&scmi_dvfs 0>;
82			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
83		};
84		CPU1: cpu1@100 {
85			compatible = "arm,armv8";
86			reg = <0x0 0x100>;
87			device_type = "cpu";
88			enable-method = "psci";
89			clocks = <&scmi_dvfs 0>;
90			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
91		};
92		CPU2: cpu2@10000 {
93			compatible = "arm,armv8";
94			reg = <0x0 0x10000>;
95			device_type = "cpu";
96			enable-method = "psci";
97			clocks = <&scmi_dvfs 1>;
98			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
99		};
100		CPU3: cpu3@10100 {
101			compatible = "arm,armv8";
102			reg = <0x0 0x10100>;
103			device_type = "cpu";
104			enable-method = "psci";
105			clocks = <&scmi_dvfs 1>;
106			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
107		};
108	};
109
110	/* The first bank of memory, memory map is actually provided by UEFI. */
111	memory@80000000 {
112		device_type = "memory";
113		/* [0x80000000-0xffffffff] */
114		reg = <0x00000000 0x80000000 0x0 0x80000000>;
115	};
116
117	memory@8080000000 {
118		device_type = "memory";
119		/* [0x8080000000-0x83ffffffff] */
120		reg = <0x00000080 0x80000000 0x1 0x80000000>;
121	};
122
123	virtio_block@1c170000 {
124		compatible = "virtio,mmio";
125		reg = <0x0 0x1c170000 0x0 0x200>;
126		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
127	};
128
129	virtio_net@1c180000 {
130		compatible = "virtio,mmio";
131		reg = <0x0 0x1c180000 0x0 0x200>;
132		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
133	};
134
135	virtio_rng@1c190000 {
136		compatible = "virtio,mmio";
137		reg = <0x0 0x1c190000 0x0 0x200>;
138		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
139	};
140
141	virtio_p9@1c1a0000 {
142		compatible = "virtio,mmio";
143		reg = <0x0 0x1c1a0000 0x0 0x200>;
144		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
145	};
146
147	ethernet@1d100000 {
148		compatible = "smsc,lan91c111";
149		reg = <0x0 0x1d100000 0x0 0x10000>;
150		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
151	};
152
153	kmi@1c150000 {
154		compatible = "arm,pl050", "arm,primecell";
155		reg = <0x0 0x1c150000 0x0 0x1000>;
156		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
157		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
158		clock-names = "KMIREFCLK", "apb_pclk";
159	};
160
161	kmi@1c160000 {
162		compatible = "arm,pl050", "arm,primecell";
163		reg = <0x0 0x1c160000 0x0 0x1000>;
164		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
165		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
166		clock-names = "KMIREFCLK", "apb_pclk";
167	};
168
169	firmware {
170		scmi {
171			compatible = "arm,scmi";
172			mbox-names = "tx", "rx";
173			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
174			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
175			#address-cells = <1>;
176			#size-cells = <0>;
177
178			scmi_dvfs: protocol@13 {
179				reg = <0x13>;
180				#clock-cells = <1>;
181			};
182		};
183	};
184
185	bp_clock24mhz: clock24mhz {
186		compatible = "fixed-clock";
187		#clock-cells = <0>;
188		clock-frequency = <24000000>;
189		clock-output-names = "bp:clock24mhz";
190	};
191};
192
193&gic {
194	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
195	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
196	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
197};
198