1/*
2 * Copyright (c) 2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	/*
11	 * Morello TRMs specify the size for these coresight components as 64K.
12	 * The actual size is just 4K though 64K is reserved. Access to the
13	 * unmapped reserved region results in a DECERR response.
14	 */
15	cpu_debug0: cpu-debug@402010000 {
16		compatible = "arm,coresight-cpu-debug", "arm,primecell";
17		cpu = <&cpu0>;
18		reg = <0x4 0x02010000 0x0 0x1000>;
19		clocks = <&soc_refclk50mhz>;
20		clock-names = "apb_pclk";
21	};
22
23	etm0: etm@402040000 {
24		compatible = "arm,coresight-etm4x", "arm,primecell";
25		cpu = <&cpu0>;
26		reg = <0x4 0x02040000 0 0x1000>;
27		clocks = <&soc_refclk50mhz>;
28		clock-names = "apb_pclk";
29		out-ports {
30			port {
31				cluster0_etm0_out_port: endpoint {
32					remote-endpoint = <&cluster0_static_funnel_in_port0>;
33				};
34			};
35		};
36	};
37
38	cpu_debug1: cpu-debug@402110000 {
39		compatible = "arm,coresight-cpu-debug", "arm,primecell";
40		cpu = <&cpu1>;
41		reg = <0x4 0x02110000 0x0 0x1000>;
42		clocks = <&soc_refclk50mhz>;
43		clock-names = "apb_pclk";
44	};
45
46	etm1: etm@402140000 {
47		compatible = "arm,coresight-etm4x", "arm,primecell";
48		cpu = <&cpu1>;
49		reg = <0x4 0x02140000 0 0x1000>;
50		clocks = <&soc_refclk50mhz>;
51		clock-names = "apb_pclk";
52		out-ports {
53			port {
54				cluster0_etm1_out_port: endpoint {
55					remote-endpoint = <&cluster0_static_funnel_in_port1>;
56				};
57			};
58		};
59	};
60
61	cpu_debug2: cpu-debug@403010000 {
62		compatible = "arm,coresight-cpu-debug", "arm,primecell";
63		cpu = <&cpu2>;
64		reg = <0x4 0x03010000 0x0 0x1000>;
65		clocks = <&soc_refclk50mhz>;
66		clock-names = "apb_pclk";
67	};
68
69	etm2: etm@403040000 {
70		compatible = "arm,coresight-etm4x", "arm,primecell";
71		cpu = <&cpu2>;
72		reg = <0x4 0x03040000 0 0x1000>;
73		clocks = <&soc_refclk50mhz>;
74		clock-names = "apb_pclk";
75		out-ports {
76			port {
77				cluster1_etm0_out_port: endpoint {
78					remote-endpoint = <&cluster1_static_funnel_in_port0>;
79				};
80			};
81		};
82	};
83
84	cpu_debug3: cpu-debug@403110000 {
85		compatible = "arm,coresight-cpu-debug", "arm,primecell";
86		cpu = <&cpu3>;
87		reg = <0x4 0x03110000 0x0 0x1000>;
88		clocks = <&soc_refclk50mhz>;
89		clock-names = "apb_pclk";
90	};
91
92	etm3: etm@403140000 {
93		compatible = "arm,coresight-etm4x", "arm,primecell";
94		cpu = <&cpu3>;
95		reg = <0x4 0x03140000 0 0x1000>;
96		clocks = <&soc_refclk50mhz>;
97		clock-names = "apb_pclk";
98		out-ports {
99			port {
100				cluster1_etm1_out_port: endpoint {
101					remote-endpoint = <&cluster1_static_funnel_in_port1>;
102				};
103			};
104		};
105	};
106
107	sfunnel0: funnel@0 { /* cluster0 funnel */
108		compatible = "arm,coresight-static-funnel";
109		out-ports {
110			port {
111				cluster0_static_funnel_out_port: endpoint {
112					remote-endpoint = <&etf0_in_port>;
113				};
114			};
115		};
116		in-ports {
117			#address-cells = <1>;
118			#size-cells = <0>;
119			port@0 {
120				reg = <0>;
121				cluster0_static_funnel_in_port0: endpoint {
122					remote-endpoint = <&cluster0_etm0_out_port>;
123				};
124			};
125			port@1 {
126				reg = <1>;
127				cluster0_static_funnel_in_port1: endpoint {
128					remote-endpoint = <&cluster0_etm1_out_port>;
129				};
130			};
131		};
132	};
133
134	sfunnel1: funnel@1 { /* cluster1 funnel */
135		compatible = "arm,coresight-static-funnel";
136		out-ports {
137			port {
138				cluster1_static_funnel_out_port: endpoint {
139					remote-endpoint = <&etf1_in_port>;
140				};
141			};
142		};
143		in-ports {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			port@0 {
147				reg = <0>;
148				cluster1_static_funnel_in_port0: endpoint {
149					remote-endpoint = <&cluster1_etm0_out_port>;
150				};
151			};
152			port@1 {
153				reg = <1>;
154				cluster1_static_funnel_in_port1: endpoint {
155					remote-endpoint = <&cluster1_etm1_out_port>;
156				};
157			};
158		};
159	};
160
161	tpiu@400130000 {
162		compatible = "arm,coresight-tpiu", "arm,primecell";
163		reg = <0x4 0x00130000 0 0x1000>;
164		clocks = <&soc_refclk50mhz>;
165		clock-names = "apb_pclk";
166		in-ports {
167			port {
168				tpiu_in_port: endpoint {
169					remote-endpoint = <&replicator_out_port0>;
170				};
171			};
172		};
173	};
174
175	main_funnel: funnel@4000a0000 {
176		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
177		reg = <0x4 0x000a0000 0 0x1000>;
178		clocks = <&soc_refclk50mhz>;
179		clock-names = "apb_pclk";
180		out-ports {
181			port {
182				main_funnel_out_port: endpoint {
183					remote-endpoint = <&replicator_in_port>;
184				};
185			};
186		};
187		main_funnel_in_ports: in-ports {
188			#address-cells = <1>;
189			#size-cells = <0>;
190			port@0 {
191				reg = <0>;
192				main_funnel_in_port0: endpoint {
193					remote-endpoint = <&cluster_funnel_out_port>;
194				};
195			};
196			port@5 {
197				reg = <5>;
198				main_funnel_in_port5: endpoint {
199					remote-endpoint = <&etf2_out_port>;
200				};
201			};
202		};
203	};
204
205	etr@400120000 {
206		compatible = "arm,coresight-tmc", "arm,primecell";
207		reg = <0x4 0x00120000 0 0x1000>;
208		clocks = <&soc_refclk50mhz>;
209		clock-names = "apb_pclk";
210		arm,scatter-gather;
211		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
212		interrupt-names = "etrbufint";
213		in-ports {
214			port {
215				etr_in_port: endpoint {
216					remote-endpoint = <&replicator_out_port1>;
217				};
218			};
219		};
220	};
221
222	replicator@400110000 {
223		compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
224		reg = <0x4 0x00110000 0 0x1000>;
225		clocks = <&soc_refclk50mhz>;
226		clock-names = "apb_pclk";
227		out-ports {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			/* replicator output ports */
231			port@0 {
232				reg = <0>;
233				replicator_out_port0: endpoint {
234					remote-endpoint = <&tpiu_in_port>;
235				};
236			};
237			port@1 {
238				reg = <1>;
239				replicator_out_port1: endpoint {
240					remote-endpoint = <&etr_in_port>;
241				};
242			};
243		};
244		in-ports {
245			port {
246				replicator_in_port: endpoint {
247					remote-endpoint = <&main_funnel_out_port>;
248				};
249			};
250		};
251	};
252
253	cluster_funnel: funnel@4000b0000 {
254		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
255		reg = <0x4 0x000b0000 0 0x1000>;
256		clocks = <&soc_refclk50mhz>;
257		clock-names = "apb_pclk";
258		out-ports {
259			port {
260				cluster_funnel_out_port: endpoint {
261					remote-endpoint = <&main_funnel_in_port0>;
262				};
263			};
264		};
265		in-ports {
266			#address-cells = <1>;
267			#size-cells = <0>;
268			port@0 {
269				reg = <0>;
270				cluster_funnel_in_port0: endpoint {
271					remote-endpoint = <&etf0_out_port>;
272				};
273			};
274			port@1 {
275				reg = <1>;
276				cluster_funnel_in_port1: endpoint {
277					remote-endpoint = <&etf1_out_port>;
278				};
279			};
280		};
281	};
282
283	etf0: etf@400410000 {
284		compatible = "arm,coresight-tmc", "arm,primecell";
285		reg = <0x4 0x00410000 0 0x1000>;
286		clocks = <&soc_refclk50mhz>;
287		clock-names = "apb_pclk";
288		in-ports {
289			port {
290				etf0_in_port: endpoint {
291					remote-endpoint = <&cluster0_static_funnel_out_port>;
292				};
293			};
294		};
295		out-ports {
296			port {
297				etf0_out_port: endpoint {
298					remote-endpoint = <&cluster_funnel_in_port0>;
299				};
300			};
301		};
302	};
303
304	etf1: etf@400420000 {
305		compatible = "arm,coresight-tmc", "arm,primecell";
306		reg = <0x4 0x00420000 0 0x1000>;
307		clocks = <&soc_refclk50mhz>;
308		clock-names = "apb_pclk";
309		in-ports {
310			port {
311				etf1_in_port: endpoint {
312					remote-endpoint = <&cluster1_static_funnel_out_port>;
313				};
314			};
315		};
316		out-ports {
317			port {
318				etf1_out_port: endpoint {
319					remote-endpoint = <&cluster_funnel_in_port1>;
320				};
321			};
322		};
323	};
324
325	stm_etf: etf@400010000 {
326		compatible = "arm,coresight-tmc", "arm,primecell";
327		reg = <0x4 0x00010000 0 0x1000>;
328		clocks = <&soc_refclk50mhz>;
329		clock-names = "apb_pclk";
330		in-ports {
331			port {
332				etf2_in_port: endpoint {
333					remote-endpoint = <&stm_out_port>;
334				};
335			};
336		};
337		out-ports {
338			port {
339				etf2_out_port: endpoint {
340					remote-endpoint = <&main_funnel_in_port5>;
341				};
342			};
343		};
344	};
345
346	stm@400800000 {
347		compatible = "arm,coresight-stm", "arm,primecell";
348		reg = <4 0x00800000 0 0x1000>,
349		      <0 0x4d000000 0 0x1000000>;
350		reg-names = "stm-base", "stm-stimulus-base";
351		clocks = <&soc_refclk50mhz>;
352		clock-names = "apb_pclk";
353		out-ports {
354			port {
355				stm_out_port: endpoint {
356					remote-endpoint = <&etf2_in_port>;
357				};
358			};
359		};
360	};
361};
362