Searched refs:ISR (Results 1 – 25 of 103) sorted by relevance
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19 Size of the stack used in the driver for nRF USBD ISR event handling.22 int "nRF UDC driver maximum number of ISR event messages"26 Maximum number of messages for handling of nRF USBD ISR events.
30 int "UDC AMBIQ maximum number of ISR event messages"34 AMBIQ maximum number of ISR event messages.
28 int "Renesas RA family UDC driver maximum number of ISR event messages"32 Maximum number of messages for handling of Renesas RA USBD ISR events.
25 Size of the stack used in the driver for IT82xx2 USBD ISR event
5 bool "$(module-str) guarantee non ISR callbacks upon stepper events"9 code is not run inside of an ISR. Can be disabled, but10 then registered stepper event callback must be ISR safe.
6 An :dfn:`interrupt service routine` (ISR) is a function that executes8 An ISR normally preempts the execution of the current thread,10 Thread execution resumes only once all ISR work has been completed.22 An ISR has the following key properties:24 * An **interrupt request (IRQ) signal** that triggers the ISR.30 to associate a given interrupt source with a given ISR.31 Only a single ISR can be associated with a specific IRQ at any given time.36 (usually of the same type). The argument value passed to an ISR's function39 The kernel provides a default ISR for all unused IDT entries. This ISR42 The kernel supports **interrupt nesting**. This allows an ISR to be preempted[all …]
21 - Called from an ISR (interrupted a task)22 - Called from an ISR (interrupted a thread)27 - Called from an ISR that interrupted a task28 - Called from an ISR that interrupted a thread48 - Used when triggering an ISR to perform ISR context work.87 Testing k_current_get() from an ISR and task88 Testing k_is_in_isr() from an ISR
36 int "ISR-mode random number pool size"41 hardware to make them ready for ISR consumers.45 int "ISR-mode random number pool low-water threshold"49 ISR consumers. As soon as the number of available bytes in the
53 int "ISR-mode random number pool size"58 hardware to make them ready for ISR consumers.62 int "ISR-mode random number pool low-water threshold"66 ISR consumers. As soon as the number of available bytes in the
39 int "ISR-mode random number pool size"44 hardware to make them ready for ISR consumers.48 int "ISR-mode random number pool low-water threshold"52 ISR consumers. As soon as the number of available bytes in the
8 bool "Use ISR safe PM for the test"
31 return ((PFIC->ISR[irq >> 5] & (1 << (irq & 0x1F))) != 0); in arch_irq_is_enabled()
10 Enables the esp32c3 interrupt controller driver to handle ISR
1 /* Keep default IRQ priority low for peripherals to reduce Radio ISR latency.
3 If a thread causes a CPU exception, and it is not in an ISR or "essential"
93 bool "Re-enable interrupts by toggling IER at end of ISR"97 an interruptible event occurs during ISR and the host interrupt103 the IER is being toggled to re-assert interrupts at the end of ISR104 to nudge the host interrupt controller to fire the ISR again.
35 bool "Shell command to dump the ISR tables"39 This option enables a shell command to dump the ISR tables.
37 processor, but rather generate an interrupt with ISR implemented under42 Using SEGGER-provided ISR63 Using other custom ISR
30 so they are typically smaller than the ISR stacks.67 int "Size of ISR substacks"70 Number of bytes from the ISR stack to reserve for each nested IRQ
174 bool "Read ACPI EC Event Data in IBF ISR"177 Enable reading event data in ACPI EC IBF ISR. This is used in OS178 environment where application expects IBF ISR to read data and pass188 Enable espi_evt_data_kbc format for encoding event in KBC IBF ISR193 Enable KBC OBE callback from OBE ISR
25 # HCI RX buffers are received in ISR context. RX messages
11 synchronously with the end of a hardware ISR. It implements a15 via a queue from the device ISR (really just a timer interrupt).24 * The cycle time between message creation in the ISR and receipt by27 * The time between ISR and receipt by the worker thread.47 thread always runs immediately after the ISR. It shows reliable,
29 Some platforms receive the HCI RX buffers in ISR context.30 If enabled, the HCI RX message is queued by the ISR, and the message is processed
227 WRITE_BIT(base->ISR, pin, mode != GPIO_INT_MODE_DISABLED); in imx_gpio_pin_interrupt_configure()249 int_status = config->base->ISR & config->base->IMR; in imx_gpio_port_isr()251 config->base->ISR = int_status; in imx_gpio_port_isr()
