1# Copyright 2023-2025 NXP 2# SPDX-License-Identifier: Apache-2.0 3 4if SOC_SERIES_MCXW 5 6config NUM_IRQS 7 default 77 if SOC_MCXW727C 8 default 75 9 10config SYS_CLOCK_HW_CYCLES_PER_SEC 11 default 96000000 if CORTEX_M_SYSTICK 12 13config MCUX_FLASH_K4_API 14 default y 15 16if BT 17 18config MAIN_STACK_SIZE 19 default 2560 20 21config BT_LONG_WQ_STACK_SIZE 22 default 2560 23 24config SYSTEM_WORKQUEUE_STACK_SIZE 25 default 2048 26 27if SHELL 28 29config SHELL_STACK_SIZE 30 default 4096 31 32endif # SHELL 33 34# Include intercore messaging component 35config NXP_RF_IMU 36 default y 37 38# Set the controller's public identity using NXP vendor command 39config BT_HCI_SET_PUBLIC_ADDR 40 default y 41 42# HCI RX buffers are received in ISR context. RX messages 43# need to be queued and processed by a dedicated thread 44config HCI_NXP_RX_THREAD 45 default y 46 47endif # BT 48 49if NET_L2_IEEE802154 || NET_L2_OPENTHREAD 50 51# Include intercore messaging component 52config NXP_RF_IMU 53 default y 54 55endif # NET_L2_IEEE802154 || NET_L2_OPENTHREAD 56 57 58endif # SOC_SERIES_MCXW 59
