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Searched refs:COMP_CSR_COMP2INSEL_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h1165 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
1166 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
1168 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
1169 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
1170 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Dstm32f051x8.h1166 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
1167 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
1169 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
1170 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
1171 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Dstm32f071xb.h1200 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
1201 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
1203 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
1204 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
1205 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Dstm32f072xb.h4959 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
4960 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
4962 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
4963 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
4964 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Dstm32f091xc.h4941 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
4942 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
4944 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
4945 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
4946 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Dstm32f098xx.h4941 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
4942 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
4944 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
4945 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
4946 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Dstm32f078xx.h4959 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
4960 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
4962 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
4963 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
4964 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f378xx.h1398 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
1399 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
1401 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
1402 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
1403 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
Dstm32f373xc.h1439 #define COMP_CSR_COMP2INSEL_Pos (20U) macro
1440 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
1442 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
1443 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
1444 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */