/hal_stm32-latest/stm32cube/stm32c0xx/soc/ |
D | stm32c011xx.h | 947 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 976 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32c031xx.h | 951 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 980 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32c071xx.h | 1028 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1057 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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/hal_stm32-latest/stm32cube/stm32g0xx/soc/ |
D | stm32g030xx.h | 992 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1021 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g050xx.h | 1011 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1040 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g070xx.h | 1014 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1043 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g031xx.h | 1035 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1064 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g041xx.h | 1082 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1111 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g051xx.h | 1098 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1127 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g061xx.h | 1145 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1174 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g071xx.h | 1147 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1176 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g081xx.h | 1194 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1223 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g0b0xx.h | 1096 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1125 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g0c1xx.h | 1361 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1390 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32g0b1xx.h | 1314 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1343 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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/hal_stm32-latest/stm32cube/stm32wlxx/soc/ |
D | stm32wle4xx.h | 1321 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1350 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32wle5xx.h | 1321 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1350 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32wl5mxx.h | 1503 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1532 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32wl54xx.h | 1503 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1532 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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D | stm32wl55xx.h | 1503 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro 1532 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 1440 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro
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D | stm32wba52xx.h | 1921 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro
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/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 1237 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro
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D | stm32u083xx.h | 1390 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro
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D | stm32u073xx.h | 1354 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ macro
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