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Searched refs:C1 (Results 1 – 25 of 78) sorted by relevance

1234

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.c71 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
558 if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
635 …if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCL… in CLOCK_SetInternalRefClkConfig()
648 MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; in CLOCK_SetInternalRefClkConfig()
1093 MCG->C1 = in CLOCK_SetFeiMode()
1094 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* … in CLOCK_SetFeiMode()
1153 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1236 MCG->C1 = in CLOCK_SetFbiMode()
1237 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* … in CLOCK_SetFbiMode()
1305 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
[all …]
Dsystem_MKL25Z4.c137 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
141 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
145 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
153 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
157 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
199 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
207 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.c71 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
582 if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
688 …if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCL… in CLOCK_SetInternalRefClkConfig()
701 MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; in CLOCK_SetInternalRefClkConfig()
1176 MCG->C1 = in CLOCK_SetFeiMode()
1177 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* … in CLOCK_SetFeiMode()
1236 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1320 MCG->C1 = in CLOCK_SetFbiMode()
1321 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* … in CLOCK_SetFbiMode()
1389 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.c71 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
582 if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
688 …if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCL… in CLOCK_SetInternalRefClkConfig()
701 MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; in CLOCK_SetInternalRefClkConfig()
1176 MCG->C1 = in CLOCK_SetFeiMode()
1177 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* … in CLOCK_SetFeiMode()
1236 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1320 MCG->C1 = in CLOCK_SetFbiMode()
1321 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* … in CLOCK_SetFbiMode()
1389 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c53 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
649 if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
787 …if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) … in CLOCK_SetInternalRefClkConfig()
802 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMod… in CLOCK_SetInternalRefClkConfig()
1412 MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | in CLOCK_SetFeiMode()
1488 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1588 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbiMode()
1673 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
1795 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutS… in CLOCK_SetPbeMode()
1848 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); in CLOCK_SetPeeMode()
[all …]
Dsystem_MKV58F24.c114 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { in SystemCoreClockUpdate()
118 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0U) { in SystemCoreClockUpdate()
122 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
130 Divider = (uint16_t)(32U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 Divider = (uint16_t)(1U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
177 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { in SystemCoreClockUpdate()
184 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c53 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
649 if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
787 …if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) … in CLOCK_SetInternalRefClkConfig()
802 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMod… in CLOCK_SetInternalRefClkConfig()
1412 MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | in CLOCK_SetFeiMode()
1488 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1588 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbiMode()
1673 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
1795 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutS… in CLOCK_SetPbeMode()
1848 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); in CLOCK_SetPeeMode()
[all …]
Dsystem_MKV56F24.c114 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { in SystemCoreClockUpdate()
118 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0U) { in SystemCoreClockUpdate()
122 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
130 Divider = (uint16_t)(32U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 Divider = (uint16_t)(1U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
177 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { in SystemCoreClockUpdate()
184 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c99 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
534 if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
617 …if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCL… in CLOCK_SetInternalRefClkConfig()
630 MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; in CLOCK_SetInternalRefClkConfig()
925 MCG->C1 = in CLOCK_SetFeiMode()
926 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* … in CLOCK_SetFeiMode()
985 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1069 MCG->C1 = in CLOCK_SetFbiMode()
1070 …((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* … in CLOCK_SetFbiMode()
1133 MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
[all …]
Dsystem_MKW41Z4.c102 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
104 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
112 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
120 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
124 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
159 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
167 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.c53 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
728 if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
894 …if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) … in CLOCK_SetInternalRefClkConfig()
909 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMod… in CLOCK_SetInternalRefClkConfig()
1554 MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | in CLOCK_SetFeiMode()
1630 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1731 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbiMode()
1816 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
1939 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutS… in CLOCK_SetPbeMode()
1992 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); in CLOCK_SetPeeMode()
[all …]
Dsystem_MK22F51212.c128 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
132 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
148 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
156 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
160 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
203 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
211 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.c53 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
695 if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
861 …if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) … in CLOCK_SetInternalRefClkConfig()
876 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMod… in CLOCK_SetInternalRefClkConfig()
1521 MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | in CLOCK_SetFeiMode()
1597 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1698 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbiMode()
1783 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
1906 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutS… in CLOCK_SetPbeMode()
1959 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); in CLOCK_SetPeeMode()
[all …]
Dsystem_MK64F12.c132 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
136 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
152 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
160 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
164 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
207 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
215 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c53 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
734 if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
901 …if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) … in CLOCK_SetInternalRefClkConfig()
916 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMod… in CLOCK_SetInternalRefClkConfig()
1563 MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | in CLOCK_SetFeiMode()
1639 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1740 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbiMode()
1825 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
1948 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutS… in CLOCK_SetPbeMode()
2001 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); in CLOCK_SetPeeMode()
[all …]
Dsystem_MK80F25615.c107 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
111 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
127 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
135 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
139 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
183 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
191 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c53 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
734 if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
901 …if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) … in CLOCK_SetInternalRefClkConfig()
916 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMod… in CLOCK_SetInternalRefClkConfig()
1563 MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | in CLOCK_SetFeiMode()
1639 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
1740 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbiMode()
1825 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
1948 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutS… in CLOCK_SetPbeMode()
2001 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); in CLOCK_SetPeeMode()
[all …]
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_i2c.c221 base->C1 &= ~(uint8_t)I2C_C1_TXAK_MASK; in I2C_MasterAckByte()
448 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); in I2C_MasterTransferRunStateMachine()
456 base->C1 |= I2C_C1_TXAK_MASK; in I2C_MasterTransferRunStateMachine()
482 base->C1 |= I2C_C1_TX_MASK; in I2C_MasterTransferRunStateMachine()
500 base->C1 |= I2C_C1_TXAK_MASK; in I2C_MasterTransferRunStateMachine()
521 uint8_t tmpC1 = base->C1; in I2C_TransferCommonIRQHandler()
578 base->C1 = 0; in I2C_MasterInit()
589 base->C1 &= ~(uint8_t)(I2C_C1_IICEN_MASK); in I2C_MasterInit()
614 base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); in I2C_MasterInit()
697 base->C1 |= I2C_C1_IICIE_MASK; in I2C_EnableInterrupts()
[all …]
Dfsl_spi.c287 if (base->C1 & SPI_C1_MSTR_MASK) in SPI_SendTransfer()
418 base->C1 &= ~SPI_C1_SPE_MASK; in SPI_MasterInit()
421 base->C1 = SPI_C1_MSTR(1U) | SPI_C1_CPOL(config->polarity) | SPI_C1_CPHA(config->phase) | in SPI_MasterInit()
449 base->C1 |= SPI_C1_SPE_MASK; in SPI_MasterInit()
481 base->C1 &= ~SPI_C1_SPE_MASK; in SPI_SlaveInit()
484 base->C1 = in SPI_SlaveInit()
506 base->C1 |= SPI_C1_SPE_MASK; in SPI_SlaveInit()
513 base->C1 &= ~SPI_C1_SPE_MASK; in SPI_Deinit()
542 base->C1 |= SPI_C1_SPIE_MASK; in SPI_EnableInterrupts()
548 base->C1 |= SPI_C1_SPTIE_MASK; in SPI_EnableInterrupts()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c53 #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
709 assert(MCG->C1 & MCG_C1_IRCLKEN_MASK); in CLOCK_EnableUsbhs0PhyPllClock()
925 if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) in CLOCK_GetInternalRefClkFreq()
1119 …if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) … in CLOCK_SetInternalRefClkConfig()
1134 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMod… in CLOCK_SetInternalRefClkConfig()
1831 MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | in CLOCK_SetFeiMode()
1907 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFeeMode()
2008 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbiMode()
2093 MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | in CLOCK_SetFbeMode()
2220 …MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutS… in CLOCK_SetPbeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c151 …MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider… in SystemInit()
173 …MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider… in SystemInit()
218 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
220 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
228 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
236 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
240 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
275 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
283 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c151 …MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider… in SystemInit()
173 …MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider… in SystemInit()
218 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
220 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
228 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
236 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
240 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
275 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
283 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c151 …MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider… in SystemInit()
173 …MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider… in SystemInit()
218 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
220 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
228 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
236 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
240 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
275 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
283 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
Dsystem_MKW21Z4.c101 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
103 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
111 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
119 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
123 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
158 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
166 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
Dsystem_MKW31Z4.c102 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { in SystemCoreClockUpdate()
104 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { in SystemCoreClockUpdate()
112 switch (MCG->C1 & MCG_C1_FRDIV_MASK) { in SystemCoreClockUpdate()
120 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
124 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
159 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { in SystemCoreClockUpdate()
167 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { in SystemCoreClockUpdate()

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