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Searched refs:resets (Results 26 – 50 of 174) sorted by relevance

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/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2350.dtsi274 resets = <&reset RPI_PICO_RESETS_RESET_UART0>;
284 resets = <&reset RPI_PICO_RESETS_RESET_UART1>;
296 resets = <&reset RPI_PICO_RESETS_RESET_SPI0>;
307 resets = <&reset RPI_PICO_RESETS_RESET_SPI1>;
319 resets = <&reset RPI_PICO_RESETS_RESET_I2C0>;
331 resets = <&reset RPI_PICO_RESETS_RESET_I2C1>;
341 resets = <&reset RPI_PICO_RESETS_RESET_ADC>;
352 resets = <&reset RPI_PICO_RESETS_RESET_PWM>;
365 resets = <&reset RPI_PICO_RESETS_RESET_TIMER0>;
381 resets = <&reset RPI_PICO_RESETS_RESET_TIMER1>;
[all …]
Drp2040.dtsi268 resets = <&reset RPI_PICO_RESETS_RESET_UART0>;
278 resets = <&reset RPI_PICO_RESETS_RESET_UART1>;
290 resets = <&reset RPI_PICO_RESETS_RESET_SPI0>;
301 resets = <&reset RPI_PICO_RESETS_RESET_SPI1>;
311 resets = <&reset RPI_PICO_RESETS_RESET_ADC>;
324 resets = <&reset RPI_PICO_RESETS_RESET_I2C0>;
336 resets = <&reset RPI_PICO_RESETS_RESET_I2C1>;
353 resets = <&reset RPI_PICO_RESETS_RESET_USBCTRL>;
364 resets = <&reset RPI_PICO_RESETS_RESET_PWM>;
375 resets = <&reset RPI_PICO_RESETS_RESET_TIMER>;
[all …]
/Zephyr-latest/dts/arm/st/wb0/
Dstm32wb05.dtsi17 resets = <&rctl STM32_RESET(APB0, 0)>;
39 resets = <&rctl STM32_RESET(APB0, 1)>;
61 resets = <&rctl STM32_RESET(APB0, 2)>;
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc54xxx.dtsi164 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
173 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
182 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
191 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
200 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
209 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
218 resets = <&reset NXP_SYSCON_RESET(1, 17)>;
227 resets = <&reset NXP_SYSCON_RESET(1, 18)>;
Dnxp_lpc55S1x_common.dtsi227 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
236 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
245 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
254 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
263 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
272 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
281 resets = <&reset NXP_SYSCON_RESET(1, 17)>;
290 resets = <&reset NXP_SYSCON_RESET(1, 18)>;
300 resets = <&reset NXP_SYSCON_RESET(1, 7)>;
310 resets = <&reset NXP_SYSCON_RESET(2, 28)>;
Dnxp_lpc55S2x_common.dtsi192 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
201 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
210 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
219 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
228 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
237 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
246 resets = <&reset NXP_SYSCON_RESET(1, 17)>;
255 resets = <&reset NXP_SYSCON_RESET(1, 18)>;
280 resets = <&reset NXP_SYSCON_RESET(2, 28)>;
Dnxp_rt5xx_common.dtsi240 resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
249 resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
258 resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
267 resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
276 resets = <&rstctl1 NXP_SYSCON_RESET(0, 12)>;
285 resets = <&rstctl1 NXP_SYSCON_RESET(0, 13)>;
294 resets = <&rstctl1 NXP_SYSCON_RESET(0, 14)>;
303 resets = <&rstctl1 NXP_SYSCON_RESET(0, 15)>;
312 resets = <&rstctl1 NXP_SYSCON_RESET(0, 23)>;
321 resets = <&rstctl1 NXP_SYSCON_RESET(0, 16)>;
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f405.dtsi50 resets = <&rctl STM32_RESET(APB1, 18U)>;
59 resets = <&rctl STM32_RESET(APB1, 19U)>;
68 resets = <&rctl STM32_RESET(APB1, 20U)>;
77 resets = <&rctl STM32_RESET(APB1, 4U)>;
93 resets = <&rctl STM32_RESET(APB1, 5U)>;
109 resets = <&rctl STM32_RESET(APB2, 1U)>;
132 resets = <&rctl STM32_RESET(APB1, 6U)>;
154 resets = <&rctl STM32_RESET(APB1, 7U)>;
176 resets = <&rctl STM32_RESET(APB1, 8U)>;
Dstm32f412.dtsi55 resets = <&rctl STM32_RESET(APB1, 18U)>;
97 resets = <&rctl STM32_RESET(APB1, 5U)>;
113 resets = <&rctl STM32_RESET(APB2, 1U)>;
136 resets = <&rctl STM32_RESET(APB1, 6U)>;
158 resets = <&rctl STM32_RESET(APB1, 7U)>;
180 resets = <&rctl STM32_RESET(APB1, 8U)>;
/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xc.dtsi30 resets = <&rctl STM32_RESET(APB1, 19U)>;
39 resets = <&rctl STM32_RESET(APB1, 20U)>;
48 resets = <&rctl STM32_RESET(APB1, 3U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
76 resets = <&rctl STM32_RESET(APB1, 5U)>;
144 resets = <&rctl STM32_RESET(APB2, 13U)>;
Dstm32f105.dtsi68 resets = <&rctl STM32_RESET(APB1, 19U)>;
77 resets = <&rctl STM32_RESET(APB1, 20U)>;
106 resets = <&rctl STM32_RESET(APB1, 3U)>;
123 resets = <&rctl STM32_RESET(APB1, 4U)>;
134 resets = <&rctl STM32_RESET(APB1, 5U)>;
/Zephyr-latest/dts/arm/st/g0/
Dstm32g051.dtsi17 resets = <&rctl STM32_RESET(APB1L, 4U)>;
32 resets = <&rctl STM32_RESET(APB1L, 5U)>;
48 resets = <&rctl STM32_RESET(APB1H, 16U)>;
Dstm32g031.dtsi18 resets = <&rctl STM32_RESET(APB1L, 20U)>;
27 resets = <&rctl STM32_RESET(APB1L, 0U)>;
Dstm32g050.dtsi17 resets = <&rctl STM32_RESET(APB1L, 4U)>;
28 resets = <&rctl STM32_RESET(APB1L, 5U)>;
/Zephyr-latest/dts/arm/st/f0/
Dstm32f070Xb.dtsi32 resets = <&rctl STM32_RESET(APB1, 18U)>;
41 resets = <&rctl STM32_RESET(APB1, 19U)>;
72 resets = <&rctl STM32_RESET(APB1, 4U)>;
83 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f071.dtsi48 resets = <&rctl STM32_RESET(APB1, 18U)>;
57 resets = <&rctl STM32_RESET(APB1, 19U)>;
66 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f030X8.dtsi25 resets = <&rctl STM32_RESET(APB1, 17U)>;
56 resets = <&rctl STM32_RESET(APB1, 4U)>;
67 resets = <&rctl STM32_RESET(APB2, 16U)>;
Dstm32f051.dtsi17 resets = <&rctl STM32_RESET(APB1, 17U)>;
48 resets = <&rctl STM32_RESET(APB1, 4U)>;
59 resets = <&rctl STM32_RESET(APB2, 16U)>;
/Zephyr-latest/dts/arm/st/f3/
Dstm32f373.dtsi72 resets = <&rctl STM32_RESET(APB1, 2U)>;
89 resets = <&rctl STM32_RESET(APB1, 3U)>;
106 resets = <&rctl STM32_RESET(APB1, 6U)>;
123 resets = <&rctl STM32_RESET(APB1, 7U)>;
140 resets = <&rctl STM32_RESET(APB1, 8U)>;
157 resets = <&rctl STM32_RESET(APB1, 9U)>;
174 resets = <&rctl STM32_RESET(APB2, 19U)>;
Dstm32f303.dtsi59 resets = <&rctl STM32_RESET(APB1, 20U)>;
79 resets = <&rctl STM32_RESET(APB2, 11U)>;
96 resets = <&rctl STM32_RESET(APB1, 2U)>;
113 resets = <&rctl STM32_RESET(APB2, 13U)>;
130 resets = <&rctl STM32_RESET(APB2, 20U)>;
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi235 resets = <&rctl STM32_RESET(APB2, 4U)>;
244 resets = <&rctl STM32_RESET(APB1, 17U)>;
253 resets = <&rctl STM32_RESET(APB1, 18U)>;
262 resets = <&rctl STM32_RESET(APB2, 5U)>;
271 resets = <&rctl STM32_RESET(APB1, 19U)>;
280 resets = <&rctl STM32_RESET(APB1, 20U)>;
413 resets = <&rctl STM32_RESET(APB2, 0U)>;
430 resets = <&rctl STM32_RESET(APB1, 0U)>;
447 resets = <&rctl STM32_RESET(APB1, 1U)>;
469 resets = <&rctl STM32_RESET(APB1, 2U)>;
[all …]
/Zephyr-latest/dts/arm/st/u0/
Dstm32u0.dtsi195 resets = <&rctl STM32_RESET(APB1H, 14U)>;
204 resets = <&rctl STM32_RESET(APB1L, 17U)>;
213 resets = <&rctl STM32_RESET(APB1L, 18U)>;
222 resets = <&rctl STM32_RESET(APB1L, 19U)>;
231 resets = <&rctl STM32_RESET(APB1L, 20U)>;
240 resets = <&rctl STM32_RESET(APB1L, 7U)>;
384 resets = <&rctl STM32_RESET(AHB1, 16U)>;
405 resets = <&rctl STM32_RESET(APB1H, 11U)>;
427 resets = <&rctl STM32_RESET(APB1L, 0U)>;
449 resets = <&rctl STM32_RESET(APB1L, 1U)>;
[all …]
/Zephyr-latest/dts/arm/st/l0/
Dstm32l051.dtsi39 resets = <&rctl STM32_RESET(APB2, 14U)>;
48 resets = <&rctl STM32_RESET(APB2, 5U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4p5.dtsi101 resets = <&rctl STM32_RESET(APB1L, 18U)>;
110 resets = <&rctl STM32_RESET(APB1L, 19U)>;
119 resets = <&rctl STM32_RESET(APB1L, 20U)>;
172 resets = <&rctl STM32_RESET(APB1L, 1U)>;
194 resets = <&rctl STM32_RESET(APB1L, 2U)>;
216 resets = <&rctl STM32_RESET(APB1L, 3U)>;
238 resets = <&rctl STM32_RESET(APB1L, 5U)>;
260 resets = <&rctl STM32_RESET(APB2, 13U)>;
277 resets = <&rctl STM32_RESET(APB2, 18U)>;
343 resets = <&rctl STM32_RESET(AHB2, 22U)>;
[all …]
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi258 resets = <&rctl STM32_RESET(APB2, 4U)>;
267 resets = <&rctl STM32_RESET(APB1, 17U)>;
276 resets = <&rctl STM32_RESET(APB1, 18U)>;
285 resets = <&rctl STM32_RESET(APB1, 19U)>;
294 resets = <&rctl STM32_RESET(APB1, 20U)>;
303 resets = <&rctl STM32_RESET(APB2, 5U)>;
312 resets = <&rctl STM32_RESET(APB1, 30U)>;
321 resets = <&rctl STM32_RESET(APB1, 31U)>;
425 resets = <&rctl STM32_RESET(APB2, 0U)>;
442 resets = <&rctl STM32_RESET(APB1, 0U)>;
[all …]

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