| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32wbax.c | 110 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in write_qword() local
117 if (regs->NSCR & FLASH_STM32_NSLOCK) { in write_qword()
136 regs->NSCR |= FLASH_STM32_NSPG; in write_qword()
139 tmp = regs->NSCR; in write_qword()
151 regs->NSCR &= (~FLASH_STM32_NSPG); in write_qword()
158 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in erase_page() local
164 if (regs->NSCR & FLASH_STM32_NSLOCK) { in erase_page()
179 regs->NSCR |= FLASH_STM32_NSPER; in erase_page()
180 regs->NSCR &= ~FLASH_STM32_NSPNB_MSK; in erase_page()
181 regs->NSCR |= (page << FLASH_STM32_NSPNB_POS); in erase_page()
[all …]
|
| D | flash_stm32l5x.c | 162 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in write_nwords() local
171 if (regs->NSCR & FLASH_STM32_NSLOCK) { in write_nwords()
205 regs->NSCR |= FLASH_STM32_NSPG; in write_nwords()
208 tmp = regs->NSCR; in write_nwords()
219 regs->NSCR &= (~FLASH_STM32_NSPG); in write_nwords()
226 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in erase_page() local
232 if (regs->NSCR & FLASH_STM32_NSLOCK) { in erase_page()
247 ((regs->OPTR & FLASH_OPTR_SWAP_BANK) == FLASH_OPTR_SWAP_BANK); in erase_page()
251 regs->NSCR &= ~FLASH_STM32_NSBKER_MSK; in erase_page()
256 regs->NSCR &= ~FLASH_STM32_NSBKER_MSK; in erase_page()
[all …]
|
| D | flash_sam.c | 33 Efc *regs; member
80 Efc *regs = config->regs; in sam_flash_mask_ready_interrupt() local
82 regs->EEFC_FMR &= ~EEFC_FMR_FRDY; in sam_flash_mask_ready_interrupt()
87 Efc *regs = config->regs; in sam_flash_unmask_ready_interrupt() local
89 regs->EEFC_FMR |= EEFC_FMR_FRDY; in sam_flash_unmask_ready_interrupt()
105 Efc *regs = config->regs; in sam_flash_section_wait_until_ready() local
117 eefc_fsr = regs->EEFC_FSR; in sam_flash_section_wait_until_ready()
232 Efc *regs = sam_config->regs; in sam_flash_write_latch_buffer_to_page() local
235 regs->EEFC_FCR = EEFC_FCR_FCMD_WP | EEFC_FCR_FARG(page) | EEFC_FCR_FKEY_PASSWD; in sam_flash_write_latch_buffer_to_page()
301 Efc *regs = sam_config->regs; in sam_flash_unlock_write_page() local
[all …]
|
| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_riscv_gcc.h | 48 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
117 : "r"(regs), "r"(RV_FPREG_WIDTH) in _load_all_float_registers()
133 static inline void _store_all_float_registers(struct fp_register_set *regs) in _store_all_float_registers() argument
202 : "r"(regs), "r"(RV_FPREG_WIDTH) in _store_all_float_registers()
221 *regs) in _load_then_store_all_float_registers()
223 _load_all_float_registers(regs); in _load_then_store_all_float_registers()
224 _store_all_float_registers(regs); in _load_then_store_all_float_registers()
|
| /Zephyr-latest/drivers/rtc/ |
| D | rtc_am1805.c | 119 uint8_t regs[7]; in am1805_set_time() local
138 regs[0] = bin2bcd(tm->tm_sec) & SECONDS_BITS; in am1805_set_time()
139 regs[1] = bin2bcd(tm->tm_min) & MINUTES_BITS; in am1805_set_time()
140 regs[2] = bin2bcd(tm->tm_hour) & HOURS_BITS; in am1805_set_time()
141 regs[3] = bin2bcd(tm->tm_mday) & DATE_BITS; in am1805_set_time()
142 regs[4] = bin2bcd(tm->tm_mon) & MONTHS_BITS; in am1805_set_time()
143 regs[5] = bin2bcd(tm->tm_year) & YEAR_BITS; in am1805_set_time()
144 regs[6] = bin2bcd(tm->tm_wday) & WEEKDAY_BITS; in am1805_set_time()
146 err = i2c_burst_write_dt(&config->int_i2c, REG_SECONDS_ADDR, regs, sizeof(regs)); in am1805_set_time()
165 uint8_t regs[7]; in am1805_get_time() local
[all …]
|
| D | rtc_rv8263.c | 204 uint8_t regs[8]; in rv8263c8_time_set() local
217 regs[0] = RV8263C8_REGISTER_SECONDS; in rv8263c8_time_set()
218 regs[1] = bin2bcd(timeptr->tm_sec) & SECONDS_BITS; in rv8263c8_time_set()
219 regs[2] = bin2bcd(timeptr->tm_min) & MINUTES_BITS; in rv8263c8_time_set()
220 regs[3] = bin2bcd(timeptr->tm_hour) & HOURS_BITS; in rv8263c8_time_set()
221 regs[4] = bin2bcd(timeptr->tm_mday) & DATE_BITS; in rv8263c8_time_set()
222 regs[5] = bin2bcd(timeptr->tm_wday) & WEEKDAY_BITS; in rv8263c8_time_set()
223 regs[6] = (bin2bcd(timeptr->tm_mon) & MONTHS_BITS) + 1; in rv8263c8_time_set()
224 regs[7] = bin2bcd(timeptr->tm_year - RV8263_YEAR_OFFSET) & YEAR_BITS; in rv8263c8_time_set()
226 return i2c_write_dt(&config->i2c_bus, regs, sizeof(regs)); in rv8263c8_time_set()
[all …]
|
| D | rtc_pcf8563.c | 225 uint8_t regs[4]; in pcf8563_alarm_set_time() local
248 regs[0] = bin2bcd(timeptr->tm_min) & PCF8563_MINUTES_MASK; in pcf8563_alarm_set_time()
251 regs[0] = BIT(7); in pcf8563_alarm_set_time()
255 regs[1] = bin2bcd(timeptr->tm_hour) & PCF8563_HOURS_MASK; in pcf8563_alarm_set_time()
257 regs[1] = BIT(7); in pcf8563_alarm_set_time()
261 regs[2] = bin2bcd(timeptr->tm_mday) & PCF8563_DAYS_MASK; in pcf8563_alarm_set_time()
263 regs[2] = BIT(7); in pcf8563_alarm_set_time()
267 regs[3] = bin2bcd(timeptr->tm_wday) & PCF8563_WEEKDAYS_MASK; in pcf8563_alarm_set_time()
269 regs[3] = BIT(7); in pcf8563_alarm_set_time()
272 ret = i2c_burst_write_dt(&config->i2c, PCF8563_ALARM_REGISTER, regs, sizeof(regs)); in pcf8563_alarm_set_time()
[all …]
|
| /Zephyr-latest/drivers/i2c/ |
| D | i2c_smartbond.c | 25 I2C_Type *regs; member
93 return ((config->regs->I2C_STATUS_REG & mask) == I2C_I2C_STATUS_REG_TFE_Msk); in i2c_smartbond_is_idle()
100 if ((config->regs->I2C_ENABLE_REG & I2C_I2C_ENABLE_REG_I2C_EN_Msk)) { in i2c_smartbond_disable_when_inactive()
103 config->regs->I2C_ENABLE_REG &= ~I2C_I2C_ENABLE_REG_I2C_EN_Msk; in i2c_smartbond_disable_when_inactive()
148 config->regs->I2C_CON_REG = con_reg; in i2c_smartbond_apply_configure()
151 config->regs->I2C_INTR_MASK_REG = 0x0000U; in i2c_smartbond_apply_configure()
153 config->regs->I2C_ENABLE_REG |= I2C_I2C_ENABLE_REG_I2C_EN_Msk; in i2c_smartbond_apply_configure()
180 reg = config->regs->I2C_CON_REG; in i2c_smartbond_get_config()
221 config->regs->I2C_ENABLE_REG &= ~I2C_I2C_ENABLE_REG_I2C_EN_Msk; in i2c_smartbond_set_target_address()
224 config->regs->I2C_CON_REG |= I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk; in i2c_smartbond_set_target_address()
[all …]
|
| /Zephyr-latest/drivers/timer/ |
| D | leon_gptimer.c | 70 volatile struct gptimer_regs *regs = get_regs(); in timer_isr() local
71 volatile struct gptimer_timer_regs *tmr = ®s->timer[0]; in timer_isr()
93 volatile struct gptimer_regs *regs = get_regs(); in sys_clock_cycle_get_32() local
94 volatile struct gptimer_timer_regs *tmr = ®s->timer[1]; in sys_clock_cycle_get_32()
109 volatile struct gptimer_regs *regs = get_regs(); in sys_clock_driver_init() local
110 volatile struct gptimer_timer_regs *tmr = ®s->timer[0]; in sys_clock_driver_init()
112 init_downcounter(®s->timer[1]); in sys_clock_driver_init()
122 regs->scaler_reload = PRESCALER - 1; in sys_clock_driver_init()
|
| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_mchp_xec.c | 24 static void config_drive_slew(struct gpio_regs * const regs, uint32_t idx, uint32_t conf) in config_drive_slew() argument
48 regs->CTRL2[idx] = (regs->CTRL2[idx] & ~msk) | (val & msk); in config_drive_slew()
93 struct gpio_regs * const regs = (struct gpio_regs * const)DT_INST_REG_ADDR(0); in xec_config_pin() local
105 config_drive_slew(regs, idx, conf); in xec_config_pin()
108 regs->CTRL[idx] &= ~(BIT(MCHP_GPIO_CTRL_AOD_POS) | BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)); in xec_config_pin()
109 pcr1 = regs->CTRL[idx]; /* current configuration including pin input state */ in xec_config_pin()
110 pcr1 = regs->CTRL[idx]; /* read multiple times to allow propagation from pad */ in xec_config_pin()
111 pcr1 = regs->CTRL[idx]; /* Is this necessary? */ in xec_config_pin()
159 regs->CTRL[idx] = pcr1; in xec_config_pin()
161 regs->CTRL[idx] = pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS); in xec_config_pin()
|
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_max32.c | 21 mxc_gpio_regs_t *regs; member
36 *value = MXC_GPIO_InGet(cfg->regs, (unsigned int)-1); in api_port_get_raw()
45 MXC_GPIO_OutPut(cfg->regs, mask, value); in api_port_set_masked_raw()
53 MXC_GPIO_OutSet(cfg->regs, pins); in api_port_set_bits_raw()
61 MXC_GPIO_OutClr(cfg->regs, pins); in api_port_clear_bits_raw()
69 MXC_GPIO_OutToggle(cfg->regs, pins); in api_port_toggle_bits()
84 gpio_cfg.port = cfg->regs; in api_pin_configure()
136 MXC_GPIO_OutClr(cfg->regs, BIT(pin)); in api_pin_configure()
138 MXC_GPIO_OutSet(cfg->regs, BIT(pin)); in api_pin_configure()
151 gpio_cfg.port = cfg->regs; in api_pin_interrupt_configure()
[all …]
|
| /Zephyr-latest/drivers/pwm/ |
| D | pwm_mchp_xec.c | 54 struct pwm_regs * const regs; member
247 struct pwm_regs * const regs = cfg->regs; in xec_compute_and_set_parameters() local
297 regs->CONFIG &= ~MCHP_PWM_CFG_ENABLE; in xec_compute_and_set_parameters()
299 cfgval = regs->CONFIG; in xec_compute_and_set_parameters()
308 regs->COUNT_ON = params->on; in xec_compute_and_set_parameters()
309 regs->COUNT_OFF = params->off; in xec_compute_and_set_parameters()
314 regs->CONFIG = cfgval; in xec_compute_and_set_parameters()
322 struct pwm_regs * const regs = cfg->regs; in pwm_xec_set_cycles() local
331 regs->CONFIG |= MCHP_PWM_CFG_ON_POL_LO; in pwm_xec_set_cycles()
344 regs->CONFIG &= ~MCHP_PWM_CFG_ENABLE; in pwm_xec_set_cycles()
[all …]
|
| D | pwm_max32.c | 23 mxc_tmr_regs_t *regs; member
40 mxc_tmr_regs_t *regs = cfg->regs; in api_set_cycles() local
68 MXC_TMR_Shutdown(regs); in api_set_cycles()
76 ret = Wrap_MXC_TMR_Init(regs, &pwm_cfg); in api_set_cycles()
81 ret = MXC_TMR_SetPWM(regs, pulse_cycles); in api_set_cycles()
86 MXC_TMR_Start(regs); in api_set_cycles()
130 .regs = (mxc_tmr_regs_t *)DT_REG_ADDR(DT_INST_PARENT(_num)), \
|
| /Zephyr-latest/drivers/serial/ |
| D | uart_smartbond.c | 75 UART2_Type *regs; member
165 if ((config->regs->UART2_USR_REG & UART2_UART2_USR_REG_UART_RFNE_Msk) == 0) { in uart_smartbond_poll_in()
171 *p_char = config->regs->UART2_RBR_THR_DLL_REG; in uart_smartbond_poll_in()
187 while (!(config->regs->UART2_USR_REG & UART2_UART2_USR_REG_UART_TFNF_Msk)) { in uart_smartbond_poll_out()
191 config->regs->UART2_RBR_THR_DLL_REG = out_char; in uart_smartbond_poll_out()
208 config->regs->UART2_MCR_REG = data->runtime_cfg.mcr_reg_val; in apply_runtime_config()
209 config->regs->UART2_SRR_REG = UART2_UART2_SRR_REG_UART_UR_Msk | in apply_runtime_config()
214 config->regs->UART2_LCR_REG |= UART2_UART2_LCR_REG_UART_DLAB_Msk; in apply_runtime_config()
215 config->regs->UART2_IER_DLH_REG = BAUDRATE_CFG_DLH(data->runtime_cfg.baudrate_cfg); in apply_runtime_config()
216 config->regs->UART2_RBR_THR_DLL_REG = BAUDRATE_CFG_DLL(data->runtime_cfg.baudrate_cfg); in apply_runtime_config()
[all …]
|
| D | uart_sam.c | 26 Uart *regs; member
49 Uart * const uart = cfg->regs; in uart_sam_poll_in()
65 Uart * const uart = cfg->regs; in uart_sam_poll_out()
79 volatile Uart * const uart = cfg->regs; in uart_sam_err_check()
105 volatile Uart * const uart = cfg->regs; in uart_sam_baudrate_set()
147 volatile Uart * const uart = cfg->regs; in uart_sam_get_parity()
171 volatile Uart * const uart = config->regs; in uart_sam_configure()
226 volatile Uart * const uart = cfg->regs; in uart_sam_fifo_fill()
242 volatile Uart * const uart = cfg->regs; in uart_sam_fifo_read()
263 volatile Uart * const uart = cfg->regs; in uart_sam_irq_tx_enable()
[all …]
|
| D | usart_sam.c | 26 Usart *regs; member
50 Usart * const usart = config->regs; in usart_sam_poll_in()
66 Usart * const usart = config->regs; in usart_sam_poll_out()
80 volatile Usart * const usart = config->regs; in usart_sam_err_check()
104 volatile Usart * const usart = config->regs; in usart_sam_baudrate_set()
146 volatile Usart * const usart = config->regs; in usart_sam_get_parity()
180 volatile Usart * const usart = config->regs; in usart_sam_get_stop_bits()
212 volatile Usart * const usart = config->regs; in usart_sam_get_data_bits()
242 volatile Usart * const usart = config->regs; in usart_sam_get_flow_ctrl()
260 volatile Usart * const usart = config->regs; in usart_sam_configure()
[all …]
|
| D | uart_renesas_ra_sci.c | 37 R_SCI0_Type * const regs; member
87 if (IS_ENABLED(CONFIG_UART_ASYNC_API) && cfg->regs->SCR_b.RIE) { in uart_ra_sci_poll_in()
93 ? cfg->regs->FDR_b.R == 0U in uart_ra_sci_poll_in()
94 : cfg->regs->SSR_b.RDRF == 0U) { in uart_ra_sci_poll_in()
101 ? cfg->regs->FRDRL in uart_ra_sci_poll_in()
102 : cfg->regs->RDR; in uart_ra_sci_poll_in()
114 while (cfg->regs->FDR_b.T > 0x8) { in uart_ra_sci_poll_out()
116 cfg->regs->FTDRL = c; in uart_ra_sci_poll_out()
120 while (cfg->regs->SSR_b.TDRE == 0U) { in uart_ra_sci_poll_out()
122 cfg->regs->TDR = c; in uart_ra_sci_poll_out()
[all …]
|
| /Zephyr-latest/drivers/dma/ |
| D | dma_mchp_xec.c | 112 struct dma_xec_regs *regs; member
153 static inline struct dma_xec_chan_regs *xec_chan_regs(struct dma_xec_regs *regs, uint32_t chan) in xec_chan_regs() argument
155 uint8_t *pregs = (uint8_t *)regs + XEC_DMA_MAIN_REGS_SIZE; in xec_chan_regs()
339 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_configure() local
353 struct dma_xec_chan_regs * const chregs = xec_chan_regs(regs, channel); in dma_xec_configure()
456 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_reload() local
464 struct dma_xec_chan_regs *chregs = xec_chan_regs(regs, channel); in dma_xec_reload()
499 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_start() local
506 struct dma_xec_chan_regs *chregs = xec_chan_regs(regs, channel); in dma_xec_start()
532 struct dma_xec_regs * const regs = devcfg->regs; in dma_xec_stop() local
[all …]
|
| D | dma_smartbond.c | 168 struct channel_regs *regs; in dma_smartbond_is_dma_active() local
171 regs = DMA_CHN2REG(idx); in dma_smartbond_is_dma_active()
173 if (DMA_CTRL_REG_GET_FIELD(DMA_ON, regs->DMA_CTRL_REG)) { in dma_smartbond_is_dma_active()
201 struct channel_regs *regs = DMA_CHN2REG(channel); in dma_smartbond_set_channel_status() local
218 DMA_CTRL_REG_SET_FIELD(DMA_ON, regs->DMA_CTRL_REG, 0x1); in dma_smartbond_set_channel_status()
220 DMA_CTRL_REG_SET_FIELD(DMA_ON, regs->DMA_CTRL_REG, 0x0); in dma_smartbond_set_channel_status()
226 while (DMA_CTRL_REG_GET_FIELD(DMA_ON, regs->DMA_CTRL_REG)) { in dma_smartbond_set_channel_status()
488 struct channel_regs *regs; in dma_smartbond_config() local
496 regs = DMA_CHN2REG(channel); in dma_smartbond_config()
498 dma_ctrl_reg = regs->DMA_CTRL_REG; in dma_smartbond_config()
[all …]
|
| /Zephyr-latest/drivers/counter/ |
| D | counter_sam0_tc32.c | 32 TcCount32 *regs; member
47 static void wait_synchronization(TcCount32 *regs) in wait_synchronization() argument
51 while ((regs->SYNCBUSY.reg & TC_SYNCBUSY_MASK) != 0) { in wait_synchronization()
55 while ((regs->STATUS.reg & TC_STATUS_SYNCBUSY) != 0) { in wait_synchronization()
62 static void read_synchronize_count(TcCount32 *regs) in read_synchronize_count() argument
65 regs->READREQ.reg = TC_READREQ_RREQ | in read_synchronize_count()
67 wait_synchronization(regs); in read_synchronize_count()
69 regs->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC; in read_synchronize_count()
70 wait_synchronization(regs); in read_synchronize_count()
72 ARG_UNUSED(regs); in read_synchronize_count()
[all …]
|
| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_smartbond.c | 131 struct smartbond_ep_reg_set *regs; member
369 struct smartbond_ep_reg_set *regs = ep_state->regs; in fill_tx_fifo() local
381 while ((regs->txs & USB_USB_TXS1_REG_USB_TCOUNT_Msk) > 0 && in fill_tx_fifo()
383 regs->txd = *src++; in fill_tx_fifo()
394 regs->txc |= (3 << USB_USB_TXC1_REG_USB_TFWL_Pos); in fill_tx_fifo()
398 regs->txc &= ~USB_USB_TXC1_REG_USB_TFWL_Msk; in fill_tx_fifo()
404 regs->txc |= USB_USB_TXC1_REG_USB_LAST_Msk; in fill_tx_fifo()
444 struct smartbond_ep_reg_set *regs = ep_state->regs; in start_rx_packet() local
454 start_rx_dma(®s->rxd, in start_rx_packet()
465 regs->rxc |= USB_USB_RXC1_REG_USB_RFWL_Msk; in start_rx_packet()
[all …]
|
| /Zephyr-latest/drivers/spi/ |
| D | spi_smartbond.c | 57 SPI_Type *regs; member
106 cfg->regs->SPI_CTRL_REG |= SPI_SPI_CTRL_REG_SPI_ON_Msk; in spi_smartbond_enable()
107 cfg->regs->SPI_CTRL_REG &= ~SPI_SPI_CTRL_REG_SPI_RST_Msk; in spi_smartbond_enable()
109 cfg->regs->SPI_CTRL_REG &= ~SPI_SPI_CTRL_REG_SPI_ON_Msk; in spi_smartbond_enable()
110 cfg->regs->SPI_CTRL_REG |= SPI_SPI_CTRL_REG_SPI_RST_Msk; in spi_smartbond_enable()
116 return (!!(cfg->regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_ON_Msk)) && in spi_smartbond_isenabled()
117 (!(cfg->regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_RST_Msk)); in spi_smartbond_isenabled()
131 cfg->regs->SPI_RX_TX_REG = *(uint8_t *)data->ctx.tx_buf; in spi_smartbond_write_word()
134 cfg->regs->SPI_RX_TX_REG = sys_get_le16(data->ctx.tx_buf); in spi_smartbond_write_word()
137 cfg->regs->SPI_RX_TX_REG = sys_get_le32(data->ctx.tx_buf); in spi_smartbond_write_word()
[all …]
|
| /Zephyr-latest/drivers/w1/ |
| D | w1_max32.c | 20 mxc_owm_regs_t *regs; member
38 mxc_owm_regs_t *regs = cfg->regs; in api_reset_bus() local
44 if (regs->ctrl_stat & MXC_F_OWM_CTRL_STAT_OW_INPUT) { in api_reset_bus()
132 mxc_owm_regs_t *regs = dev_config->regs; in api_configure() local
135 regs->cfg |= MXC_F_OWM_CFG_EXT_PULLUP_MODE; in api_configure()
137 regs->cfg &= ~MXC_F_OWM_CFG_EXT_PULLUP_MODE; in api_configure()
193 .regs = (mxc_owm_regs_t *)DT_INST_REG_ADDR(_num), \
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_mchp_ecia_xec.c | 86 struct ecia_regs *regs = ECIA_XEC_REG_BASE; in mchp_xec_ecia_girq_aggr_en() local
89 regs->BLK_EN_SET = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
91 regs->BLK_EN_CLR = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
101 struct ecia_regs *regs = ECIA_XEC_REG_BASE; in mchp_xec_ecia_girq_src_clr() local
104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()
113 struct ecia_regs *regs = ECIA_XEC_REG_BASE; in mchp_xec_ecia_girq_src_en() local
116 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_en()
125 struct ecia_regs *regs = ECIA_XEC_REG_BASE; in mchp_xec_ecia_girq_src_dis() local
128 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_dis()
137 struct ecia_regs *regs = ECIA_XEC_REG_BASE; in mchp_xec_ecia_girq_src_clr_bitmap() local
[all …]
|
| /Zephyr-latest/drivers/mdio/ |
| D | mdio_xmc4xxx.c | 46 ETH_GLOBAL_TypeDef *const regs; member
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer() local
62 if ((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) { in mdio_xmc4xxx_transfer()
70 regs->GMII_DATA = data_write; in mdio_xmc4xxx_transfer()
73 regs->GMII_ADDRESS = reg | ETH_GMII_ADDRESS_MB_Msk | in mdio_xmc4xxx_transfer()
77 if (!WAIT_FOR((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0, in mdio_xmc4xxx_transfer()
85 *data_read = regs->GMII_DATA; in mdio_xmc4xxx_transfer()
176 .regs = (ETH_GLOBAL_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(0)),
|
