1 /*
2 * Copyright (c) 2023-2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT adi_max32_pwm
8
9 #include <errno.h>
10 #include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
11 #include <zephyr/drivers/pwm.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/sys/util_macro.h>
14
15 #include <wrap_max32_tmr.h>
16
17 #include <zephyr/logging/log.h>
18
19 LOG_MODULE_REGISTER(pwm_max32, CONFIG_PWM_LOG_LEVEL);
20
21 /** PWM configuration. */
22 struct max32_pwm_config {
23 mxc_tmr_regs_t *regs;
24 const struct pinctrl_dev_config *pctrl;
25 const struct device *clock;
26 struct max32_perclk perclk;
27 int prescaler;
28 };
29
30 /** PWM data. */
31 struct max32_pwm_data {
32 uint32_t period_cycles;
33 };
34
api_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)35 static int api_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles,
36 uint32_t pulse_cycles, pwm_flags_t flags)
37 {
38 int ret = 0;
39 const struct max32_pwm_config *cfg = dev->config;
40 mxc_tmr_regs_t *regs = cfg->regs;
41 wrap_mxc_tmr_cfg_t pwm_cfg;
42 int prescaler_index;
43
44 prescaler_index = LOG2(cfg->prescaler);
45 if (prescaler_index == 0) {
46 pwm_cfg.pres = TMR_PRES_1; /* TMR_PRES_1 is 0 */
47 } else {
48 /* TMR_PRES_2 is 1<<X */
49 pwm_cfg.pres = TMR_PRES_2 + (prescaler_index - 1);
50 }
51 pwm_cfg.mode = TMR_MODE_PWM;
52 pwm_cfg.cmp_cnt = period_cycles;
53 pwm_cfg.bitMode = 0; /* Timer Mode 32 bit */
54
55 if (pulse_cycles == 0) {
56 /* Special case to handle duty_cycle=0 case */
57 pulse_cycles = period_cycles;
58 pwm_cfg.pol = (flags & PWM_POLARITY_MASK) ? 1 : 0;
59 } else {
60 pwm_cfg.pol = (flags & PWM_POLARITY_MASK) ? 0 : 1;
61 }
62
63 pwm_cfg.clock = Wrap_MXC_TMR_GetClockIndex(cfg->perclk.clk_src);
64 if (pwm_cfg.clock < 0) {
65 return -ENOTSUP;
66 }
67
68 MXC_TMR_Shutdown(regs);
69
70 /* enable clock */
71 ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
72 if (ret) {
73 return ret;
74 }
75
76 ret = Wrap_MXC_TMR_Init(regs, &pwm_cfg);
77 if (ret != E_NO_ERROR) {
78 return ret;
79 }
80
81 ret = MXC_TMR_SetPWM(regs, pulse_cycles);
82 if (ret != E_NO_ERROR) {
83 return -EINVAL;
84 }
85
86 MXC_TMR_Start(regs);
87
88 return 0;
89 }
90
api_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)91 static int api_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
92 {
93 int ret = 0;
94 const struct max32_pwm_config *cfg = dev->config;
95 uint32_t clk_frequency = 0;
96
97 ret = clock_control_get_rate(cfg->clock, (clock_control_subsys_t)&cfg->perclk,
98 &clk_frequency);
99 if (clk_frequency == 0) {
100 return -ENOTSUP; /* Unsupported clock source */
101 }
102
103 *cycles = (uint64_t)(clk_frequency / cfg->prescaler);
104
105 return ret;
106 }
107
108 static DEVICE_API(pwm, pwm_max32_driver_api) = {
109 .set_cycles = api_set_cycles,
110 .get_cycles_per_sec = api_get_cycles_per_sec,
111 };
112
pwm_max32_init(const struct device * dev)113 static int pwm_max32_init(const struct device *dev)
114 {
115 int ret = 0;
116 const struct max32_pwm_config *cfg = dev->config;
117
118 ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
119 if (ret) {
120 LOG_ERR("PWM pinctrl initialization failed (%d)", ret);
121 }
122
123 return ret;
124 }
125
126 #define PWM_MAX32_DEFINE(_num) \
127 static struct max32_pwm_data max32_pwm_data_##_num; \
128 PINCTRL_DT_INST_DEFINE(_num); \
129 static const struct max32_pwm_config max32_pwm_config_##_num = { \
130 .regs = (mxc_tmr_regs_t *)DT_REG_ADDR(DT_INST_PARENT(_num)), \
131 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
132 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(_num))), \
133 .perclk.bus = DT_CLOCKS_CELL(DT_INST_PARENT(_num), offset), \
134 .perclk.bit = DT_CLOCKS_CELL(DT_INST_PARENT(_num), bit), \
135 .perclk.clk_src = DT_PROP(DT_INST_PARENT(_num), clock_source), \
136 .prescaler = DT_PROP(DT_INST_PARENT(_num), prescaler), \
137 }; \
138 DEVICE_DT_INST_DEFINE(_num, &pwm_max32_init, NULL, &max32_pwm_data_##_num, \
139 &max32_pwm_config_##_num, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
140 &pwm_max32_driver_api);
141
142 DT_INST_FOREACH_STATUS_OKAY(PWM_MAX32_DEFINE)
143
