37 	R_SCI0_Type * const regs;  member
87 	if (IS_ENABLED(CONFIG_UART_ASYNC_API) && cfg->regs->SCR_b.RIE) {  in uart_ra_sci_poll_in()
93 		    ? cfg->regs->FDR_b.R == 0U  in uart_ra_sci_poll_in()
94 		    : cfg->regs->SSR_b.RDRF == 0U) {  in uart_ra_sci_poll_in()
101 		     ? cfg->regs->FRDRL  in uart_ra_sci_poll_in()
102 		     : cfg->regs->RDR;  in uart_ra_sci_poll_in()
114 		while (cfg->regs->FDR_b.T > 0x8) {  in uart_ra_sci_poll_out()
116 		cfg->regs->FTDRL = c;  in uart_ra_sci_poll_out()
120 		while (cfg->regs->SSR_b.TDRE == 0U) {  in uart_ra_sci_poll_out()
122 		cfg->regs->TDR = c;  in uart_ra_sci_poll_out()
134 		const uint8_t status = cfg->regs->SSR_FIFO;  in uart_ra_sci_err_check()
149 		cfg->regs->SSR_FIFO &= ~ssr_fifo;  in uart_ra_sci_err_check()
153 		const uint8_t status = cfg->regs->SSR;  in uart_ra_sci_err_check()
168 		cfg->regs->SSR &= ~ssr;  in uart_ra_sci_err_check()
308 		while ((size - num_tx > 0) && cfg->regs->FDR_b.T < data->sci.fifo_depth) {  in uart_ra_sci_fifo_fill()
310 			cfg->regs->FTDRL = tx_data[num_tx++];  in uart_ra_sci_fifo_fill()
312 		cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_TDFE_TEND;  in uart_ra_sci_fifo_fill()
316 		if (size > 0 && cfg->regs->SSR_b.TDRE) {  in uart_ra_sci_fifo_fill()
318 			cfg->regs->TDR = tx_data[num_tx++];  in uart_ra_sci_fifo_fill()
333 		while ((size - num_rx > 0) && cfg->regs->FDR_b.R > 0) {  in uart_ra_sci_fifo_read()
335 			rx_data[num_rx++] = cfg->regs->FRDRL;  in uart_ra_sci_fifo_read()
337 		cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_DR_RDF;  in uart_ra_sci_fifo_read()
341 		if (size > 0 && cfg->regs->SSR_b.RDRF) {  in uart_ra_sci_fifo_read()
343 			rx_data[num_rx++] = cfg->regs->RDR;  in uart_ra_sci_fifo_read()
345 		cfg->regs->SSR &= (uint8_t)~R_SCI0_SSR_RDRF_Msk;  in uart_ra_sci_fifo_read()
357 		cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_TDFE_TEND;  in uart_ra_sci_irq_tx_enable()
361 		cfg->regs->SSR = (uint8_t)~SCI_UART_SSR_TDRE_TEND;  in uart_ra_sci_irq_tx_enable()
364 	cfg->regs->SCR |= (R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk);  in uart_ra_sci_irq_tx_enable()
371 	cfg->regs->SCR &= ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk);  in uart_ra_sci_irq_tx_disable()
382 		ret = (cfg->regs->SCR_b.TIE == 1U) && (data->ssr & R_SCI0_SSR_FIFO_TDFE_Msk);  in uart_ra_sci_irq_tx_ready()
386 		ret = (cfg->regs->SCR_b.TIE == 1U) && (data->ssr & R_SCI0_SSR_TDRE_Msk);  in uart_ra_sci_irq_tx_ready()
397 	return (cfg->regs->SCR_b.TEIE == 1U) && (data->ssr & BIT(R_SCI0_SSR_TEND_Pos));  in uart_ra_sci_irq_tx_complete()
407 		cfg->regs->SSR_FIFO &= (uint8_t) ~(SCI_UART_SSR_FIFO_DR_RDF);  in uart_ra_sci_irq_rx_enable()
411 		cfg->regs->SSR_b.RDRF = 0U;  in uart_ra_sci_irq_rx_enable()
413 	cfg->regs->SCR_b.RIE = 1U;  in uart_ra_sci_irq_rx_enable()
420 	cfg->regs->SCR_b.RIE = 0U;  in uart_ra_sci_irq_rx_disable()
431 		ret = (cfg->regs->SCR_b.RIE == 1U) && (data->ssr & SCI_UART_SSR_FIFO_DR_RDF);  in uart_ra_sci_irq_rx_ready()
435 		ret = (cfg->regs->SCR_b.RIE == 1U) && (data->ssr & R_SCI0_SSR_RDRF_Msk);  in uart_ra_sci_irq_rx_ready()
465 		scr = cfg->regs->SCR;  in uart_ra_sci_irq_is_pending()
466 		ssr = cfg->regs->SSR_FIFO;  in uart_ra_sci_irq_is_pending()
476 		scr = cfg->regs->SCR;  in uart_ra_sci_irq_is_pending()
477 		ssr = cfg->regs->SSR;  in uart_ra_sci_irq_is_pending()
495 		data->ssr = cfg->regs->SSR_FIFO;  in uart_ra_sci_irq_update()
498 		cfg->regs->SSR_FIFO &= ssr;  in uart_ra_sci_irq_update()
502 		data->ssr = cfg->regs->SSR;  in uart_ra_sci_irq_update()
505 		cfg->regs->SSR_FIFO &= ssr;  in uart_ra_sci_irq_update()
634 	cfg->regs->SCR_b.RIE = 0;  in async_rx_disable()
637 		cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_DR_RDF;  in async_rx_disable()
641 		cfg->regs->SSR_b.RDRF = 0;  in async_rx_disable()
670 	cfg->regs->SCR &= (uint8_t) ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk);  in disable_tx()
677 		       ? cfg->regs->SSR_FIFO_b.TEND != 1U  in disable_tx()
678 		       : cfg->regs->SSR_b.TEND != 1U) {  in disable_tx()
681 	cfg->regs->SCR_b.TE = 0;  in disable_tx()
688 	cfg->regs->SCR_b.TE = 1;  in enable_tx()
742 		cfg->regs->SSR_FIFO &= (uint8_t) ~(SCI_UART_SSR_FIFO_ERR_MSK);  in uart_ra_sci_async_rx_enable()
746 		cfg->regs->SSR = (uint8_t)~SCI_UART_SSR_ERR_MSK;  in uart_ra_sci_async_rx_enable()
762 	cfg->regs->SCR_b.RIE = 1;  in uart_ra_sci_async_rx_enable()
1173 		.regs = (R_SCI0_Type *)DT_REG_ADDR(DT_INST_PARENT(index)),                         \