| /Zephyr-latest/drivers/ipm/ |
| D | ipm_stm32_hsem.c | 37 struct stm32_pclken pclken; member
168 if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) { in stm32_hsem_mailbox_init()
197 .pclken = {
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| D | ipm_stm32_ipcc.c | 91 struct stm32_pclken pclken; member
256 (clock_control_subsys_t)&cfg->pclken) != 0) { in stm32_ipcc_mailbox_init()
293 .pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
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| /Zephyr-latest/drivers/dac/ |
| D | dac_stm32.c | 48 struct stm32_pclken pclken; member
156 (clock_control_subsys_t) &cfg->pclken) != 0) { in dac_stm32_init()
182 .pclken = { \
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_ll_stm32.c | 92 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[1], in i2c_stm32_runtime_configure()
98 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[0], in i2c_stm32_runtime_configure()
110 ret = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]); in i2c_stm32_runtime_configure()
128 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]); in i2c_stm32_runtime_configure()
338 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]); in i2c_stm32_suspend()
373 (clock_control_subsys_t) &cfg->pclken[0]) != 0) { in i2c_stm32_activate()
414 (clock_control_subsys_t) &cfg->pclken[1], in i2c_stm32_init()
599 .pclken = pclken_##index, \
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| D | i2c_ll_stm32.h | 42 const struct stm32_pclken *pclken; member
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_wwdg_stm32.h | 26 struct stm32_pclken pclken; member
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| D | wdt_wwdg_stm32.c | 96 if (clock_control_get_rate(clk, (clock_control_subsys_t) &cfg->pclken, in wwdg_stm32_get_pclk()
290 if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) { in wwdg_stm32_init()
307 .pclken = {
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| /Zephyr-latest/drivers/mbox/ |
| D | mbox_stm32_hsem.c | 49 struct stm32_pclken pclken; member
51 .pclken = {
210 if (clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken) != 0) { in mbox_stm32_clock_init()
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_dwmac_stm32h7x.c | 35 static const struct stm32_pclken pclken = { variable
60 ret = clock_control_on(p->clock, (clock_control_subsys_t)&pclken); in dwmac_bus_init()
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| D | eth_stm32_hal_priv.h | 35 struct stm32_pclken pclken; member
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| /Zephyr-latest/drivers/counter/ |
| D | counter_ll_stm32_rtc.c | 96 const struct stm32_pclken *pclken; member
193 if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) { in rtc_stm32_start()
216 if (clock_control_off(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) { in rtc_stm32_stop()
564 if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) { in rtc_stm32_init()
578 (clock_control_subsys_t) &cfg->pclken[1], in rtc_stm32_init()
647 .pclken = rtc_clk,
660 if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) { in rtc_stm32_pm_action()
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| D | counter_ll_stm32_timer.c | 107 struct stm32_pclken pclken; member
368 static int counter_stm32_get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk) in counter_stm32_get_tim_clk() argument
380 r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken, in counter_stm32_get_tim_clk()
390 if (pclken->bus == STM32_CLOCK_BUS_APB1) { in counter_stm32_get_tim_clk()
396 if (pclken->bus == STM32_CLOCK_BUS_APB1) { in counter_stm32_get_tim_clk()
477 (clock_control_subsys_t)&cfg->pclken); in counter_stm32_init_timer()
482 r = counter_stm32_get_tim_clk(&cfg->pclken, &tim_clk); in counter_stm32_init_timer()
665 .pclken = { \
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| /Zephyr-latest/drivers/crypto/ |
| D | crypto_stm32_priv.h | 22 struct stm32_pclken pclken; member
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_stm32.c | 90 struct stm32_pclken *pclken; member
112 .pclken = pclken_rng
149 (clock_control_subsys_t) &dev_cfg->pclken[0], in entropy_stm32_suspend()
161 (clock_control_subsys_t)&dev_cfg->pclken[0]); in entropy_stm32_suspend()
179 (clock_control_subsys_t)&dev_cfg->pclken[0]); in entropy_stm32_resume()
767 (clock_control_subsys_t)&dev_cfg->pclken[0]); in entropy_stm32_rng_init()
773 (clock_control_subsys_t)&dev_cfg->pclken[1], in entropy_stm32_rng_init()
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| /Zephyr-latest/drivers/can/ |
| D | can_stm32_fdcan.c | 172 const struct stm32_pclken *pclken; member
417 (clock_control_subsys_t) &stm32fd_cfg->pclken[1], in can_stm32fd_get_core_clock()
424 (clock_control_subsys_t) &stm32fd_cfg->pclken[0], in can_stm32fd_get_core_clock()
453 (clock_control_subsys_t)&stm32fd_cfg->pclken[1], in can_stm32fd_clock_enable()
461 ret = clock_control_on(clk, (clock_control_subsys_t)&stm32fd_cfg->pclken[0]); in can_stm32fd_clock_enable()
606 .pclken = can_stm32fd_pclken_##inst, \
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| /Zephyr-latest/drivers/i2s/ |
| D | i2s_ll_stm32.h | 18 const struct stm32_pclken *pclken; member
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_stm32.c | 93 struct stm32_pclken pclken; member
223 static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk) in get_tim_clk() argument
231 r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken, in get_tim_clk()
241 if (pclken->bus == STM32_CLOCK_BUS_APB1) { in get_tim_clk()
247 if (pclken->bus == STM32_CLOCK_BUS_APB1) { in get_tim_clk()
797 r = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken); in pwm_stm32_init()
803 r = get_tim_clk(&cfg->pclken, &data->tim_clk); in pwm_stm32_init()
903 .pclken = DT_INST_CLK(index, timer), \
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| /Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_spi_stm32.c | 159 const struct stm32_pclken *pclken; member
210 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(id); \
215 .pclken = pclken, \
341 (clock_control_subsys_t)&hc_spi->spi_config->pclken[0]); in spi_init()
351 (clock_control_subsys_t)&hc_spi->spi_config->pclken[1], NULL); in spi_init()
838 (clock_control_subsys_t)&cfg->pclken[0]); in ec_host_cmd_spi_stm32_pm_action()
862 (clock_control_subsys_t)&cfg->pclken[0]); in ec_host_cmd_spi_stm32_pm_action()
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| /Zephyr-latest/drivers/serial/ |
| D | uart_stm32.h | 28 const struct stm32_pclken *pclken; member
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| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32_xspi.h | 70 const struct stm32_pclken *pclken; member
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| /Zephyr-latest/drivers/disk/ |
| D | sdmmc_stm32.c | 85 struct stm32_pclken *pclken; member
146 (clock_control_subsys_t)&priv->pclken[1], in stm32_sdmmc_clock_enable()
157 (clock_control_subsys_t)&priv->pclken[1], in stm32_sdmmc_clock_enable()
170 return clock_control_on(clock, (clock_control_subsys_t)&priv->pclken[0]); in stm32_sdmmc_clock_enable()
181 (clock_control_subsys_t)&priv->pclken); in stm32_sdmmc_clock_disable()
813 .pclken = pclken_sdmmc,
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| /Zephyr-latest/drivers/dma/ |
| D | dmamux_stm32.c | 50 struct stm32_pclken pclken; member
260 (clock_control_subsys_t) &config->pclken) != 0) { in dmamux_stm32_init()
370 (.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \
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| D | dma_stm32_bdma.h | 39 struct stm32_pclken pclken; member
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| /Zephyr-latest/drivers/adc/ |
| D | adc_stm32.c | 188 const struct stm32_pclken *pclken; member
466 (clock_control_subsys_t) &config->pclken[0], &adc_rate) < 0) { in adc_stm32_calibration_delay()
1438 clk_src = (clock_control_subsys_t)(adc_stm32_is_clk_sync(config) ? &config->pclken[0]
1439 : &config->pclken[1]);
1492 (clock_control_subsys_t) &config->pclken[0]) != 0) {
1499 (clock_control_subsys_t) &config->pclken[1],
1705 err = clock_control_off(clk, (clock_control_subsys_t)&config->pclken[0]);
1939 .pclken = pclken_##index, \
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| /Zephyr-latest/drivers/video/ |
| D | video_stm32_dcmi.c | 52 struct stm32_pclken pclken; member
188 err = clock_control_on(dcmi_clock, (clock_control_subsys_t *) &config->pclken); in stm32_dcmi_enable_clock()
462 .pclken = {
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