1 /* 2 * Copyright (c) 2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_FLASH_XSPI_STM32_H_ 8 #define ZEPHYR_DRIVERS_FLASH_XSPI_STM32_H_ 9 10 /* Macro to check if any xspi device has a domain clock or more */ 11 #define STM32_XSPI_DOMAIN_CLOCK_INST_SUPPORT(inst) \ 12 DT_CLOCKS_HAS_IDX(DT_INST_PARENT(inst), 1) || 13 #define STM32_XSPI_INST_DEV_DOMAIN_CLOCK_SUPPORT \ 14 (DT_INST_FOREACH_STATUS_OKAY(STM32_XSPI_DOMAIN_CLOCK_INST_SUPPORT) 0) 15 16 /* This symbol takes the value 1 if device instance has a domain clock in its dts */ 17 #if STM32_XSPI_INST_DEV_DOMAIN_CLOCK_SUPPORT 18 #define STM32_XSPI_DOMAIN_CLOCK_SUPPORT 1 19 #else 20 #define STM32_XSPI_DOMAIN_CLOCK_SUPPORT 0 21 #endif 22 23 #define STM32_XSPI_FIFO_THRESHOLD 4U 24 25 /* Valid range is [0, 255] */ 26 #define STM32_XSPI_CLOCK_PRESCALER_MIN 0U 27 #define STM32_XSPI_CLOCK_PRESCALER_MAX 255U 28 #define STM32_XSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / ((prescaler) + 1U)) 29 30 /* Max Time value during reset or erase operation */ 31 #define STM32_XSPI_RESET_MAX_TIME 100U 32 #define STM32_XSPI_BULK_ERASE_MAX_TIME 460000U 33 #define STM32_XSPI_SECTOR_ERASE_MAX_TIME 1000U 34 #define STM32_XSPI_SUBSECTOR_4K_ERASE_MAX_TIME 400U 35 #define STM32_XSPI_WRITE_REG_MAX_TIME 40U 36 37 /* used as default value for DTS writeoc */ 38 #define SPI_NOR_WRITEOC_NONE 0xFF 39 40 #if STM32_XSPI_USE_DMA 41 /* Lookup table to set dma priority from the DTS */ 42 static const uint32_t table_priority[] = { 43 DMA_LOW_PRIORITY_LOW_WEIGHT, 44 DMA_LOW_PRIORITY_MID_WEIGHT, 45 DMA_LOW_PRIORITY_HIGH_WEIGHT, 46 DMA_HIGH_PRIORITY, 47 }; 48 49 /* Lookup table to set dma channel direction from the DTS */ 50 static const uint32_t table_direction[] = { 51 DMA_MEMORY_TO_MEMORY, 52 DMA_MEMORY_TO_PERIPH, 53 DMA_PERIPH_TO_MEMORY, 54 }; 55 56 struct stream { 57 DMA_TypeDef *reg; 58 const struct device *dev; 59 uint32_t channel; 60 struct dma_config cfg; 61 uint8_t priority; 62 bool src_addr_increment; 63 bool dst_addr_increment; 64 }; 65 #endif /* STM32_XSPI_USE_DMA */ 66 67 typedef void (*irq_config_func_t)(const struct device *dev); 68 69 struct flash_stm32_xspi_config { 70 const struct stm32_pclken *pclken; 71 size_t pclk_len; 72 irq_config_func_t irq_config; 73 size_t flash_size; 74 uint32_t max_frequency; 75 int data_mode; /* SPI or QSPI or OSPI */ 76 int data_rate; /* DTR or STR */ 77 const struct pinctrl_dev_config *pcfg; 78 #if STM32_XSPI_RESET_GPIO 79 const struct gpio_dt_spec reset; 80 #endif /* STM32_XSPI_RESET_GPIO */ 81 }; 82 83 struct flash_stm32_xspi_data { 84 /* XSPI handle is modifiable ; so part of data struct */ 85 XSPI_HandleTypeDef hxspi; 86 struct k_sem sem; 87 struct k_sem sync; 88 #if defined(CONFIG_FLASH_PAGE_LAYOUT) 89 struct flash_pages_layout layout; 90 #endif 91 struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES]; 92 /* Number of bytes per page */ 93 uint16_t page_size; 94 /* Address width in bytes */ 95 uint8_t address_width; 96 /* Read operation dummy cycles */ 97 uint8_t read_dummy; 98 uint32_t read_opcode; 99 uint32_t write_opcode; 100 enum jesd216_mode_type read_mode; 101 enum jesd216_dw15_qer_type qer_type; 102 #if defined(CONFIG_FLASH_JESD216_API) 103 /* Table to hold the jedec Read ID given by the octoFlash const */ 104 uint8_t jedec_id[JESD216_READ_ID_LEN]; 105 #endif /* CONFIG_FLASH_JESD216_API */ 106 int cmd_status; 107 #if STM32_XSPI_USE_DMA 108 struct stream dma_tx; 109 struct stream dma_rx; 110 #endif /* STM32_XSPI_USE_DMA */ 111 }; 112 113 #endif /* ZEPHYR_DRIVERS_FLASH_XSPI_STM32_H_ */ 114
