1 /*
2 * Copyright (c) 2016 BayLibre, SAS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/pm/device.h>
11 #include <zephyr/pm/device_runtime.h>
12 #include <zephyr/pm/policy.h>
13 #include <zephyr/sys/util.h>
14 #include <zephyr/kernel.h>
15 #include <soc.h>
16 #include <stm32_ll_i2c.h>
17 #include <stm32_ll_rcc.h>
18 #include <errno.h>
19 #include <zephyr/drivers/i2c.h>
20 #include <zephyr/drivers/pinctrl.h>
21 #include "i2c_ll_stm32.h"
22
23 #ifdef CONFIG_I2C_STM32_BUS_RECOVERY
24 #include "i2c_bitbang.h"
25 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
26
27 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
28 #include <zephyr/logging/log.h>
29 #include <zephyr/irq.h>
30 LOG_MODULE_REGISTER(i2c_ll_stm32);
31
32 #include "i2c-priv.h"
33
34 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
35 #define DT_DRV_COMPAT st_stm32_i2c_v2
36 #else
37 #define DT_DRV_COMPAT st_stm32_i2c_v1
38 #endif
39
40 /* This symbol takes the value 1 if one of the device instances */
41 /* is configured in dts with a domain clock */
42 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
43 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
44 #else
45 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
46 #endif
47
i2c_stm32_get_config(const struct device * dev,uint32_t * config)48 int i2c_stm32_get_config(const struct device *dev, uint32_t *config)
49 {
50 struct i2c_stm32_data *data = dev->data;
51
52 if (!data->is_configured) {
53 LOG_ERR("I2C controller not configured");
54 return -EIO;
55 }
56
57 *config = data->dev_config;
58
59 #if CONFIG_I2C_STM32_V2_TIMING
60 /* Print the timing parameter of device data */
61 LOG_INF("I2C timing value, report to the DTS :");
62
63 /* I2C BIT RATE */
64 if (data->current_timing.i2c_speed == 100000) {
65 LOG_INF("timings = <%d I2C_BITRATE_STANDARD 0x%X>;",
66 data->current_timing.periph_clock,
67 data->current_timing.timing_setting);
68 } else if (data->current_timing.i2c_speed == 400000) {
69 LOG_INF("timings = <%d I2C_BITRATE_FAST 0x%X>;",
70 data->current_timing.periph_clock,
71 data->current_timing.timing_setting);
72 } else if (data->current_timing.i2c_speed == 1000000) {
73 LOG_INF("timings = <%d I2C_SPEED_FAST_PLUS 0x%X>;",
74 data->current_timing.periph_clock,
75 data->current_timing.timing_setting);
76 }
77 #endif /* CONFIG_I2C_STM32_V2_TIMING */
78
79 return 0;
80 }
81
i2c_stm32_runtime_configure(const struct device * dev,uint32_t config)82 int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
83 {
84 const struct i2c_stm32_config *cfg = dev->config;
85 struct i2c_stm32_data *data = dev->data;
86 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
87 I2C_TypeDef *i2c = cfg->i2c;
88 uint32_t i2c_clock = 0U;
89 int ret;
90
91 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
92 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[1],
93 &i2c_clock) < 0) {
94 LOG_ERR("Failed call clock_control_get_rate(pclken[1])");
95 return -EIO;
96 }
97 } else {
98 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[0],
99 &i2c_clock) < 0) {
100 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
101 return -EIO;
102 }
103 }
104
105 data->dev_config = config;
106
107 k_sem_take(&data->bus_mutex, K_FOREVER);
108
109 #ifdef CONFIG_PM_DEVICE_RUNTIME
110 ret = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]);
111 if (ret < 0) {
112 LOG_ERR("failure Enabling I2C clock");
113 return ret;
114 }
115 #endif
116
117 LL_I2C_Disable(i2c);
118 #if defined(I2C_CR1_SMBUS) || defined(I2C_CR1_SMBDEN) || defined(I2C_CR1_SMBHEN)
119 i2c_stm32_set_smbus_mode(dev, data->mode);
120 #endif
121 ret = stm32_i2c_configure_timing(dev, i2c_clock);
122
123 if (data->smbalert_active) {
124 LL_I2C_Enable(i2c);
125 }
126
127 #ifdef CONFIG_PM_DEVICE_RUNTIME
128 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
129 if (ret < 0) {
130 LOG_ERR("failure disabling I2C clock");
131 return ret;
132 }
133 #endif
134
135 k_sem_give(&data->bus_mutex);
136
137 return ret;
138 }
139
140 #define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK)
141
i2c_stm32_transfer(const struct device * dev,struct i2c_msg * msg,uint8_t num_msgs,uint16_t slave)142 static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
143 uint8_t num_msgs, uint16_t slave)
144 {
145 struct i2c_stm32_data *data = dev->data;
146 struct i2c_msg *current, *next;
147 int ret = 0;
148
149 /* Check for validity of all messages, to prevent having to abort
150 * in the middle of a transfer
151 */
152 current = msg;
153
154 /*
155 * Set I2C_MSG_RESTART flag on first message in order to send start
156 * condition
157 */
158 current->flags |= I2C_MSG_RESTART;
159
160 for (uint8_t i = 1; i <= num_msgs; i++) {
161
162 if (i < num_msgs) {
163 next = current + 1;
164
165 /*
166 * Restart condition between messages
167 * of different directions is required
168 */
169 if (OPERATION(current) != OPERATION(next)) {
170 if (!(next->flags & I2C_MSG_RESTART)) {
171 ret = -EINVAL;
172 break;
173 }
174 }
175
176 /* Stop condition is only allowed on last message */
177 if (current->flags & I2C_MSG_STOP) {
178 ret = -EINVAL;
179 break;
180 }
181 }
182
183 current++;
184 }
185
186 if (ret) {
187 return ret;
188 }
189
190 /* Send out messages */
191 k_sem_take(&data->bus_mutex, K_FOREVER);
192
193 /* Prevent driver from being suspended by PM until I2C transaction is complete */
194 #ifdef CONFIG_PM_DEVICE_RUNTIME
195 (void)pm_device_runtime_get(dev);
196 #endif
197
198 /* Prevent the clocks to be stopped during the i2c transaction */
199 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
200
201 current = msg;
202
203 while (num_msgs > 0) {
204 uint8_t *next_msg_flags = NULL;
205
206 if (num_msgs > 1) {
207 next = current + 1;
208 next_msg_flags = &(next->flags);
209 }
210 ret = stm32_i2c_transaction(dev, *current, next_msg_flags, slave);
211 if (ret < 0) {
212 break;
213 }
214 current++;
215 num_msgs--;
216 }
217
218 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
219
220 #ifdef CONFIG_PM_DEVICE_RUNTIME
221 (void)pm_device_runtime_put(dev);
222 #endif
223
224 k_sem_give(&data->bus_mutex);
225
226 return ret;
227 }
228
229 #if CONFIG_I2C_STM32_BUS_RECOVERY
i2c_stm32_bitbang_set_scl(void * io_context,int state)230 static void i2c_stm32_bitbang_set_scl(void *io_context, int state)
231 {
232 const struct i2c_stm32_config *config = io_context;
233
234 gpio_pin_set_dt(&config->scl, state);
235 }
236
i2c_stm32_bitbang_set_sda(void * io_context,int state)237 static void i2c_stm32_bitbang_set_sda(void *io_context, int state)
238 {
239 const struct i2c_stm32_config *config = io_context;
240
241 gpio_pin_set_dt(&config->sda, state);
242 }
243
i2c_stm32_bitbang_get_sda(void * io_context)244 static int i2c_stm32_bitbang_get_sda(void *io_context)
245 {
246 const struct i2c_stm32_config *config = io_context;
247
248 return gpio_pin_get_dt(&config->sda) == 0 ? 0 : 1;
249 }
250
i2c_stm32_recover_bus(const struct device * dev)251 static int i2c_stm32_recover_bus(const struct device *dev)
252 {
253 const struct i2c_stm32_config *config = dev->config;
254 struct i2c_stm32_data *data = dev->data;
255 struct i2c_bitbang bitbang_ctx;
256 struct i2c_bitbang_io bitbang_io = {
257 .set_scl = i2c_stm32_bitbang_set_scl,
258 .set_sda = i2c_stm32_bitbang_set_sda,
259 .get_sda = i2c_stm32_bitbang_get_sda,
260 };
261 uint32_t bitrate_cfg;
262 int error = 0;
263
264 LOG_ERR("attempting to recover bus");
265
266 if (!gpio_is_ready_dt(&config->scl)) {
267 LOG_ERR("SCL GPIO device not ready");
268 return -EIO;
269 }
270
271 if (!gpio_is_ready_dt(&config->sda)) {
272 LOG_ERR("SDA GPIO device not ready");
273 return -EIO;
274 }
275
276 k_sem_take(&data->bus_mutex, K_FOREVER);
277
278 error = gpio_pin_configure_dt(&config->scl, GPIO_OUTPUT_HIGH);
279 if (error != 0) {
280 LOG_ERR("failed to configure SCL GPIO (err %d)", error);
281 goto restore;
282 }
283
284 error = gpio_pin_configure_dt(&config->sda, GPIO_OUTPUT_HIGH);
285 if (error != 0) {
286 LOG_ERR("failed to configure SDA GPIO (err %d)", error);
287 goto restore;
288 }
289
290 i2c_bitbang_init(&bitbang_ctx, &bitbang_io, (void *)config);
291
292 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate) | I2C_MODE_CONTROLLER;
293 error = i2c_bitbang_configure(&bitbang_ctx, bitrate_cfg);
294 if (error != 0) {
295 LOG_ERR("failed to configure I2C bitbang (err %d)", error);
296 goto restore;
297 }
298
299 error = i2c_bitbang_recover_bus(&bitbang_ctx);
300 if (error != 0) {
301 LOG_ERR("failed to recover bus (err %d)", error);
302 }
303
304 restore:
305 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
306
307 k_sem_give(&data->bus_mutex);
308
309 return error;
310 }
311 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
312
313 static DEVICE_API(i2c, api_funcs) = {
314 .configure = i2c_stm32_runtime_configure,
315 .transfer = i2c_stm32_transfer,
316 .get_config = i2c_stm32_get_config,
317 #if CONFIG_I2C_STM32_BUS_RECOVERY
318 .recover_bus = i2c_stm32_recover_bus,
319 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
320 #if defined(CONFIG_I2C_TARGET)
321 .target_register = i2c_stm32_target_register,
322 .target_unregister = i2c_stm32_target_unregister,
323 #endif
324 #ifdef CONFIG_I2C_RTIO
325 .iodev_submit = i2c_iodev_submit_fallback,
326 #endif
327 };
328
329 #ifdef CONFIG_PM_DEVICE
330
i2c_stm32_suspend(const struct device * dev)331 static int i2c_stm32_suspend(const struct device *dev)
332 {
333 int ret;
334 const struct i2c_stm32_config *cfg = dev->config;
335 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
336
337 /* Disable device clock. */
338 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
339 if (ret < 0) {
340 LOG_ERR("failure disabling I2C clock");
341 return ret;
342 }
343
344 /* Move pins to sleep state */
345 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
346 if (ret == -ENOENT) {
347 /* Warn but don't block suspend */
348 LOG_WRN("I2C pinctrl sleep state not available ");
349 } else if (ret < 0) {
350 return ret;
351 }
352
353 return 0;
354 }
355
356 #endif
357
i2c_stm32_activate(const struct device * dev)358 static int i2c_stm32_activate(const struct device *dev)
359 {
360 int ret;
361 const struct i2c_stm32_config *cfg = dev->config;
362 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
363
364 /* Move pins to active/default state */
365 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
366 if (ret < 0) {
367 LOG_ERR("I2C pinctrl setup failed (%d)", ret);
368 return ret;
369 }
370
371 /* Enable device clock. */
372 if (clock_control_on(clk,
373 (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
374 LOG_ERR("i2c: failure enabling clock");
375 return -EIO;
376 }
377
378 return 0;
379 }
380
381
i2c_stm32_init(const struct device * dev)382 static int i2c_stm32_init(const struct device *dev)
383 {
384 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
385 const struct i2c_stm32_config *cfg = dev->config;
386 uint32_t bitrate_cfg;
387 int ret;
388 struct i2c_stm32_data *data = dev->data;
389 #ifdef CONFIG_I2C_STM32_INTERRUPT
390 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
391 cfg->irq_config_func(dev);
392 #endif
393
394 data->is_configured = false;
395 data->mode = I2CSTM32MODE_I2C;
396
397 /*
398 * initialize mutex used when multiple transfers
399 * are taking place to guarantee that each one is
400 * atomic and has exclusive access to the I2C bus.
401 */
402 k_sem_init(&data->bus_mutex, 1, 1);
403
404 if (!device_is_ready(clk)) {
405 LOG_ERR("clock control device not ready");
406 return -ENODEV;
407 }
408
409 i2c_stm32_activate(dev);
410
411 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
412 /* Enable I2C clock source */
413 ret = clock_control_configure(clk,
414 (clock_control_subsys_t) &cfg->pclken[1],
415 NULL);
416 if (ret < 0) {
417 return -EIO;
418 }
419 }
420
421 #if defined(CONFIG_SOC_SERIES_STM32F1X)
422 /*
423 * Force i2c reset for STM32F1 series.
424 * So that they can enter master mode properly.
425 * Issue described in ES096 2.14.7
426 */
427 I2C_TypeDef *i2c = cfg->i2c;
428
429 LL_I2C_EnableReset(i2c);
430 LL_I2C_DisableReset(i2c);
431 #endif
432
433 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
434
435 ret = i2c_stm32_runtime_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
436 if (ret < 0) {
437 LOG_ERR("i2c: failure initializing");
438 return ret;
439 }
440
441 #ifdef CONFIG_PM_DEVICE_RUNTIME
442 (void)pm_device_runtime_enable(dev);
443 #endif
444
445 data->is_configured = true;
446
447 return 0;
448 }
449
450 #ifdef CONFIG_PM_DEVICE
451
i2c_stm32_pm_action(const struct device * dev,enum pm_device_action action)452 static int i2c_stm32_pm_action(const struct device *dev, enum pm_device_action action)
453 {
454 int err;
455
456 switch (action) {
457 case PM_DEVICE_ACTION_RESUME:
458 err = i2c_stm32_activate(dev);
459 break;
460 case PM_DEVICE_ACTION_SUSPEND:
461 err = i2c_stm32_suspend(dev);
462 break;
463 default:
464 return -ENOTSUP;
465 }
466
467 return err;
468 }
469
470 #endif
471
472 #ifdef CONFIG_SMBUS_STM32_SMBALERT
i2c_stm32_smbalert_set_callback(const struct device * dev,i2c_stm32_smbalert_cb_func_t func,const struct device * cb_dev)473 void i2c_stm32_smbalert_set_callback(const struct device *dev, i2c_stm32_smbalert_cb_func_t func,
474 const struct device *cb_dev)
475 {
476 struct i2c_stm32_data *data = dev->data;
477
478 data->smbalert_cb_func = func;
479 data->smbalert_cb_dev = cb_dev;
480 }
481 #endif /* CONFIG_SMBUS_STM32_SMBALERT */
482
483 #if defined(I2C_CR1_SMBUS) || defined(I2C_CR1_SMBDEN) || defined(I2C_CR1_SMBHEN)
i2c_stm32_set_smbus_mode(const struct device * dev,enum i2c_stm32_mode mode)484 void i2c_stm32_set_smbus_mode(const struct device *dev, enum i2c_stm32_mode mode)
485 {
486 const struct i2c_stm32_config *cfg = dev->config;
487 struct i2c_stm32_data *data = dev->data;
488 I2C_TypeDef *i2c = cfg->i2c;
489
490 data->mode = mode;
491
492 switch (mode) {
493 case I2CSTM32MODE_I2C:
494 LL_I2C_SetMode(i2c, LL_I2C_MODE_I2C);
495 return;
496 #ifdef CONFIG_SMBUS_STM32
497 case I2CSTM32MODE_SMBUSHOST:
498 LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_HOST);
499 return;
500 case I2CSTM32MODE_SMBUSDEVICE:
501 LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_DEVICE);
502 return;
503 case I2CSTM32MODE_SMBUSDEVICEARP:
504 LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_DEVICE_ARP);
505 return;
506 #endif
507 default:
508 LOG_ERR("%s: invalid mode %i", dev->name, mode);
509 return;
510 }
511 }
512 #endif
513
514 #ifdef CONFIG_SMBUS_STM32
i2c_stm32_smbalert_enable(const struct device * dev)515 void i2c_stm32_smbalert_enable(const struct device *dev)
516 {
517 struct i2c_stm32_data *data = dev->data;
518 const struct i2c_stm32_config *cfg = dev->config;
519
520 data->smbalert_active = true;
521 LL_I2C_EnableSMBusAlert(cfg->i2c);
522 LL_I2C_EnableIT_ERR(cfg->i2c);
523 LL_I2C_Enable(cfg->i2c);
524 }
525
i2c_stm32_smbalert_disable(const struct device * dev)526 void i2c_stm32_smbalert_disable(const struct device *dev)
527 {
528 struct i2c_stm32_data *data = dev->data;
529 const struct i2c_stm32_config *cfg = dev->config;
530
531 data->smbalert_active = false;
532 LL_I2C_DisableSMBusAlert(cfg->i2c);
533 LL_I2C_DisableIT_ERR(cfg->i2c);
534 LL_I2C_Disable(cfg->i2c);
535 }
536 #endif /* CONFIG_SMBUS_STM32 */
537
538 /* Macros for I2C instance declaration */
539
540 #ifdef CONFIG_I2C_STM32_INTERRUPT
541
542 #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
543 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
544 do { \
545 IRQ_CONNECT(DT_INST_IRQN(index), \
546 DT_INST_IRQ(index, priority), \
547 stm32_i2c_combined_isr, \
548 DEVICE_DT_INST_GET(index), 0); \
549 irq_enable(DT_INST_IRQN(index)); \
550 } while (false)
551 #else
552 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
553 do { \
554 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
555 DT_INST_IRQ_BY_NAME(index, event, priority),\
556 stm32_i2c_event_isr, \
557 DEVICE_DT_INST_GET(index), 0); \
558 irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
559 \
560 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
561 DT_INST_IRQ_BY_NAME(index, error, priority),\
562 stm32_i2c_error_isr, \
563 DEVICE_DT_INST_GET(index), 0); \
564 irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
565 } while (false)
566 #endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
567
568 #define STM32_I2C_IRQ_HANDLER_DECL(index) \
569 static void i2c_stm32_irq_config_func_##index(const struct device *dev)
570 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
571 .irq_config_func = i2c_stm32_irq_config_func_##index,
572 #define STM32_I2C_IRQ_HANDLER(index) \
573 static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
574 { \
575 STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
576 }
577 #else
578
579 #define STM32_I2C_IRQ_HANDLER_DECL(index)
580 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index)
581 #define STM32_I2C_IRQ_HANDLER(index)
582
583 #endif /* CONFIG_I2C_STM32_INTERRUPT */
584
585 #define STM32_I2C_INIT(index) \
586 STM32_I2C_IRQ_HANDLER_DECL(index); \
587 \
588 IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
589 (static const uint32_t i2c_timings_##index[] = \
590 DT_INST_PROP_OR(index, timings, {});)) \
591 \
592 PINCTRL_DT_INST_DEFINE(index); \
593 \
594 static const struct stm32_pclken pclken_##index[] = \
595 STM32_DT_INST_CLOCKS(index); \
596 \
597 static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
598 .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
599 .pclken = pclken_##index, \
600 .pclk_len = DT_INST_NUM_CLOCKS(index), \
601 STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
602 .bitrate = DT_INST_PROP(index, clock_frequency), \
603 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
604 IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \
605 (.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}),\
606 .sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),))\
607 IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
608 (.timings = (const struct i2c_config_timing *) i2c_timings_##index,\
609 .n_timings = ARRAY_SIZE(i2c_timings_##index),)) \
610 }; \
611 \
612 static struct i2c_stm32_data i2c_stm32_dev_data_##index; \
613 \
614 PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
615 \
616 I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
617 PM_DEVICE_DT_INST_GET(index), \
618 &i2c_stm32_dev_data_##index, \
619 &i2c_stm32_cfg_##index, \
620 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
621 &api_funcs); \
622 \
623 STM32_I2C_IRQ_HANDLER(index)
624
625 DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT)
626
