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/Zephyr-latest/dts/arm/xilinx/
Dzynq7000.dtsi15 ocm_low: memory@1000 {
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
21 ocm_high: memory@fffc0000 {
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
/Zephyr-latest/drivers/usb/udc/
DKconfig26 Total amount of memory available for UDC requests.
29 bool "Place the buffer pools in the nocache memory region"
32 Place the buffer pools in the nocache memory region if the driver
33 cannot handle buffers in cached memory.
/Zephyr-latest/arch/xtensa/core/
DREADME_MMU.txt3 As with other elements of the architecture, paged virtual memory
13 memory. It is partitioned into an automatically managed
24 below) does not, and Zephyr's memory spaces are unified regardless.
56 with which to fill the TLB and use for a (restarted) memory access.
59 memory fetch vs. e.g. the 2-5 fetches required to walk a page table on
62 This special "refill" fetch is otherwise identical to any other memory
65 of virtual, not physical, address space, in the same memory space
67 of which might be mapped in physical memory) are a linear array of
69 virtual memory. Note especially that exactly one of those pages
73 Obviously, the page table memory being virtual means that the fetch
[all …]
/Zephyr-latest/dts/arm/adi/max32/
Dmax32660.dtsi46 sram1: memory@20004000 {
51 sram2: memory@20008000 {
56 sram3: memory@20010000 {
/Zephyr-latest/boards/ezurio/bl5340_dvk/
Dbl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi16 * Secure image will use sram0 for system memory.
19 * sram0_ns for system memory.
45 * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
/Zephyr-latest/drivers/dma/
DKconfig.mcux_lpc22 int "Number of DMA channels to allocate memory for in driver"
25 The MCUX LPC DMA driver can save memory by not allocating static data
26 depending on this value. So, the application can save some data memory
/Zephyr-latest/dts/arm/broadcom/
Dvalkyrie.dtsi29 sram0: memory@400000 {
30 device_type = "memory";
/Zephyr-latest/tests/boards/nrf/dmm/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay47 memory-regions = <&cpuapp_dma_region>;
61 memory-regions = <&dma_fast_region>;
/Zephyr-latest/dts/arm/nuvoton/
Dnpcx7m6fb.dtsi19 sram0: memory@200c0000 {
25 bootloader_ram: memory@200cf800 {
Dnpcx7m6fc.dtsi19 sram0: memory@200c0000 {
25 bootloader_ram: memory@200cf800 {
/Zephyr-latest/boards/qemu/malta/
Dqemu_malta.dts38 sram0: memory@80200000 {
39 device_type = "memory";
/Zephyr-latest/doc/hardware/peripherals/
Dflash.rst12 the flash memory beginning address. This rule shall be applied to
13 all flash controller regular memory that layout is accessible via
/Zephyr-latest/dts/arm/nxp/
Dnxp_mcxw71.dtsi29 compatible = "zephyr,memory-region","mmio-sram";
31 zephyr,memory-region = "RetainedMem";
Dnxp_imx8ml_m7.dtsi47 ocram_sys: memory@20200000 {
48 device_type = "memory";
58 ocram_s_sys: memory@20180000 {
59 device_type = "memory";
65 device_type = "memory";
70 ddr_sys: memory@80200000 {
71 device_type = "memory";
/Zephyr-latest/tests/drivers/uart/uart_errors/boards/
Dnrf54h20dk_nrf54h20_common.dtsi50 memory-regions = <&cpuapp_dma_region>;
59 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/boards/atmel/sam/sam4s_xplained/
Dsam4s_xplained.dts34 compatible = "zephyr,memory-region", "mmio-sram";
35 device_type = "memory";
37 zephyr,memory-region = "SRAM1";
41 compatible = "zephyr,memory-region", "mmio-sram";
42 device_type = "memory";
44 zephyr,memory-region = "SRAM2";
/Zephyr-latest/boards/arduino/giga_r1/
Darduino_giga_r1_stm32h747xx_m7.dts10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
29 compatible = "zephyr,memory-region", "mmio-sram";
30 device_type = "memory";
32 zephyr,memory-region = "SDRAM1";
33 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_cavs25_tgph.dtsi45 sram0: memory@be000000 {
46 device_type = "memory";
51 sram1: memory@be800000 {
52 device_type = "memory";
87 IMR1: memory@b0000000 {
91 zephyr,memory-region = "IMR1";
114 memory = <&sram0>;
121 memory = <&sram0>;
127 memory = <&sram0>;
133 memory = <&sram0>;
/Zephyr-latest/boards/nordic/nrf54h20dk/
Dnrf54h20dk_nrf54h20_cpuapp.dts202 execution-memory = <&cpuppr_code_data>;
203 source-memory = <&cpuppr_code_partition>;
207 execution-memory = <&cpuflpr_code_data>;
208 source-memory = <&cpuflpr_code_partition>;
247 memory-regions = <&cpuapp_dma_region>;
317 memory-regions = <&cpuapp_dma_region>;
321 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/doc/kernel/
Dcode-relocation.rst9 required files and place them in the required memory region. The memory region
13 This script provides a robust way to re-order the memory contents without
21 The memory region and file are given to the :ref:`gen_relocate_app.py` script
56 for data copy operations from ROM to required memory type.
68 argument is the memory where it must be placed.
79 * if the memory is SRAM1, SRAM2, CCD, or AON, then place the full object in the
87 * if the memory type is appended with _DATA, _TEXT, _RODATA or _BSS, only the
88 selected memory is placed in the required memory region.
151 to the ``EXTFLASH`` memory region where it will be executed from (XIP). The
177 destination memory region is configured to allow code execution.
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/
Dstm32h747i_disco_stm32h747xx_m7.overlay8 /* Frame buffer memory when cached causes screen flickering. */
9 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
/Zephyr-latest/boards/qemu/x86/
Dqemu_x86_lakemont.dts34 dram0: memory@DT_DRAM_BASE {
35 device_type = "memory";
/Zephyr-latest/boards/enjoydigital/litex_vexriscv/
Dlitex_vexriscv.dts24 ram0: memory@40000000 {
25 device_type = "memory";
/Zephyr-latest/tests/drivers/uart/uart_elementary/boards/
Dnrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay28 memory-regions = <&cpuapp_dma_region>;
58 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/tests/boot/mcuboot_data_sharing/boards/
Dnrf52840dk_nrf52840.overlay5 compatible = "zephyr,memory-region", "mmio-sram";
7 zephyr,memory-region = "RetainedMem";

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